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9 Block Diagram
9.1.
Main Block Diagram
S5/ S3.3/ S1.8
IF_AGC
IFD_OUT1
Low -IF
IFD_OUT2
SCL
DMD_IIC0
SDA
SIF_OUT
SIF_OUT
Video_OUT (CVBS)
Video_OUT
D/A TUNER
< FE_XRST
IEC
Reset
ENGS9301D5F
Analog AV Input
Analog AV Input
PC
AUDIO OUT
R
L
R
L
Pr
Pb
Y/V
AV1 / YUV1
Side
AV2
CVBS
BD5452AM
BD5452AM
Only C55D
HDMI1
DDC* > STM, Peaks
HPD* < STM
HDMI_5V_DET* > STM
HDMI2
DDC* > STM, Peaks
HPD* < STM
HDMI_5V_DET* > STM
TS-OUT
TS-IN
HS1BCLKIN
HSBCLKOUT
HS0BCLKIN
HS1SYNCIN
HSSYNCOUT
HS0SYNCIN
HS1VALIN
HSVALOUT
HS0VALIN
HS1DIN[0:7]
HSDOUT[0:7]
HS0DIN[0:7]
Cross Stream Switch
S9/S5
DVB-T
FEAIN
A-Chip VDD
DTV Decoder
SIFIN
ADC
VIF Decoder
SIF Decoder
P-IIC
Video Input
RGB /YPbPr /CVBS /YC
R1, G1, B1, V1
HS,VS
AV-SW
V-SW
ADC
Analog Video
(Thru)
DAC
Processor
CVBS
VDAC1
R2A11023FT
(W/O EU)
LIN1_R, LIN1_L
Audio Input
Main Audio L/R
Monitor OUT L/R
Audio OUT L/R
SCART Out L/R
LO1_R, LO1_L
A-SW
Monitor Out L/R
ADC
(Thru)
(Audio L/R)
LO2_R, LO2_L
HP1_R, HP1_L
DAC
SOUND_VCC
SOUND_VCC
ASMCK
AS
A A MCK
I2S
I2S
ALRC
ALRCLKO
R LKO
K K
ABCKO
ABCKO
K K
AMP
AMP
A A DOUT2
AS
ASDOUT2
A-Chip
SOUND_VCC
PWM0LP
PWM
PWM0LN
PWM0RP
AMP
PWM0RN
LV4923V
S3.3
IECOUT
ARC Buffer-SW
ARC_OFF <
Rx*
Rx*
HDMI
Rx
MUX
x3
CPU BUS
CTRL
ADR
DATA
S5/ S3.3
XNMIRQ
XIRQ1
XECS1
XERE
XEAS
XEWE0
ECLK
ESZ0
ESZ1
XEDK
XEWE1
Support
BOOTSWAP
ERXW
(XRST)
Card
EA[7:0],EA[24]
< TV_SOS
AMP/HP MUTE
MONITOROUT MUTE
ED[15:0]
< DTV_XRST
S3.3
2G - Function
ED[7:0]
NAND
VIErA-CAST Browser
Flash
EU MHP
S12
1G
UK BBC iPlayer
Latin GINGA MHP
DCDC_EN
Peaks
NAND-IF
DCDC
XNFCE,XNFW
PCOE
CI-IF
DTV_XRST >
P
PCWE
PCWAIT
NFCLE,NFAL
SW_OFF_DET >
PCIORD
E
PCIOWR
PCCD1
S1.2
S1.5
S1.8
S3.3
XNFWE,XNFR
PCRESET
PCCD2
EA[15:1]
ED[15:0]
E
PCCE1
PCREADY
NANDRYBY
Trans Port Decoder
CPUBUS
NAND-IF
IIC
DMD
DMD-IIC0
P-IIC2 (For DMD only)
DMD-IIC1
Peaks
Video
IPR INS
Format
Processor
sLD2
DSP
DDR
2G-1333Hz
S1.5
S1.5
DDR3+
DDR3+
x16
x32
1G
1G
1333Hz
I2S
SW
D D R -IF x16
D D R -IF x16
A-D Chip
Internal BUS
EEP
ASIA,Latin
ELSE: 16k
For STM
For Peaks
STB3.3
S3.3
AMP
PWM
EEP
EEPROM_WP
EEP
16k
P-IIC
SPDIF
STM
SW
EEP_WP >
D-Chip
STM
IIC
STM-IIC
Serial
IIC
Serial
STM-Serial0
P-IIC0
P-Serial0
DMD IIC
STM-Serial1
P-IIC1
P-Serial1
XOR
DMD_IIC
(P-IIC2)
P-UART0
0
P-IIC3
P-UART2
DMD_IIC
STM-D Chip
1
CLK
Communication Register
GEN
STB3.3
STB1.2
24.576MHz
31
S9
STB5/5VS
S12/S5
(SD-Data-VCC)
S9-REG
Analog
3.3/1.8
ASIC
UHS-1
< (SDVOLC)
AN34043A
REG
STB3.3V/1.2V_REG
OVP
STB5V Reset IC (STM)
Safety
SOS
Circuit
S9V_REG
S12V Reset IC (Peaks)
Audio MUTE
OCP/OVP/TV-SOS
< MON_MUTE
HP_MUTE,EXT_MUTE
< SP_HP_MUTE
UHS-I_REG
PWM >
TV_SOS
PWM
Back Light
PWM >
BL_ON >
BL_SOS <
INVERTER
S3.3
or
S9
LED Driver
STB3.3
STB1.2
TEMP
SENSOR
INV-LED
P-IIC
For EEFL
PWMA
XRST POWER_DET
STB_XRST
PANEL_LED_ON >
LCD
Driver
(LPL),LPR,POLL,POLR
PANEL
T - C ON
Ctrl
CPV,GDATA1,GDATA2
LD
m ini-LVDS 156MHz RGB24bit
7pair(6data+1clk 156M) Single
LCD
L V DS -T x
Driver
m ini-L V DS -T x
S15.7
AVDD_ENB >
PANEL_VCC_ON >
T-CON
DCDC
BD81021MUV
P-IIC
BKSEL
GAMMA
DAC
BUF12840
P-IIC
EEP
P-IIC
2k
LCD_EEP_WP >
FHD
D-Book6.x Network
MKV decording
S5
USB
USB*VBUS >
USB
< USB*OC
S5
Power SW
S5
USB Memory
USB*VBUS >
USB
< USB*OC
S5
Power SW
U S B -IF
S5
Only C55D
2
2
COL,CRS
COL,CRS,RXCLK
R R ,RX
R R CLK
RXD0,RXD1,RXD2,RXD3
RX
R R D0,RX
R R D1,RX
R R D2,RX
R R D3
RXDV,RXER,TXCLK
R R DV,RX
RX
R R ER,TX
T T CLK
TXD0,TXD1,TXD2,TXD3
TX
T T D0,TX
T T D1,TX
T D2,TX
T T D3
E E E E H H H E E E R R R
ETHER
E E E T T T
TXEN,MDC,MDIO,MDIO_INTL
T T EN,MDC,MDIO,MDIO_INTL
TX
M II- IF
P P P H H H Y Y Y R R R
PHYRSTL,WAKEUP,WUC
Y Y Y Y Y Y S S S
R R R R R R T T T L L L ,W W W A A A K K K E E E U U U P P P ,W W W U U U C C C
KSZ
KSZ
S5
S
ETHER_XRST <
SD_PWR_ON >
< SD_COIN_DET
SD Reg
S3.3
ExFAT: yes
SDXC
High Speed: no
SD-Data-VCC
UHS-I : no
S D - IF
SDCLK,SDCMD,SDVOLC,
SDDAT[3:0],SDCD,SDWP
<
KEY3
< KEY1
TH-L32C53T
POWER KEY
CONTROL PANEL KEY
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