Hardware Configuration - Silicon Laboratories Si3482 SMART PSE-24 KIT User Manual

Si 34 82 S mart PSE- 24 UG
2. Smart PSE-24 Kit Contents
Table 1 lists the contents of the PSE-24 kit.
The SmartPSE24-RD, which includes the Si3482, six Si3452 PoE controllers, a –50 V to +3.3 V dc-to-dc
1 converter based on a Si3500, isolation for UART communications, and an alternative SPI interface (the
SPI interface is not isolated).
Two Si3402ISO-EVB powered device evaluation boards. The boards are configured to provide a Class 3
2
signature.
One Si3402ISO-C4- EVB. This board is configured to supply a Class 4 signature. The Class 4 boards
3
are marked Class 4 and can also be identified by the diodes on the back of the board.
4 Three switchable loads. The switchable loads draw approximately 6.5, 13, or 19.5 W from the PSE.
One 24-port connector board to bring the Si3452 power to Ethernet jacks. The connector board does not
5
have Ethernet data functionality.
PoE USB adapter. This adapter supports USB to UART, SPI or I
6
the Smart PSE 24 Kit.
7 Three Ethernet cables, one USB cable, and two 24-wire ribbon cables.
3. Using the Smart PSE-24 Kit

3.1. Hardware Configuration

The boards are connected as shown in Figure 1. A nominal 50 V power supply is connected to J815 (note the
polarity). For high-power support according to the IEEE standard, the supply voltage should be between 51 and
57 V. For normal power levels, the power supply can be 45 to 57 V. The total power supply wattage can be as high
as 720 W for full power on all ports. Effective evaluation can be done with a power supply of 40 W or more. Once
configured, the Si3482 manages the available power.
The large diode, D801, will be forward-biased in case of incorrect input polarity.
Note: It is recommended that the power supply be connected to the board and then turned on so as to
reduce large inrush current charging the (3) 33 µF filter capacitors on the board.
Table 2 lists the jumper settings.
Jumper Logic Level
JP7
JP8
JP4, JP5, JP6 1,1,1
JP9
2
Table 1. PSE-24 Kit Contents
Table 2. Jumper Settings
1 Si3482 is not reset when the PoE USB adapter is removed.
JP8 selects UART or SPI interface. The PoE USB adapter board is generally
1
set for UART.
JP4, JP5, and JP6 set the UART baud rate. The PoE USB adapter is config-
ured for 115.2 kHz
JP 9 is for testing the power supply removal function for the third power sup-
ply. As will be discussed later, the power manager GUI can control the first
0 and second power supply lines. The status of the third power supply line is
reported but cannot be controlled. Generally, JP9 is set to 0 (power supply 3
not inserted).
2
C. It is generally used for UART with
Reason
Rev. 0.2