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and
Product Compliance
Specifications
Specifications
Table
Table
Device
Switch
Control
system
Traffic
Control
Line
Table
Table
Item
Dimensions
Weight
A100
Cisco HyperSwitch
1-2
and
Product
Compliance
A100
1-2
the
lists
HyperSwitch
A100
1-2
HyperSwitch
Component
Switch
architecture
Switch
capacity
Buffer
Cell
delay
Control processor
Number
of concurrent
connectable
channels
Path
Setting
NMS
Interface
MAT
interface
control
Policing
Congestion
control
control
Priority
Maximum
line
speed
Maximum
number
of
lines
switch
Line
interface
types
A100
1-3
the
HyperSwitch
lists
AlDO
1-3
HyperSwitch
Specification
Height
Width
Depth
General
equipped
Fully
User Guide
ATM
switch
specifications
ATM
Switch
Specifications
Specification
and
buffer
Input
output
Gbps 155
Mbps
2.4
2048
buffer
Input
128
buffer
Output
20 microseconds
to
Reduced
Internal
32-bit
processor
4096
channels per
VPI
12
of
All
bits
Lower
12-x
of 16
bits
PVC
fixed
path
automatically
connectable
Multicast
Can
be
added/changed
SVC
switched
path
SNMP
EIA/TIA-232
Peak
be
can
set per
rate
Back
pressure
output
Two
loss
levels
Cell
Two
Cell
levels
delay
155
Mbps
line
per
16
lines
per
SONET OC3/SDH
FDDI
4B/5B
TAXI
physical
specifications
Specifications
Physical
mm
165
1/2
approximately
mm
435
17
1/8
approximately
mm
420
16
5/8
approximately
33
lb
15
kg
approximately
17
kg
approximately
type
16
cells
two
lines
per
two
lines
cells
per
milliseconds
Set Computing
Instruction
VP/VC
line
supported
routing
VCI
of
bits
PVC
information
set
per
from
external
terminal
channel
line
switch
line
input
STM1
Mbps
155
100 Mbps
in
in
in
37
1/2
lb
RISC
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