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5
CLK GEN CK505
D
50歐姆:[18/4/10/4/18]
R50
[4]
CPUCLK
R57
[4]
-CPUCLK
R66
[11]
PCHCLK
R70
[11]
-PCHCLK
[10]
DOTCLK
[10]
-DOTCLK
50歐姆:[18/4/10/4/18]
[12]
SRCCLK_SATA
[12]
-SRCCLK_SATA
[4]
SRCCLK_CPU
[4]
-SRCCLK_CPU
[10]
SRCCLK_PCH
[10]
-SRCCLK_PCH
[15]
SRCCLK_3GIO
[15]
-SRCCLK_3GIO
[16]
SRCCLK_3GIO3
[16]
-SRCCLK_3GIO3
C
[29]
SRCCLK_LAN
[29]
-SRCCLK_LAN
R43
[17]
PCLK1
R42
[17]
PCLK0
R63
[18]
LPC33
R46
[12]
PCH33
R75
[18]
LPCCLK48
R33
B
[11]
PCHCLK14
50歐姆:[4/10]
R67
8.2K/4
VCC3
FSBSEL0
R72
1K/4/1
FSA
FSBSEL1
R47
1K/4/1
FSB
R38
8.2K/4
FSBSEL2
R45
1K/4/1
FSC
A
R30
8.2K/4
R64
8.2K/4/X
FSD
3VDUAL
R44
1K/4/1
To enhance PD strength
5
4
CLK
22/4
CPU_CLK
62
CPUT0+
22/4
-CPU_CLK
61
CPUC0-
22/4
PCH_CLK
59
CPUT1+
22/4
-PCH_CLK
58
CPUC1-
12
DOT96T/PCIET11+
13
DOT96C/PCIET11-
15
SATAT
16
SATAC
20
PCIET0+
21
PCIEC0-
24.576Mhz
22
PCIET1+
23
PCIEC1-
25
PCIET2+
26
PCIEC2-
28
PCIET3+
29
PCIEC3-
32
PCIET4+
33
PCIEC4-
34
PCIET5+
35
PCIEC5-
38
PCIET6+
37
PCIEC6-
40
PCIET7+
39
PCIEC7-
RESET_IN#/RESET#
Vtt_PwrGd/PD#/WOL_STOP#
42
PCIET8+
**RLATCH
41
PCIEC8-
45
PCIET9+/CPU_STOP#
44
PCIEC9-/PCI_STOP#
47
PCIET10+
46
PCIEC10-
33/4
33/4
PCICLK0
2
PCICLK0_2X
33/4
S_STOP
3
**SEL_STOP/PCICLK1_2X
FSD
4
PCICLK2_2X
FSC
5
FSLC/PCICLK3_2X
33/4
FSB
6
FSLB/PCICLK4_2X
FSA
9
FSLA/USB_48
33/4
SEL_48
10
*SEL24_48#/24_48
33/4
GSEL
70
REF0/GSEL*
RTM885N-914-GRT/QFN72
R58
GSEL=1,96Mhz from 12/13
GSEL
CKVDD
GSEL=0,100Mhz from12/13
8.2K/4
R77
SEL_48=1, 24Mhz from pin10
SEL_48
SEL_48=0, 48Mhz from pin10
8.2K/4
R61
8.2K/4
S_STOP
R62
8.2K/4/X
CKVDD
Pull High
SEL_STOP: latched input to select pin functionality
1 = Selects pin 44/45 to be PCI_STOP#/CPU_STOP#
0 = Selects pin 44/45 to be PCIEX outputs ;
3.3V PCICLK output
4
3
CKVDD
27
VDD
31
VDD
50
VDD
BC25
BC36
BC28
7
VDDPCI
0.1u/4/Y5V/16V/Z
0.1u/4/Y5V/16V/Z
0.1u/4/Y5V/16V/Z
8
VDD48
49
VDDI/O
60
VDDCPU
66
VDDREF
17
VDDSATA
53
VDDA
54
C24
22p/4/NPO/50V/J
X1
68
X1
14.318M/16p/20ppm/49US/40/D
67
X2
C25
22p/4/NPO/50V/J
R60
10/4
64
SCLK
R59
10/4
65
SDATA
R74
22/4
51
25Mhz
25MCLK_LAN [29]
C22
C33
100p/4/NPO/50V/J/X
CLK_T0
22p/4/NPO/50V/J/X
71
DOC_0**
CLK_T1
72
DOC_1**
R89
10/4
57
-SYS_RST [4,13,27]
R79
1K/4/1
19
PCH_VRMPWRGD [13,26]
CLK_RLATCH
56
BC38
0.1u/4/X7R/16V/K/X
69
GND
63
GND
55
GNDA
BC37
52
GND
22p/4/NPO/50V/J/X
48
GND
43
GND
36
GND
30
GND
24
GND
18
GND
14
GND
11
GND
1
GND
73
GND
FSC
FSB
FSA
0
0
0
0
0
1
0
1
1
0
1
1
CLK_T0
R81
8.2K/4
[18]
CLK_T0
CLK_T1
R80
8.2K/4
[18]
CLK_T1
3
2
BC35
BC17
BC16
BC33
0.1u/4/Y5V/16V/Z
0.1u/4/Y5V/16V/Z
0.1u/4/Y5V/16V/Z
0.1u/4/Y5V/16V/Z
CKVDD
BC15
1u/4/X5R/6.3V/K
SMBCLK [7,8,13,15,16,17,26]
SMBDATA [7,8,13,15,16,17,26]
C21
100p/4/NPO/50V/J/X
EUP
R114
Q8
8.2K/4
2
5VDUAL
3
1
2N7002/SOT23/25pF/5
CPU
0
266MHz
1
133MHz
0
200MHz
1
166MHz
0
333MHz
0
400MHz
VCC3
Gigabyte Technology
Title
CK505 CLK GEN
Size
Document Number
GA-H55M-S2
Custom
Date:
Tuesday, October 05, 2010
2
1
3VDUAL
FB4
D
30/6/4A/S
BC32
BC27
0.1u/4/Y5V/16V/Z
0.1u/4/Y5V/16V/Z
C
-S4_S5 [13,24]
B
A
Rev
1.3
Sheet
22
of
31
1
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