Fpga Irqs - Technologic Systems TS-7100 Series Manual

2/11/2020
Some registers are dual purpose, having separate read and write functionality; while others may only have write
functionality. Registers that do not read and write the same are indicated with "(RD)" and "(WR)" notation. All
other registers read and write the same data set. Any unlisted register addresses are Reserved / Undefined.
Offset Bits
0x00 (RD) 31:0 Revision and Info Register.
0x10 (RD) 15:0 DIO bank 0 Pin State
0x10 (WR) 15:0 DIO bank 0 Data Set
0x12 (WR) 15:0 DIO bank 0 Output Enable Set
0x14 (RD) 15:0 DIO bank 0 Data
0x14 (WR) 15:0 DIO bank 0 Data Clear
0x16 (RD) 15:0 DIO bank 0 Output Enable
0x16 (WR) 15:0 DIO bank 0 Output Enable Clear
0x20 (WR) 31:0 Fractional clock generator
0x24 (RD) 31:0 IRQ Status
0x24 (WR) 31:0 Fractional PWM generator
0x40 (RD) 15:0 DIO bank 1 Pin State
0x40 (WR) 15:0 DIO bank 1 Data Set
0x42 (WR) 15:0 DIO bank 1 Output Enable Set
0x44 (RD) 15:0 DIO bank 1 Data
0x44 (WR) 15:0 DIO bank 1 Data Clear
0x46 (RD) 15:0 DIO bank 1 Output Enable
0x46 (WR) 15:0 DIO bank 1 Output Enable Clear
0x48 31:0 IRQ mask
0x50 (RD) 15:0 DIO bank 2 Pin State
0x50 (WR) 15:0 DIO bank 2 Data Set
0x52 (WR) 15:0 DIO bank 2 Output Enable Set
0x54 (RD) 15:0 DIO bank 2 Data
0x54 (WR) 15:0 DIO bank 2 Data Clear
0x56 (RD) 15:0 DIO bank 2 Output Enable
0x56 (WR) 15:0 DIO bank 2 Output Enable Clear
1. ↑ Note that this is also used for UART clock generation.

10.9.1.4 FPGA IRQs

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