Theory Of Operation And Clocking; Status Signal - HP E2470A Manual

Preprocessor Interface Hardware Reference

Theory of Operation and Clocking

Theory of Operation and Clocking
For timing measurements, raw digital signals from the MC68HC16Y1 are
presented to the logic analyzer through the timing connectors. The
acquisition clock is provided by the logic analyzer.
For state measurements, raw digital signals from the MC68HC16Y1 and
generated signals from the programmable logic are latched and presented to
the logic analyzer through the state connectors. The acquisition clock is
generated by the programmable logic.
As can be seen in the timing diagram on page 3-6, all state information (data,
address, and status) for external cycles (normal and fast termination) is
available within the bus cycle. For internal cycles (also known as show
cycles), however, data is not available until after the completion of the bus
cycle. To capture both internal and external cycles with a single acquisition
clock, all timing must conform to the internal cycle case. The acquisition
clock must be delayed until a clock after any bus cycle completes. In turn, all
state information must be latched.
Signals that could be used in address calculations, including address, chip
selects, and function codes, are latched at the same time. Although bus
control signals could be active and latched with this group, BGACK is the
only signal of importance and, if asserted, prevents the microcontroller from
controlling the bus.
Status signals are latched at the end of the bus cycle and at the same time to
minimize logic. While most status signals are valid much sooner, BERR and
BKPT are valid only at the end.
Data must be latched separately because it becomes valid at two different
times.
The acquisition clock is always generated one clock after the end of a bus
cycle. For address and status, and data on external cycles, this simply means
extra set-up time. For internal cycles, it means that data is aligned with its
associated address and status. Any combination of state signals may be
specified in the trigger menu to find either an internal or external cycle.
3–4