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TC74HC4040P
[12-STAGE
BINARY COUNTER]
(IC23, 24)
UADD-FFs]
FUNCTION TABLE
"
INPUTS
""
OUTPUTS
CLOCK
(io)
CLEAR
QL
4HC245P
[QCTAL
3
STATE
TRANSCEIVER]
FUNCTION TABLE
FUNCTION TABLE
OUTPUTS:
ENABLE
G1
G2*
:
select:
4HC259P
[8
BIT
ADDRESSABLE
LATCHES]
(IC42, 43)
X:
DON'T
CARE
,uPD710540P
[PROGRAMMABLE
^PD8253C-2
INTERVAL
TIMER]
(IC5,
6, 7, 8)
//PD780C
[8
BIT
CPU]
(IC1)
16
BIT
ADDRESS
BUS
WRITE CONTROL
FUNCTION TABLE
BEAD CONTROL
INPUTS
CHIP
SELECT
OUTPUTS
DATA BUS
ENABLE
CLOCK
1
6 BIT
ADDRESS
BUS
ADDRESS
BUS
COUNTER
CLOCK
COUNTER
OUT
COUNTER SATE
COUNTER
CLOCK
BBIT DATA
BUS
COUNTER OUT
COUNTER
CLOCK
COUNTER GATE
COUNTER
GATE
LATCH STL
COUNTER
OUT
REFRESH
MACHINE CYCLE ONE
C74HC373
[3
STATE
OCTAL
D-TYPE LATCH]
C21)
//PD8255
AC-2
(IC4
1
8USR0
©
INTERRUPT REQUEST
LATCH
ENABLE
NON MASKABLE
INTERRUPT
WAIT
CONTROL
HUSAK
fj)
HALT STATE
-.10}
HALT
BUS
AC
KNOW
(FORE
QS)
MR
EO
MEMORY
BEQUEST
WRITE
CONTROL
LEO
DISPLAY DRIVE
LEO DISPLAY
DRIVE
inbut/output
reoufst
IORQ
READ
CONTROL
-PD8237
AC-5
(IC9, 10)
READ CONTROL
WRITE CONTROL
[PROGRAMBLE
DMA
CONTROLHR]
CHIP
SELECT
I/O
READ
ADDRESS
BUS
AOORCSS
BUS
CLEAR
OUTPUT
STATE
H
ALL
OUTPUTS
=
"L"
L
NO CHANGE
L
ADVANCE
TO NEXT STATE
Control
Inputs
Operation
G
DIR
L
L
B
data
to
A
bus
L
H
A
data
to
B
bus
H
X
Isolation
X
c
(V)
07
Vcc
©
©
D6
WR
0
}
©
06
RO
©
©
D4
CS
(
21
©
D3
A
l
©
®
DZ
AO
©
(
7
)
Dl
CLK2
(w
(J)
00
OUT
2
@
(5)
CLK
o
GATE
2
©
OUT
0
CLK
1
©
©
GATE
0
GATEl
©
g)
GND
GUT
|
(J3)
rER
FACE]
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