Gigabyte GA-880GM-D2H Wiring Diagram page 13

5
PLACE THESE PCIE AC COUPLING
CAPS CLOSE TO U600
D
S.B HEATSINK
SB_HS SB_HS
VCC_SB
SB_HS/[12SP2-030005-42R_12SP2-030005-41R_12SP2-030005-43R] SB_HS/[12SP2-030005-42R_12SP2-030005-41R_12SP2-030005-43R]
C
B
RTC_XI
RTC_XO
R166 R166
20M/4 20M/4
X4 X4
32.768K/12.5p/20ppm/TF38/35K/D 32.768K/12.5p/20ppm/TF38/35K/D
1 2
C93 C93 C92 C92
18P/4/NPO/50V/J 18P/4/NPO/50V/J 18P/4/NPO/50V/J 18P/4/NPO/50V/J
X4 X4
A SHW /D0.64*5.08*6.74 SHW /D0.64*5.08*6.74
5
4
U2A U2A
R283 R283 33/4 33/4
N2
<24> -A_RST
A_RST#
C218 C218 0.1U/4/X7R/16V/K 0.1U/4/X7R/16V/K
V23
<9> A_RX0P
PCIE_TX0P
C219 C219 0.1U/4/X7R/16V/K 0.1U/4/X7R/16V/K V22
<9> A_RX0N
PCIE_TX0N
C220 C220 0.1U/4/X7R/16V/K 0.1U/4/X7R/16V/K
V24
<9> A_RX1P PCIE_TX1P
C221 C221 0.1U/4/X7R/16V/K 0.1U/4/X7R/16V/K
V25
<9> A_RX1N
PCIE_TX1N
C222 C222 0.1U/4/X7R/16V/K 0.1U/4/X7R/16V/K
U25
<9> A_RX2P
PCIE_TX2P
C224 C224 0.1U/4/X7R/16V/K 0.1U/4/X7R/16V/K
U24
<9> A_RX2N PCIE_TX2N
C226 C226 0.1U/4/X7R/16V/K 0.1U/4/X7R/16V/K T23
<9> A_RX3P
PCIE_TX3P
C227 C227 0.1U/4/X7R/16V/K 0.1U/4/X7R/16V/K
T22
<9> A_RX3N PCIE_TX3N
U22
<9> A_TX0P
PCIE_RX0P
U21
<9> A_TX0N
PCIE_RX0N
U19
<9> A_TX1P
PCIE_RX1P
V19
<9> A_TX1N
PCIE_RX1N
R20
<9> A_TX2P
PCIE_RX2P
R21
<9> A_TX2N
PCIE_RX2N
R18
<9> A_TX3P
PCIE_RX3P
R17
<9> A_TX3N
PCIE_RX3N
R226 R226 562/4/1 562/4/1
T25
PCIE_CALRP
R241 R241 2.05K/4/1 2.05K/4/1
T24
VCC_SB
PCIE_CALRN
P24
PCIE_PVDD
P25
PCIE_PVSS
BC815 BC815 BC816 BC816
1U/6/Y5V/10V/Z 1U/6/Y5V/10V/Z 10U/8/X5R/6.3V/K 10U/8/X5R/6.3V/K
N25
<12> SBSRC_CLKP
PCIE_RCLKP/NB_LNK_CLKP
N24
<12> SBSRC_CLKN
PCIE_RCLKN/NB_LNK_CLKN
K23
NB_DISP_CLKP
K22
NB_DISP_CLKN
M24
NB_HT_CLKP
M25
NB_HT_CLKN
P17
CPU_HT_CLKP
M18
CPU_HT_CLKN
M23
SLT_GFX_CLKP
M22
SLT_GFX_CLKN
J19
GPP_CLK0P
J18
GPP_CLK0N
L20
GPP_CLK1P
L19
GPP_CLK1N
M19
GPP_CLK2P
M20
GPP_CLK2N
N22
GPP_CLK3P
P22
GPP_CLK3N
L18
25M_48M_66M_OSC
J21
25M_X1
J20
25M_X2
RTC_XI
A3
X1
RTC_XO
B3
X2
R169 R169 8.2K/4/1 8.2K/4/1
VCC18
F23
<10> ALLOW _LDTSTOP ALLOW_LDTSTP
-PROCHOT_CPU
F24
<6> -PROCHOT_CPU
PROCHOT#
F22
<6> CPU_PG_SB
LDT_PG
-LDT_STOP
G25
<6,10> -LDT_STOP LDT_STP#
-CPURST
G24
<6,10> -CPURST
LDT_RST#
Note: LDT_PG, LDT_STP# & LDT_RST# are OD
SB710/FCBGA528/A14/[10HB1-06B710-11R] SB710/FCBGA528/A14/[10HB1-06B710-11R]
and require a PU to the CPU I/O rail. They are
also in the S5 domain to prevent glitching at
power up.
4
3
SB700 SB700
P4
PCICLK0
Part 1 of 5 Part 1 of 5 PCLK1 R251 R251
P3
PCICLK1
PCLK2 R160 R160
P1
PCICLK2
P2 PCLK3 R161 R161
PCICLK3
T4
PCICLK4
T3
PCICLK5/GPIO41
R165 R165
N1
PCIRST#
AD0
U2
AD0
AD1
P7
AD1
AD2
V4
AD2
AD3
T1
AD3
AD4
V3
AD4
AD5
U1
AD5
AD6
V1
AD6
AD7
V2
AD7
AD8
T2
AD8
AD9
W1
AD9
T9 AD10
AD10
AD11
R6
AD11
AD12
R7
AD12
AD13
R5
AD13
AD14
U8
AD14
AD15
U5
AD15
AD16
Y7
AD16
AD17
W8
AD17
AD18
V9
AD18
AD19
Y8
AD19
AD20
AA8
AD20
AD21
Y4
AD21
AD22
Y3
AD22
AD23
Y2
AD23
AA2 AD24
AD24
AD25
AB4
AD25
AD26
AA1
AD26
AD27
AB3
AD27
AD28
AB2
AD28
AD29
AC1
AD29
AD30
AC2
AD30
AD31
AD1
AD31
W2 -C_BE0
-C_BE0 <18>
CBE0#
-C_BE1
U7
CBE1# -C_BE1 <18>
-C_BE2
AA7
CBE2# -C_BE2 <18>
Y1 -C_BE3
-C_BE3 <18>
CBE3#
-FRAME
AA6
FRAME# -FRAME <18>
-DEVSEL
W5
-DEVSEL <18>
DEVSEL#
-IRDY
AA5
-IRDY <18>
IRDY#
-TRDY
Y5
TRDY# -TRDY <18>
PAR
U6
PAR <18>
PAR
-STOP
W6
STOP# -STOP <18>
-PERR
W4
PERR# -PERR <18>
V7 -SERR
-SERR <18>
SERR#
-REQ0
AC3
REQ0# -REQ0 <18>
-REQ1
AD4
-REQ1 <18>
REQ1#
AB7 -REQ2
-REQ2 <18>
REQ2#
-REQ3
AE6
REQ3#/GPIO70 -REQ3 <18>
-REQ4
AB6
-REQ4 <18>
REQ4#/GPIO71
AD2 -GNT0
-GNT0 <18>
GNT0#
-GNT1
AE4
GNT1# -GNT1 <18>
AD5
GNT2#
AC6
GNT3#/GPIO72
-GNT4
AE5
GNT4#/GPIO73 -GNT4 <18>
-PCI_CLKRUN
AD6
CLKRUN#
-PLOCK
V5
LOCK# -PLOCK <18>
AD3 -INTA
-INTA <18>
INTE#/GPIO33
-INTB
AC4
INTF#/GPIO34 -INTB <18>
-INTC
AE2
-INTC <18>
INTG#/GPIO35
-INTD
AE3
-INTD <18>
INTH#/GPIO36
R253 R253 22/4 22/4 LPC_CLK0
G22
LPCCLK0
R254 R254 22/4 22/4 LPC_CLK1
E22
LPCCLK1
LAD0
H24
LAD0 LAD0 <24>
LAD1
H23
LAD1 LAD1 <24>
LAD2
J25
LAD2 LAD2 <24>
J24 LAD3
LAD3 LAD3 <24>
-LFRAME
H25
LFRAME# -LFRAME <24>
-LDRQ0
H22
-LDRQ0 <24>
LDRQ0#
AB8 -LDRQ1 R76 R76
LDRQ1#/GNT5#/GPIO68
R2710 R2710
AD7
BMREQ#/REQ5#/GPIO65
SERIRQ
V15
SERIRQ <24>
SERIRQ
RTC_CLK
C3
RTCCLK
-INTR_ALERT R255 R255 100K/4/1 100K/4/1
C2
INTRUDER_ALERT#
B2
RTCVDD
VBAT
BC21 BC21
0.1U/4/X7R/16V/K 0.1U/4/X7R/16V/K
-PCI_CLKRUN
RTC_CLK
3
2
PCLK2
22/4 22/4 LPC33
LPC33 <24>
22/4 22/4 PCICLK1
PCICLK1 <18>
22/4 22/4 PCICLK2
PCICLK2 <18>
PCLK3
33/4 33/4 -PPCIRST
-PPCIRST <18>
AD[0..31] <18>
EMI 20071107
VCC
PULL
HIGH
C159 C159
1n/4/X7R/50V/K 1n/4/X7R/50V/K
PULL
LOW
LPC_CLK0
LPC_CLK1
PULL
HIGH
PULL
LOW
20mil
3VDUAL
<24> VBAT
8.2K/4/X 8.2K/4/X VBAT_2 RB RB 1K/4/1 1K/4/1
VCC3
8.2K/4/1 8.2K/4/1 BAT54C/SOT23/200mA BAT54C/SOT23/200mA
VCC3
20mil
RTCVDD
BAT BAT
BAT-SK/BK/P/S/D/SN BAT-SK/BK/P/S/D/SN
CR2032 CR2032 BAT BAT
CR2032 CR2032
+ +
VCC3
R172 R172 8.2K/4/X 8.2K/4/X
3VDUAL
R171 R171 8.2K/4/1 8.2K/4/1
Title Title Title
ATI SB710 PCIE/PCI/CPU/LPC ATI SB710 PCIE/PCI/CPU/LPC ATI SB710 PCIE/PCI/CPU/LPC
Size Size Size Document Number Document Number Document Number
Custom Custom Custom
Date: Date: Date: Thursday, August 05, 2010 Thursday, August 05, 2010 Thursday, August 05, 2010
2
1
VCC3
R127 R127 8.2K/4/X 8.2K/4/X
R126 R126 8.2K/4/1 8.2K/4/1
VCC3
R125 R125 8.2K/4/X 8.2K/4/X
R124 R124 8.2K/4/1 8.2K/4/1
D
PCLK2 PCLK3
WATCHDOG TIMER USE
ON NB_PWRGD DEBUG
ENABLED STRAPS
WATCHDOG TIMER IGNORE
ON NB_PWRGD DEBUG
DISABLED STRAPS
DEFAULT DEFAULT
BIOS after boot setting
R121 R121 8.2K/4/1 8.2K/4/1
EC AOD-ACC
R115 R115 8.2K/4/1 8.2K/4/1
C
LPC_CLK0 LPC_CLK1
IMC CLKGEN
ENABLED ENABLED
AOD Extreme
IMC CLKGEN
DISABLED DISABLED
DEFAULT DEFAULT
B
20mil
Q4 Q4 RTCVDD
R163 R163 1K/4/1 1K/4/1
BC783 BC783 BC22 BC22
0.1U/4/X7R/16V/K 0.1U/4/X7R/16V/K 1U/6/Y5V/10V/Z 1U/6/Y5V/10V/Z
CLR_CMOS CLR_CMOS
RTCVDD
PH/1*2/BK/2.54/VA/D PH/1*2/BK/2.54/VA/D
CLR_CMOS
SHORT CLEAR CMOS
OPEN NORMAL
A
NOT ADD ICT FOR RTCVDD PIN
Rev Rev Rev
GA-880GM-D2H GA-880GM-D2H GA-880GM-D2H 1.32 1.32 1.32
Sheet Sheet Sheet 13 13 13 of of of 30 30 30
1