Denon AVR-X2200W Service Manual page 152

W9864G6KH-5 (HDMI : U1023)
W9864G6KH-5 Pin description
5. PIN DESCRIPTION
PIN NUMBER
23 ~ 26, 22,
29 ~35
20, 21
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
45, 47, 48, 50,
51, 53
19
18
17
16
39, 15
38
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
36, 40
PIN NAME FUNCTION
Multiplexed pins for row and column address.
Row address: A0 A11. Column address: A0 A7.
A0 A11 Address
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
Select bank to activate during row address latch time,
BS0, BS1 Bank Select
or bank to read/write during address latch time.
Data
Multiplexed pins for data output and input.
DQ0 DQ15
Input/ Output
Disable or enable the command decoder. When
Chip Select command decoder is disabled, new command is
CS
ignored and previous operation continues.
Command input. When sampled at the rising edge of
Row Address
the clock
Strobe
operation to be executed.
Column
CAS Address Strobe Referred to
Write Enable
WE Referred to
The output buffer is placed at Hi-Z (with latency of 2)
UDQM
Input/output when DQM is sampled high in read cycle. In write
mask cycle, sampling DQM high will block the write
LDQM
operation with zero latency.
System clock used to sample inputs on the rising
CLK Clock Inputs
edge of clock.
CKE controls the clock activation and deactivation.
CKE Clock Enable When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
V Power Power for input buffers and logic circuit inside DRAM.
DD
Ground for input buffers and logic circuit inside
V Ground
SS
DRAM.
Power for I/O Separated power from V
V
DDQ
buffer immunity.
Ground for I/O Separated ground from V
V
SSQ
buffer immunity.
NC No Connection No connection.
- 5 -
W9864G6KH
DESCRIPTION
, CAS and WE define the
, to improve DQ noise
DD
, to improve DQ noise
SS
Publication Release Date: Nov. 12, 2013
152
Revision A02