Page 1 AT-MIO E Series Register-Level Programmer Manual Multifunction I/O Boards for the PC AT AT-MIO E Series RLPM August 1998 Edition Part Number 340747C-01...
Page 2 Singapore 2265886, Spain 91 640 0085, Sweden 08 730 49 70, Switzerland 056 200 51 51, Taiwan 02 377 1200, United Kingdom 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, Texas 78730-5039 USA Tel: 512 794 0100 © Copyright 1995, 1998 National Instruments Corporation. All rights reserved.
Page 3 90 days from date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period.
Page 4: Table Of Contents
Digital I/O Circuitry.......................2-23 Timing I/O Circuitry ......................2-24 RTSI Bus Interface Circuitry ..................2-25 Chapter 3 Register Map and Descriptions Register Map........................3-1 Register Sizes ....................3-4 Register Descriptions .....................3-4 Misc Register Group..................3-4 Serial Command Register ..............3-5 © National Instruments Corporation AT-MIO E Series RLPM...
Page 5 Example 1 ....................... 4-7 Example 2 ....................... 4-10 Example 3 ....................... 4-12 Example Program ................4-13 Example 4 ....................... 4-15 Example 5 ....................... 4-18 Example 6 ....................... 4-20 Example 7 ....................... 4-22 AT-MIO E Series RLPM © National Instruments Corporation...
Page 6 OKI MSM82C55A Data Sheet Appendix B Customer Communication Glossary Index Figures Figure 2-1. AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 Block Diagram2-1 Figure 2-2. AT-MIO-16E-10 and AT-MIO-16DE-10 Block Diagram....2-2 Figure 2-3. AT-MIO-16XE-10 Block Diagram ............2-3 © National Instruments Corporation AT-MIO E Series RLPM...
Page 7 AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-64E-3 EEPROM Map ... 5-2 Table 5-2. AT-MIO-16E-10 and AT-MIO-16DE-10 EEPROM Map ....5-4 Table 5-3. AT-MIO-16XE-50 EEPROM Map ............5-5 Table 5-4. AT-MIO-16XE-10 and AT-AI-16XE-10 EEPROM Map ....5-7 AT-MIO E Series RLPM viii © National Instruments Corporation...
Page 8: About This Manual
The DAQ-STC, a National Instruments system timing controller ASIC, is the timing engine that drives the AT E Series boards. Consequently, the timing and programming sections in this manual repeat certain information from, or draw your attention to, sections in the DAQ-STC Technical Reference Manual.
Page 9: Conventions Used In This Manual
(OKI Semiconductor). • Appendix B, Customer Communication, contains forms for you to complete to help you communicate with National Instruments about our products. • Glossary contains an alphabetical list and description of terms used in this manual, including acronyms, abbreviations, metric prefixes, mnemonics, and symbols.
Page 10: Related Documentation
PC refers to the IBM PC AT and compatible computers. Related Documentation You may find the following National Instruments documents helpful for programming interrupts and DMA: • Programming Interrupts for Data Acquisition on 80x86-Based Computers, Application Note 010 •...
Page 11: General Description
The AT E Series boards are the first completely switchless and jumperless DAQ boards. This feature is made possible by the National Instruments DAQ-PnP bus interface chip to connect the board to the AT I/O bus.
Page 12: Table 1-1. Features Of The At E Series Boards
100 kS/s, eight digital I/O, analog and digital triggering Your AT E Series board is completely software configurable. Refer to your AT E Series User Manual if you have not already installed and configured your board. AT-MIO E Series RLPM © National Instruments Corporation...
Page 13: Theory Of Operation
Output Timing/Control Interface Interface Digital I/O (8) Control Control AO Control DAC0 Data (16) FIFO DAC1 Calibration RTSI Bus DACs *32 on the AT-MIO-64E-3 Figure 2-1. AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 Block Diagram © National Instruments Corporation AT-MIO E Series RLPM...
Page 14: Figure 2-2. At-Mio-16E-10 And At-Mio-16De-10 Block Diagram
Interface Control Control AT-MIO-16DE-10 ONLY PA (8) 8255 PB (8) AO Control Port Data (8) PC (8) DAC0 Data (16) DAC1 Calibration RTSI Bus DACs Figure 2-2. AT-MIO-16E-10 and AT-MIO-16DE-10 Block Diagram AT-MIO E Series RLPM © National Instruments Corporation...
Page 15: Figure 2-3. At-Mio-16Xe-10 Block Diagram
Analog Output Analog 8255 RTSI Bus Digital I/O (8) Digital I/O Output Timing/Control Interface Interface Control Control AO Control DAC0 Data (16) FIFO DAC1 Calibration RTSI Bus DACs Figure 2-3. AT-MIO-16XE-10 Block Diagram © National Instruments Corporation AT-MIO E Series RLPM...
Page 16 Interface Timing I/O DAQ-PnP Interface Play Analog Output RTSI Bus Analog 8255 Digital I/O (8) Digital I/O Output Interface Timing/Control Interface Control Control Data (16) RTSI Bus Figure 2-4. AT-AI-16XE-10 Block Diagram AT-MIO E Series RLPM © National Instruments Corporation...
Page 17 DAQ-STC is the timing engine that provides precise timing signals for the analog input and output operations. The timing I/O circuitry information in this manual is skeletal in nature and is sufficient in most © National Instruments Corporation AT-MIO E Series RLPM...
Page 18: Isa Bus Interface Circuitry
Interface Request DMA TC Sources Data Bus 16 Internal Data Bus Data Buffers DAQ-STC Analog Input FIFO Flags IRQ 8 Analog Output FIFO Flags Figure 2-6. ISA Bus Interface Circuitry Block Diagram AT-MIO E Series RLPM © National Instruments Corporation...
Page 19 The AT E Series boards connect the eight DAQ-STC interrupt lines (0..7) to the IRQ3, 4, 5, 7, 10, 11, 12, and 15 lines, respectively. © National Instruments Corporation AT-MIO E Series RLPM...
Page 20: Analog Input And Timing Circuitry
Figure 2-7. Analog Input and Data Acquisition Circuitry Block Diagram Analog Input Circuitry The general model for analog input on the AT E Series boards includes input multiplexer, multiplexer mode selection switches, a software-programmable gain instrumentation amplifier, calibration AT-MIO E Series RLPM © National Instruments Corporation...
Page 21 ADC. In such applications, which are often lower frequency in nature, adding the dither © National Instruments Corporation AT-MIO E Series RLPM...
Page 22 The EEPROM stores calibration constants that can be AT-MIO E Series RLPM 2-10 © National Instruments Corporation...
Page 23: Data Acquisition Timing Circuitry
Single conversion timing of this type is appropriate for reading channel data on an ad hoc basis. However, if you need a sequence of conversions, the time interval between successive © National Instruments Corporation 2-11 AT-MIO E Series RLPM...
Page 24: Data Acquisition Sequence Timing
LASTCHANNEL bit in the configuration memory or by programming the 16-bit DIV counter to count the number of conversions per SCAN and using the terminal count of the DIV counter as a STOP pulse. AT-MIO E Series RLPM 2-12 © National Instruments Corporation...
Page 25 Example 1 allows you to sample all three channels at a rate of 10 kS/s per channel (100 µs sample interval period). To achieve different rates for different channels, you must do multirate scanning. © National Instruments Corporation 2-13 AT-MIO E Series RLPM...
Page 26 Figures 2-11, 2-12, and 2-13 show timing sequences for different ratios. In these figures, the numbers above the CONVERT pulses indicate the channels sampled in that conversion. AT-MIO E Series RLPM 2-14 © National Instruments Corporation...
Page 27 Here, channel 0 is sampled three times, whereas channels 1 and 2 are sampled once every three scans. Sampling Rates Channel 0: Channel 1: Channel 2 = 4:2:1 START CONVERT STOP Figure 2-13. Multirate Scanning of Three Channels with 4:2:1 Sampling Rate © National Instruments Corporation 2-15 AT-MIO E Series RLPM...
Page 28 Figure 2-15 shows the relative occurrences of convert pulses in Figure 2-14. Channel 1, Example 3 Convert Figure 2-15. Occurrences of Conversion on Channel 1 in Example 3. AT-MIO E Series RLPM 2-16 © National Instruments Corporation...
Page 29: Table 2-1. Analog Input Configuration Memory
— ghost last channel The symbol — indicates that ghost or last channel is absent. Now both channel 0 and channel 1 are sampled with 50% duty cycle. © National Instruments Corporation 2-17 AT-MIO E Series RLPM...
Page 30: Posttrigger And Pretrigger Acquisition
In this mode, the SC gets reloaded each time it counts down to zero. The acquisition can be stopped by disarming the SC. When the SC counts down to zero, acquisition stops. AT-MIO E Series RLPM 2-18 © National Instruments Corporation...
Page 31: Analog Triggering
The AT E Series boards have two analog output channels and a timing core within the DAQ-STC that is dedicated to analog output operation. Figure 2-17 shows a general block diagram for the analog output circuitry. © National Instruments Corporation 2-19 AT-MIO E Series RLPM...
Page 32: Analog Output Circuitry
(Vref) multiplied by the digital code loaded into the DAC. Note that the output will be set to 0 V on power up. The polarity, reference source, and reglitching circuit are all configured in the AO Configuration Register. AT-MIO E Series RLPM 2-20 © National Instruments Corporation...
Page 33 The AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-64E-3, and AT-MIO-16XE-10 include 2 kword-deep FIFOs to buffer the analog output data. This buffering will increase the maximum rate that the analog output © National Instruments Corporation 2-21 AT-MIO E Series RLPM...
Page 34: Analog Output Timing Circuitry
These update pulses can be routed to the DACs. The update counter (UC) is 24 bits wide and counts the number of updates. The value loaded into this counter defines a buffer. The buffer counter (BC) determines how AT-MIO E Series RLPM 2-22 © National Instruments Corporation...
Page 35: Digital I/O Circuitry
DIO0 is used as the serial data out pin. You can use handshaking with the EXTSTROBE* pin to do either parallel or serial data transfer. Refer to the DAQ-STC Technical Reference Manual for more details on the DIO features. © National Instruments Corporation 2-23 AT-MIO E Series RLPM...
Page 36: Timing I/O Circuitry
TC of the other counter. With the last option, the two counters can be concatenated. Similarly, the GATE can also be selected from a variety of different sources. The sources for both of these signals are described in the DAQ-STC Technical Reference Manual. AT-MIO E Series RLPM 2-24 © National Instruments Corporation...
Page 37: Rtsi Bus Interface Circuitry
Theory of Operation RTSI Bus Interface Circuitry The AT E Series is interfaced to the National Instruments RTSI bus. The RTSI bus has seven trigger lines and a system clock line. You can wire all National Instruments AT E Series boards with RTSI bus connectors inside the PC AT and share these signals.
Page 38 Of the four RTSI board signals, only one is used. By programming certain bits in the DAQ-STC, you can drive the CONVERT pulse onto RTSI_BRD0 and then onto any of the TRIGGER lines. AT-MIO E Series RLPM 2-26 © National Instruments Corporation...
Page 39: Register Map And Descriptions
180 to 32 bytes. However, this reduced address space is at the cost of two write operations to write data to or two read operations to read data from a register. © National Instruments Corporation AT-MIO E Series RLPM...
Page 40: Table 3-1. At E Series Register Map
DMA Control Register Group Strobes Write-only 16-bit Channel A Mode Write-only 16-bit Channel B Mode Write-only 16-bit Channel C Mode Write-only 16-bit AI AO Select Write-only 16-bit G0 G1 Select Write-only 16-bit AT-MIO E Series RLPM © National Instruments Corporation...
Page 41: Table 3-2. At E Series Windowed Register Map
Table 3-2. AT E Series Windowed Register Map Word Offset Register Name Decimal Type Size FIFO Strobe Register Group Configuration Memory Clear Write-only 16-bit ADC FIFO Clear Write-only 16-bit DAC FIFO Clear Write-only 16-bit © National Instruments Corporation AT-MIO E Series RLPM...
Page 42: Register Sizes
DACs, EEPROM, and analog trigger source, and one status register that includes EEPROM and DMA information. Bit descriptions of the three registers making up the Misc Register Group are given on the following pages. AT-MIO E Series RLPM © National Instruments Corporation...
Page 43: Serial Command Register
DACs. EEPromCS EEPROM Chip Select—This bit controls the chip select of the onboard EEPROM used to store calibration constants. When EEPromCS is set, the chip select signal to the EEPROM is enabled. © National Instruments Corporation AT-MIO E Series RLPM...
Page 44: Misc Command Register
PGIA is selected as the trigger source. If this bit is cleared, the TRIG1 signal from the I/O connector is selected as the trigger source. 6–0 Reserved Reserved—Always write 0 to these bits. AT-MIO E Series RLPM © National Instruments Corporation...
Page 45: Status Register
DMATCA will be set. This bit is cleared by the DmaTcAClr bit in the Strobes Register. PROMOUT EEPROM Output Data—This bit reflects the serial output data of the serial EEPROM. © National Instruments Corporation AT-MIO E Series RLPM...
Page 46: Analog Input Register Group
The binary format used is determined by the mode in which the ADC is configured. Following is the bit pattern returned for either format: Address: Base address + 1C (hex) Type: Read-only Word Size: 16-bit Bit Map: AT-MIO E Series RLPM © National Instruments Corporation...
Page 47 0xFFFF) when the ADC is in unipolar mode and 32,768 to 32,767 decimal (0x8000 to 0x7FFF) when the ADC is in bipolar mode. The mode is controlled by the Unip/Bip bit in the Configuration Memory Low Register. © National Instruments Corporation AT-MIO E Series RLPM...
Page 48: Configuration Memory Low Register
RTSI_BRD0 input of the DAQ-STC during the CONVERT signal. This trigger is used at the application level and can perform such actions as time stamping and starting waveform generation. AT-MIO E Series RLPM 3-10 © National Instruments Corporation...
Page 49: Table 3-3. Pgia Gain Selection
The following gains can be selected on the AT E Series: Table 3-3. PGIA Gain Selection Gain<2..0> Actual Gain Not supported on the AT-MIO-16XE-50. Not supported on the AT-MIO-16XE-10 and AT-AI-16XE-10. © National Instruments Corporation 3-11 AT-MIO E Series RLPM...
Page 50: Configuration Memory High Register
ChanType<2..0> Channel Type 2 through 0—These bits indicate which type of resource is active for the current entry in the scan list. The following table lists the valid channel types. Type<2..0> Resource Calibration Differential NRSE Ghost AT-MIO E Series RLPM 3-12 © National Instruments Corporation...
Page 51: Table 3-4. Calibration Channel Assignments
ADC Offset 0001 REF5V AI GND ADC Gain 0110 DAC0OUT REF5V DAC 0 Gain 0111 DAC1OUT REF5V DAC 1 Gain 1xxx Reserved Reserved — * AIGND on the AT-MIO-16XE-50, AT-MIO-16XE-10 and AT-AI-16XE-10. © National Instruments Corporation 3-13 AT-MIO E Series RLPM...
Page 52: Table 3-5. Differential Channel Assignments
AISense 0010 ACh2 AISense 0011 ACh3 AISense 0100 ACh4 AISense 0101 ACh5 AISense 0110 ACh6 AISense 0111 ACh7 AISense 1000 ACh8 AISense 1001 ACh9 AISense 1010 ACh10 AISense 1011 ACh11 AISense AT-MIO E Series RLPM 3-14 © National Instruments Corporation...
Page 53: Table 3-7. Referenced Single-Ended Channel Assignments
AIGround 0110 ACh6 AIGround 0111 ACh7 AIGround 1000 ACh8 AIGround 1001 ACh9 AIGround 1010 ACh10 AIGround 1011 ACh11 AIGround 1100 ACh12 AIGround 1001 ACh13 AIGround 1110 ACh14 AIGround 1111 ACh15 AIGround © National Instruments Corporation 3-15 AT-MIO E Series RLPM...
Page 54: Analog Output Register Group
DAC Select—This bit indicates which DAC is the destination for the configuration bits in this register. DAC0 will be selected when this bit is cleared, and DAC1 will be selected when set. AT-MIO E Series RLPM 3-16 © National Instruments Corporation...
Page 55 DAC is interpreted in straight binary format. This bit is reserved on the AT-MIO-16XE-50 and should be set to 1. The AT-MIO-16XE-50 DACs are always configured in bipolar mode. © National Instruments Corporation 3-17 AT-MIO E Series RLPM...
Page 56: Dac Fifo Data Register
DAC data FIFO. This data is interpreted in straight binary form when DAC1 is configured for unipolar operation. When DAC1 is configured for bipolar operation, the data is interpreted in two’s complement form (AT-MIO-16XE-10 and AT-AI-16XE-10 only). AT-MIO E Series RLPM 3-18 © National Instruments Corporation...
Page 57: Dac0 Direct Data Register
DAC data FIFO. This data is interpreted in straight binary form when DAC0 is configured for unipolar operation. When DAC0 is configured for bipolar operation, the data is interpreted in two’s complement form (AT-MIO-16XE-10 and AT-AI-16XE-10 only). © National Instruments Corporation 3-19 AT-MIO E Series RLPM...
Page 58: Dac1 Direct Data Register
DAC data FIFO. This data is interpreted in straight binary form when DAC1 is configured for unipolar operation. When DAC1 is configured for bipolar operation, the data is interpreted in two’s complement form (AT-MIO-16XE-10 and AT-AI-16XE-10 only). AT-MIO E Series RLPM 3-20 © National Instruments Corporation...
Page 59: Dma Control Register Group
DMA TC interrupt if caused by logical channel B. DmaTcAClr DMA Terminal Count A Clear—Clears the DMA TC status bit for logical channel A. This action also removes the DMA TC interrupt if caused by logical channel A. © National Instruments Corporation 3-21 AT-MIO E Series RLPM...
Page 60: Channel A Mode Register
Channel<2..0> Physical Channel Select 2 through 0—These three bits select which physical channel is associated with logical channel A. The AT E Series can use only 16-bit DMA channels, so these bits must be set appropriately. AT-MIO E Series RLPM 3-22 © National Instruments Corporation...
Page 61: Channel B Mode Register
Channel<2..0> Physical Channel Select 2 through 0—These three bits select which physical channel is associated with logical channel B. The AT E Series can use only 16-bit DMA channels, so these bits must be set appropriately. © National Instruments Corporation 3-23 AT-MIO E Series RLPM...
Page 62: Channel C Mode Register
Channel<2..0> Physical Channel Select 2 through 0—These three bits select which physical channel is associated with logical channel C. The AT E Series can use only 16-bit DMA channels, so these bits must be set appropriately. AT-MIO E Series RLPM 3-24 © National Instruments Corporation...
Page 63: Ai Ao Select Register
AT E Series boards support only single channel DMA; therefore, only one of the three bits must be set for proper operation. These bits must be set prior to enabling the logical channels. © National Instruments Corporation 3-25 AT-MIO E Series RLPM...
Page 64: G0 G1 Select Register
8255 data sheet, included in Appendix A. Note that the port C interrupt lines, PC0 and PC3, are ORed together on the board and connected to the DAQ-STC group A pass-through interrupt. AT-MIO E Series RLPM 3-26 © National Instruments Corporation...
Page 65: Daq-Stc Register Group
DAC FIFO Clear Register Accessing the DAC FIFO Clear Register clears all information in the DAC data FIFO. Window Address: 54 (hex) Type: Write-only Word Size: 16-bit Bit Map: Not applicable; no bits used © National Instruments Corporation 3-27 AT-MIO E Series RLPM...
Page 66: Programming
To implement the function, you will need to perform a write to or a read from the specified registers. The complete examples are provided on the AT E Series Register-Level Programmer Manual Companion Disk. © National Instruments Corporation AT-MIO E Series RLPM...
Page 67: Plug And Play Initialization
This long sequence of 34 writes was chosen to decrease the chances that a poorly written program that writes randomly into I/O space does not accidentally access the Plug and Play configuration registers. The function performs this series of writes. Write_PNP_Initiation_Key AT-MIO E Series RLPM © National Instruments Corporation...
Page 68 The registers for the E Series board can now be accessed by their offset from the base I/O address that was assigned above. It is important to note that the code given above must be repeated every time that the computer is © National Instruments Corporation AT-MIO E Series RLPM...
Page 69: Windowing Registers
Since the DAQ-STC contains a large number of registers (180), eight address lines would be required to decode the addresses in direct address mode. In addition to the DAQ-STC registers, the AT-MIO E Series boards have other discrete registers. This enormous I/O address space makes it impossible to use other peripheral cards with their own registers.
Page 70: Digital I/O
Chapter 7 of the DAQ-STC Technical Reference Manual.) Set up the Plug and Play resources. Use the function provided on the Companion Disk. Setup_PNP_Board Configure all the digital lines as outputs. DIO_Control_Register = 0xFF; © National Instruments Corporation AT-MIO E Series RLPM...
Page 71: Example 2
Programming the AT E Series boards for analog input can be divided into writing to and reading from two main register groups: discrete board registers, and DAQ-STC registers. The following functions configure the board by calling the functions: Board_Read Board_Write Setup_PNP_Board; Configure_Board; AT-MIO E Series RLPM © National Instruments Corporation...
Page 72: Example 1
The first two steps set up the E Series board, and the subsequent steps configure the DAQ-STC. Set up the Plug and Play resources. Use the function provided on the Companion Disk. Setup_PNP_Board The second step configures the analog channel for the given settings. © National Instruments Corporation AT-MIO E Series RLPM...
Page 73 AI_Reset_All and start the configuration process. Joint_Reset_Register AI reset = 1; AI configuration start = 1; Interrupt_A_Ack_Register = 0x3F80; AI_Mode_1_Register Reserved one = 1; AI start stop = 1; AT-MIO E Series RLPM © National Instruments Corporation...
Page 74 AI configuration end = 1; Call to set the triggering options. AI_Trigger_Signals Joint_Reset_Register AI configuration start = 1; AI_Mode_1_Register Trigger once = 1; AI_Trigger_Select_Register Start edge = 1; Start sync = 1; © National Instruments Corporation AT-MIO E Series RLPM...
Page 75 Example 2 illustrates the manner in which to program the STC for scanning. Acquire 5 scans at a scan interval of 1ms. The scan list contains channels 5, 4, 1, and 0, repectively. The channels are configured as RSE at a gain AT-MIO E Series RLPM 4-10 © National Instruments Corporation...
Page 76 AI configuration start = 0; AI configuration end = 1; Perform Analog Input Example 1 Step 11. selects the convert signal for the acquisition. Convert_Signal Joint_Reset_Register AI configuration start = 1; © National Instruments Corporation 4-11 AT-MIO E Series RLPM...
Page 77 Acquire 5 scans at a scan interval of 1ms. The scan list contains channels 5, 4, 1, and 0 respectively. The channels are configured as RSE at a gain of 1. Within each scan, the sample interval should be 100f during the AT-MIO E Series RLPM 4-12 © National Instruments Corporation...
Page 78: Example Program
AI_Command_1_Register AI SC Load = 1; Joint_Reset_Register AI configuration start = 0; AI configuration end = 1; The function selects the scan start event. AI_Scan_Start Joint_Reset_Register AI configuration start = 1; © National Instruments Corporation 4-13 AT-MIO E Series RLPM...
Page 79 The function enables interrupts for the AI_Interrupt_Enable acquisition. Interrupt_A_Enable_Register AI FIFO interrupt enable = 1; AI error interrupt enable = 1; Interrupt_Control_Register MSC IRQ pin = 4; MSC IRQ enable = 1; AT-MIO E Series RLPM 4-14 © National Instruments Corporation...
Page 80: Example 4
Only channel 0 has Last channel set to 1. Perform Analog Input Example 1 Steps 3-9. Call the function to load the number of scans. Number_of_Scans Joint_Reset_Register AI configuration start = 1; © National Instruments Corporation 4-15 AT-MIO E Series RLPM...
Page 81 AI SI2 special ticks - 1 = 1999; AI_SI2_Load_B_Register AI SI2 ordinary ticks -1 = 1999; AI_Mode_2_Register AI SI2 reload mode = 1; AI_Command_1_Register AI SI2 load = 1; AI_Mode_2_Register AI SI2 initial load source = 1; AT-MIO E Series RLPM 4-16 © National Instruments Corporation...
Page 82 AI SC arm = 1; AI SI arm = 1; AI SI2 arm = 1; AI DIV arm = 1; 13. The function starts the acquisition AI_Start_The_Acquisition process. AI_Command_2_Register AI START1 Pulse = 1; © National Instruments Corporation 4-17 AT-MIO E Series RLPM...
Page 83: Example 5
AI configuration start = 1; AI_SC_Load_A_Registers (24 bits) Number of posttrigger scans - 1 = 4; AI_Command_1_Register AI SC Load = 1; Joint_Reset_Register AI configuration start = 0; AI configuration end = 1; AT-MIO E Series RLPM 4-18 © National Instruments Corporation...
Page 84 Perform Analog Input Example 1 Step 4. 10. Call to arm the analog input counter. AI_Arming AI_Command_1_Register AI SC arm = 1; AI SI arm = 0; AI SI2 arm = 1; AI DIV arm = 1; © National Instruments Corporation 4-19 AT-MIO E Series RLPM...
Page 85: Example 6
Call the function to load the number of scans. Number_of_Scans Joint_Reset_Register AI configuration start = 1; AI_Mode_2_Register AI pretrigger = 1; AI_SC_Load_B_Registers (24 bits) Number of pretrigger scans - 1 = 9; AT-MIO E Series RLPM 4-20 © National Instruments Corporation...
Page 86 AI SI2 special ticks - 1 = 1999; AI_SI2_Load_B_Register AI SI2 ordinary ticks -1 = 1999; AI_Mode_2_Register AI SI2 reload mode = 1; AI_Command_1_Register AI SI2 load = 1; AI_Mode_2_Register AI SI2 initial load source = 1; © National Instruments Corporation 4-21 AT-MIO E Series RLPM...
Page 87 Call the function to load the number of scans. Number_of_Scans Joint_Reset_Register AI configuration start = 1; AI_SC_Load_A_Registers (24 bits) Number of posttrigger scans - 1 = 4; AI_Command_1_Register AI SC Load = 1; AT-MIO E Series RLPM 4-22 © National Instruments Corporation...
Page 88 AI SC arm = 1; AI SI arm = 0; AI SI2 arm = 0; AI DIV arm = 1; 10. The function starts the acquisition AI_Start_The_Acquisition process. AI_Command_2_Register AI START1 pulse = 1; © National Instruments Corporation 4-23 AT-MIO E Series RLPM...
Page 89 Call the function to load the number of scans. Number_of_Scans Joint_Reset_Register AI configuration start = 1; AI_SC_Load_A_Registers (24 bits) Number of posttrigger scans - 1 = 99; AI_Command_1_Register AI SC Load = 1; AT-MIO E Series RLPM 4-24 © National Instruments Corporation...
Page 90 AI SI2 load = 1; AI_Mode_2_Register AI SI2 initial load source = 1; Joint_Reset_Register AI configuration start = 0; AI configuration end = 1; 10. Perform Analog Input Example 1 Step 4. © National Instruments Corporation 4-25 AT-MIO E Series RLPM...
Page 91 Memory_Output configuration FIFO. This function also configures the DIO circuitry for the AMUX-64T. AI_Command_1_Register AI convert one pulse = 1; AI_Mode_2_Register AI external mux present = 1; AT-MIO E Series RLPM 4-26 © National Instruments Corporation...
Page 92 AI configuration end = 1; The function selects the scan start event. AI_Scan_Start Joint_Reset_Register AI configuration start = 1; AI_START_STOP_Select_Register = 0x0060; AI_SI_Load_A_Registers (24 bits) AI SI special ticks - 1 = 1 © National Instruments Corporation 4-27 AT-MIO E Series RLPM...
Page 93 AI SC arm = 1; AI SI arm = 1; AI SI2 arm = 1; AI DIV arm = 1; 13. Now start the acquisition with AI_Start_The_Acquisition AI_Command_2_Register AI START1 pulse = 1; AT-MIO E Series RLPM 4-28 © National Instruments Corporation...
Page 94: Analog Output
The AT E Series Register Level Programmer Manual Companion Disk contains the complete programs. The following pseudo-code examples and the programs on the Companion Disk follow the flowchart structure presented in the DAQ-STC Technical Reference Manual. © National Instruments Corporation 4-29 AT-MIO E Series RLPM...
Page 95: Example 1
DAQ-STC. AO_Board_Personalize Joint_Reset_Register AO_Configuration_Start = 1; AO_Personal_Register = 0x1430; Clock_and_FOUT_Register = 0x1B20; AO_Output_Control_Register = 0x0000; AO_START_Select_Register = 0x 0000; Joint_Reset_Register AO configuration start = 0; AO configuration end = 1; AT-MIO E Series RLPM 4-30 © National Instruments Corporation...
Page 96 = (voltage/10) * 2048 Configure the board by setting the following board level bits. AO_Configuration_Register: DACSel<3:0> = 1; BipDac = 1; ExtRef = 0; ReGlitch = 0; GroundRef = 0; Reset the data FIFO. © National Instruments Corporation 4-31 AT-MIO E Series RLPM...
Page 97 Call to program the trigger signal. Configure the AO_Triggering DAQ-STC to trigger once and use a software START1 trigger. Joint_Reset_Register AO configuration start = 1; AO_Mode_1_Register AO trigger once = 1; AT-MIO E Series RLPM 4-32 © National Instruments Corporation...
Page 98 AO configuration start = 0; AO configuration end = 1; 11. Call to program the update interval. Use the internal AO_Updating UPDATE mode. Set the UI source to AO_IN_TIMEBASE1. Load the © National Instruments Corporation 4-33 AT-MIO E Series RLPM...
Page 99 Joint_Reset_Register AO configuration start = 0; AO configuration end = 1; 13. Call to configure LDAC1 to AO_LDAC_Source_And_Update_Mode output UPDATE in the timed update mode. Joint_Reset_Register AO configuration start = 1; AT-MIO E Series RLPM 4-34 © National Instruments Corporation...
Page 100 DAC with the AO_Arming first analog output value. AO_Mode_3_Register AO not an UPDATE = 1; AO_Mode_3_Register AO not an UPDATE = 0; If (!VirtualFIFO) Wait until DACs have been preloaded. AO_Command_1_Register = 0x0554; © National Instruments Corporation 4-35 AT-MIO E Series RLPM...
Page 101 AO configuration start = 1; AO_Mode_1_Register AO continuous = 0; AO_Mode_2_Register AO BC initial load source = 0; AO_BC_Load_A_Registers (24 bits) Number of buffers -1 = 49; AO_Command_1_Register AO BC load =1; AT-MIO E Series RLPM 4-36 © National Instruments Corporation...
Page 102 AO UI special ticks -1 = 1; AO_Command_1_Register AO UI load = 1; AO_UI_Load_A_Registers (24 bits) AO UI ordinary ticks - 1 = 1999; Joint_Reset_Register AO configuration start = 0; AO configuration end = 1; © National Instruments Corporation 4-37 AT-MIO E Series RLPM...
Page 103: Example 2
Call to program the trigger signal. Configure the AO_Triggering DAQ-STC to trigger once. Set the START1 select to PFI6. Joint_Reset_Register AO configuration start = 1; AO_Mode_1_Register AO trigger once = 1; AT-MIO E Series RLPM 4-38 © National Instruments Corporation...
Page 104 Points per buffer = 100; AO_Command_1_Register AO UC load = 1; AO_UC_Load_A_Registers (24 bits) Points per buffer - 1 = 99; Joint_Reset_Register AO configuration start = 0; AO configuration end = 1; © National Instruments Corporation 4-39 AT-MIO E Series RLPM...
Page 105: Example Program
Perform Analog Output Example 2 Steps 1-14. Call to disable the FIFO retransmit and set the FIFO mode. AO_FIFO Joint_Reset_Register AO configuration start = 1; AO_Mode_2_Register AO FIFO Mode = 1; AO FIFO retransmit enable = 0; AT-MIO E Series RLPM 4-40 © National Instruments Corporation...
Page 106 AO_Command_2_Register AO START1 pulse = 1; Poll the AO FIFO half full flag in the AO_Status_1_Register until half full and call the ISR. If (AO FIFO half full) then call service_interrupt © National Instruments Corporation 4-41 AT-MIO E Series RLPM...
Page 107: General-Purpose Counter/Timer
Call MSC_IO_Pin_Configure() to set all the PFI pins for input. IO_Bidirection_Pin_Register BD_i_Pin_Dir <= 0; Call G0_Reset_All() to reset all the necessary registers in DAQ-STC. Joint Reset Register G0_Reset=1; G0_Mode_Register=0x0000; G0_Command_Register=0x0000; G0_Input_Select_Register=0x0000; AT-MIO E Series RLPM 4-42 © National Instruments Corporation...
Page 108 G0_Gate_On_Both_Edges = 0; G0_Trigger_Mode_For_Edge_Gate = 2; G0_Stop_Mode = 0; G0_Counting_Once = 0; G0_Command_Register G0_Up_Down = 1; (up counting) G0_Bank_Switch_Enable = 0; G0_Bank_Switch_Mode = 0; Interrupt_A_Enable_Register G0_TC_Interrupt_Enable = 0; G0_Gate_Interrupt_Enable = 0; © National Instruments Corporation 4-43 AT-MIO E Series RLPM...
Page 109 Perform General Purpose Counter and Timer Example 1 Steps 1-3. Call Buffered_Pulse_Width_Measurement() to setup DAC-STC for buffered pulse width measurement. Go_Mode_Register G0_Load_Source=0; G0_Load_A_Registers (24 bits) G0_Load_A=0x0000; //initial counter value G0_Command_Register G0_Load=1; AT-MIO E Series RLPM 4-44 © National Instruments Corporation...
Page 110 (buffer is not done and buffer is not full) then current buffer value =save_1; increase buffer pointer; if (all the points have been written into the buffer) then G0_Command_Register G0_Disarm=1; © National Instruments Corporation 4-45 AT-MIO E Series RLPM...
Page 111: Example 2
Perform General Purpose Counter and Timer Example 1 Steps 1-3. If you want to use G_In_timebase2 Call MSC_Clock _Configure() to setup the G_In_timebase2 Clock_and_FOUT_Register Slow_Internal_Timebase <= msc_slow_int_tb_enable (1) Slow_Internal_Time_Divide_By_2 <=msc_slow_int_tb_divide_ by_2 (1) Clock_To_Board <= p->msc_clock_to_board_enable (1) Clock_To_Board_Divide_By_2 <= msc_clock_to_board_divide _by_2(1) AT-MIO E Series RLPM 4-46 © National Instruments Corporation...
Page 112 G0_Up_Down = 0; (down counting) G0_Bank_Switch_Enable = 0; or G0_Bank_Switch_Enable = 1 if you want to change rate. And need call G0_Seamless_Pulse_Train_Change() G0_Bank_Switch_Mode = 0; Interrupt_A_Enable_Register G0_TC_Interrupt_Enable = 0; G0_Gate_Interrupt_Enable = 0; © National Instruments Corporation 4-47 AT-MIO E Series RLPM...
Page 113: Rtsi Trigger Lines Programming Considerations
There are seven 12-1 muxes that drive the seven RTSI lines. Any of the RTSI lines can be driven with any of eight internally generated timing signals or with any of the four RTSI board signals. Similarly, there are four AT-MIO E Series RLPM 4-48 © National Instruments Corporation...
Page 114: Analog Triggering
When the PFI0/TRIG1 input is being used for an analog signal, it must be disconnected from the DAQ-STC PFI input. You can do this by clearing the Analog_Trigger_Drive bit in the DAQ-STC. © National Instruments Corporation 4-49 AT-MIO E Series RLPM...
Page 115: Analog Trigger Structure
To set the low and high analog thresholds, CALDACs 11 and 12 must be written with appropriate values. The protocol for writing to these DACs is the same as that for all the CALDACs mentioned in Chapter 5, Calibration, in this manual. AT-MIO E Series RLPM 4-50 © National Instruments Corporation...
Page 116 Call the function Number_of Scans() to load the number of scans to load the number of scans. Joint_Reset_Register AI configuration start = 1; AI_SC_Load_A_Register(24 bits) Number of postrigger scan -1 = 99 © National Instruments Corporation 4-51 AT-MIO E Series RLPM...
Page 117: Interrupt Programming
1 interrupts, and one pass-through interrupt. The Group B pass-through interrupt is connected to the DMA TC interrupt, which will be asserted whenever the individual DMA TC interrupts are enabled and the TC occurs. AT-MIO E Series RLPM 4-52 © National Instruments Corporation...
Page 118: Dma Programming
0x0B) to assign particular logical channels to either AI, AO, or GPCTs. Figure 4-2 shows the three-stage DMA structure. Analog Logical Input Channel A Analog Output Physical Logical Channel Channel B Assignment GPCT1 Logical GPCT2 Channel C Figure 4-2. DMA Structure © National Instruments Corporation 4-53 AT-MIO E Series RLPM...
Page 119: Single Channel Versus Dual Channel Dma
TC which generates an interrupt, if the board is programmed for DMA. Usually, the interrupt latency is long enough so that, by the time you reprogram your DMA controller, some data is lost. This affects sustained throughput. AT-MIO E Series RLPM 4-54 © National Instruments Corporation...
Page 120 Also notice that whenever a TC interrupt is generated, the corresponding DMATCCLR bit in the Strobes Register (address 0x01) must be strobed. This clears the TC status bits for that logical DMA channel. © National Instruments Corporation 4-55 AT-MIO E Series RLPM...
Page 121: Calibration
Do not attempt to write to the EEPROM. If the factory area of the EEPROM (the upper 128 bytes) or the Plug and Play area (the lower 256 bytes) is lost, the board can be rendered inoperable. In this situation, you will have to send © National Instruments Corporation AT-MIO E Series RLPM...
Page 122: Table 5-1. At-Mio-16E-1, At-Mio-16E-2, At-Mio-64E-3 Eeprom Map
Chapter 5 Calibration the board back to National Instruments to be reprogrammed. National Instruments is liable for such mistakes, and you will have to bear the full expense of the RMA. EEPROMCS SerClk SerData A3 A2 D7 D6 D5 D4 D3 D2 PROMOUT Figure 5-1.
Page 123 Factory CALDAC 10 bipolar value (AO) (8-bit) Factory CALDAC 9 bipolar value (AO) (8-bit) Factory CALDAC 5 unipolar value (AO) (8-bit) Factory CALDAC 7 unipolar value (AO) (8-bit) Factory CALDAC 6 unipolar value (AO) (8-bit) © National Instruments Corporation AT-MIO E Series RLPM...
Page 124: Table 5-2. At-Mio-16E-10 And At-Mio-16De-10 Eeprom Map
Factory CALDAC 1 value (AI) (8-bit) Factory CALDAC 3 value (AI) (8-bit) Factory CALDAC 2 value (AI) (8-bit) Factory CALDAC 5 bipolar value (AO) (8-bit) Factory CALDAC 7 bipolar value (AO) (8-bit) AT-MIO E Series RLPM © National Instruments Corporation...
Page 125: Table 5-3. At-Mio-16Xe-50 Eeprom Map
Start of the 5 user calibration sections *Board Codes: 36—AT-MIO-16E-10, 37—AT-MIO-16DE-10 Table 5-3. AT-MIO-16XE-50 EEPROM Map Address Data Description NI-DAQ Board Code Revision Revision Sub-revision Sub-revision Year Year of last factory calibration Month Month of last factory calibration © National Instruments Corporation AT-MIO E Series RLPM...
Page 126 (AI)–unipolar (8-bit) Factory CALDAC 6 value (AO) (8-bit) Factory CALDAC 4 value (AO) (8-bit) Factory CALDAC 7 value (AO) (8-bit) Factory CALDAC 5 value (AO) (8-bit) Start of the 5 user calibration sections AT-MIO E Series RLPM © National Instruments Corporation...
Page 127: Table 5-4. At-Mio-16Xe-10 And At-Ai-16Xe-10 Eeprom Map
(AI)–unipolar Factory CALDAC 2 value (AI)–unipolar Factory CALDAC 3 value (AI)–unipolar Factory CALDAC 0 value (AI)–unipolar Factory CALDAC 1 value (AI)–unipolar Start of the 4 user calibration sections *Board Codes: 50—AT-MIO-16XE-10, 51—AT-AI-16XE-10 © National Instruments Corporation AT-MIO E Series RLPM...
Page 128: Calibration Dacs
SerDacLd pin. The timing diagram for the write cycle for each DAC is shown in Figure 5-2 (a, b, c, d). Note Review the timing diagram and specifications very carefully before attempting to write code. AT-MIO E Series RLPM © National Instruments Corporation...
Page 129: Ni-Daq Calibration Function
, which is run only when the board needs new Calibrate_E_Series calibration constants. Writing such an application allows the normal application to simply copy the calibration constants from the EEPROM and write them to the calibration DACs upon board initialization. © National Instruments Corporation AT-MIO E Series RLPM...
Page 130: Oki Msm82C55A Data Sheet
CMOS programmable peripheral interface (OKI Semiconductor). This interface is used on the AT-MIO-16DE-10. Copyright © OKI Semiconductor. 1993. Reprinted with permission of copyright owner. All rights reserved. OKI Semiconductor. Microprocessor Data Book 1993. © National Instruments Corporation AT-MIO E Series RLPM...
Page 147: Customer Communication
Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24-hour support with a collection of files and documents to answer most common customer questions. From these sites, you can also download the latest instrument drivers, updates, and example programs. For recorded instructions on how to use the bulletin board and FTP services and for BBS automated information, call 512 795 6990.
Page 148 Telephone and Fax Support National Instruments has branch offices all over the world. Use the list below to find the technical support number for your country. If there is no National Instruments office in your country, contact the source from which you purchased your software to obtain support.
Page 149 National Instruments for technical support helps our applications engineers answer your questions more efficiently. If you are using any National Instruments hardware or software products related to this problem, include the configuration forms from their user manuals. Include additional pages if necessary.
Page 150 Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
Page 151 Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: AT-MIO E Series Register-Level Programmer Manual Edition Date: August 1998 Part Number: 340747C-01 Please comment on the completeness, clarity, and organization of the manual.
Page 152: Glossary
Symbols inverted bit (negative logic) if after a bit name Ω ohms amperes alternating current analog-to-digital A/D converter AIGND analog input ground signal AOGND analog output ground signal ASIC application-specific integrated circuit © National Instruments Corporation AT-MIO E Series RLPM...
Page 153 D/A converter DAC0OUT analog channel 0 output signal DAC1OUT analog channel 1 output signal DACSe DAC select bit data acquisition direct current DitherEn dither enable bit divide by signal AT-MIO E Series RLPM © National Instruments Corporation...
Page 154 FIFO first-in-first-out Gain channel gain select bit GenTrig general trigger bit ghost a conversion that is performed but the data is thrown away GPCT1 general-putpose counter timer 1 bit © National Instruments Corporation AT-MIO E Series RLPM...
Page 155 Input analog input bit Int/Ext Trig internal/external analog trigger input/output interrupt request signal Industry Standard Architecture LASTCHANNEL last channel bit least significant bit meters megabytes of memory most significant bit multiplexer AT-MIO E Series RLPM © National Instruments Corporation...
Page 156 PFI 1/Trigger 2 signal PGIA Programmable Gain Instrumentation Amplifier parts per million PRETRIG pretrigger signal PROMOUT EEPROM output data bit ReGlitch reglitch DAC bit resistance-temperature detector RTSI Real-Time System Integration bus RTSI_BRD0 RTSI board © National Instruments Corporation AT-MIO E Series RLPM...
Page 157 START start signal STOP stop signal terminal count TCIntEnable DMATC interrupt enable bit Transfer transfer type bit transistor-transistor logic update counter update interval update interval 2 Unip/Bip channel unipolar/bipolar bit AT-MIO E Series RLPM © National Instruments Corporation...
Page 158 Glossary volts V ref input voltage reference don’t care bits © National Instruments Corporation AT-MIO E Series RLPM...
Page 159: Index
20 scans, 4-20 to 4-22 analog input example, 4-9 acquiring one sample from channel 0, AI_Interrupt_Enable function 4-7 to 4-10 DMA scanning example, 4-17 interrupt scanning example, 4-14 AI_Reset_All function, 4-8 © National Instruments Corporation AT-MIO E Series RLPM...
Page 160 4-36 to 4-38 Assign_PNP_Data_Port_Address Analog Output Register Group function, 4-3 AO Configuration Register, 3-16 to 3-17 AT-MIO E series boards. See also theory of operation. DAC FIFO Data Register, 3-18 block diagrams DAC0 Direct Data Register, 3-19...
Page 161 GPCT0<C..A>, 3-26 2-10 to 2-11, 5-1 GPCT1<C..A>, 3-26 reading from, 5-1 to 5-2 GroundRef, 3-17 writing to accidentally (note), 5-1 Input<C..A>, 3-25 NI-DAQ calibration function, 5-9 Int/Ext Trig, 3-6 LastChan, 3-10 LASTCHANNEL, 2-12 © National Instruments Corporation AT-MIO E Series RLPM...
Page 162 Channel B Mode Register, 3-23 customer communication, xi, B-1 to B-2 Channel C Mode Register, 3-24 ChanType<2..0> bit, 3-12 Clear_FIFO function, 4-8 configuration memory definition, 2-9 multirate scanning without ghost (table), 2-17 AT-MIO E Series RLPM © National Instruments Corporation...
Page 163 See programming Channel A Mode Register, 3-22 examples. Channel B Mode Register, 3-23 DAQ_STC_Windowed_Mode_Read Channel C Mode Register, 3-24 function, 4-4 G0 G1 Select Register, 3-26 DAQ_STC_Windowed_Mode_Write overview, 3-21 function, 4-4 © National Instruments Corporation AT-MIO E Series RLPM...
Page 164 G0_Watch function, 4-42 ESERFNCT.c example file, 4-4 Gain<2..0> bits, 3-11 ESERRLP.h example file, 4-4 GATE signal, timing I/O circuitry, 2-24 event counting example, 4-42 to 4-44 gated event counting example, 4-42 to 4-44 AT-MIO E Series RLPM © National Instruments Corporation...
Page 165 4:2:1 Kick_Start_FIFO function, 4-35, 4-41 sampling rate (figure), 2-15 scanning two channels (figure), 2-14 1:x sampling rate, 2-15 3:1:1 sampling rate, 2-15 LastChan bit, 3-10 LASTCHANNEL bit, 2-12 © National Instruments Corporation AT-MIO E Series RLPM...
Page 166 OKI MSM82C55A CMOS programmable acquiring one sample from channel 0, peripheral interface, A-1 to A-17 4-7 to 4-10 operation of AT-MIO E series boards. See functions for programming, theory of operation. 4-6 to 4-7 OUT signal, timing I/O circuitry, 2-24 sampling one channel on Output<C..A>...
Page 167 DAC0 Direct Data Register, 3-19 SCAN sequence DAC1 Direct Data Register, 3-20 definition, 2-12 overview, 3-16 starting, 2-12 DAQ-STC Register Group, 3-27, 4-1 scanning, multirate. See multirate scanning. DIO Register Group, 3-26 © National Instruments Corporation AT-MIO E Series RLPM...
Page 168 AT-MIO-16DE-10, 2-2 Simple_Gated_Count function, 4-42 AT-MIO-16XE-10, 2-3 single channel vs. dual channel DMA, AT-MIO-16XE-50, 2-5 4-54 to 4-55 components of AT-MIO E series single-point output, analog output timing boards, 2-5 circuitry, 2-22 data acquisition timing circuitry, single-read timing, data acquisition timing...
Page 169 Channel B Mode Register, 3-23 Channel C Mode Register, 3-24 trigger lines, RTSI, programming considerations, 4-48 to 4-49 triggering analog triggering programming considerations, 4-49 to 4-52 theory of operation, 2-19 posttrigger and pretrigger acquisition, 2-18 © National Instruments Corporation I-11 AT-MIO E Series RLPM...

This manual is also suitable for:

At-mio-16e-1 At-mio-16e-2 At-mio-64e-3 At-mio-16e-10 At-mio-16de-10 At-mio-16xe-10 ... Show all

National Instruments AT-MIO E Series Programmer's Manual

About this Manual

Chapter 1 General Description

Chapter 2 Theory of Operation

Chapter 3 Register Map and Descriptions

Chapter 4 Programming

Chapter 5 Calibration

Appendix A

OKI MSM82C55A Data Sheet

Appendix B

Customer Communication

Glossary

Index

Quick Links

Need help?

Questions and answers

Summary of Contents for National Instruments AT-MIO E Series

This manual is also suitable for:

Table of Contents