Main (Video (3/4)) Schematic Diagram - Panasonic SDR-S26P Service Manual

8.15. MAIN (VIDEO (3/4)) SCHEMATIC DIAGRAM

G
TO MAIN CN (G-7)
<TO SYSCON/KAO>
(J91) ADM[0-15]
(J95) ALE
(J94) XWEH
(J93) XWEL
F (J92) XRE
TO MAIN CN (G-7)
<TO SYSCON>
(J97) UNI_CS
(J96) XREADY
(J100) CAM_IRQ
TO MAIN CN (L-7)
<TO USB HOST>
(J52) ARM_USBHOST_RST
TO MAIN CN (F-7)
<TO SYSCON/MEMORY>
(J103) XRST_ARM
E
TO MAIN CN (L-7)
<TO USB HOST>
(J47) USB_VBUS_ON_H
(J51) USB_HOST_ERROR_L
TO MAIN CN (L-7)
<TO USB HOST/USB JACK>
(J50) USB_DET_L
TO MAIN CN (K-6)
<TO MEMORY>
(J14) XSCS0
(J15) XSWE0
(J16) XARD
D
(J17) AADR[1-16]
(J18) ADAT[0-15]
(J19) RY/XBY
NOTE:
DO NOT USE ANY PART NUMBER SHOWN ON
THIS SCHEMATIC DIAGRAM FOR ORDERING.
WHEN YOU ORDER A PART, PLEASE REFER
TO PARTS LIST.
NOTE:
CIRCUIT VOLTAGE AND WAVEFORM DESCRIBED
HEREIN SHALL BE REGARDED AS REFERENCE
INFORMATION WHEN PROBING DEFECT POINT,
BECAUSE IT MAY DIFFER FROM AN ACTUAL MEASURING
C VALUE DUE TO DIFFERENCE OF MEASURING
INSTRUMENT AND ITS MEASURING CONDITION
AND PRODUCT ITSELF.
NOTE:
THE MEASUREMENT MODE OF THE DC VOLTAGE ON THIS DIAGRAM IS PLAYBACK MODE.
THE MEASUREMENT MODE OF THE DC VOLTAGE IN THE BRACKETS ( ) ON THIS DIAGRAM
IS RECORD MODE. (SP MODE)
TO MAIN CN (L-7)
<TO AVIO>
(J53) AVIO_SIF_RST
(J54) SBA_CS
(J55) SBA_SIF_CLK
(J56) SBA_SIF_SDA
TO MAIN CN (L-7)
B
<TO USB HOST/USB JACK>
(J46) VBUS
TO MAIN CN (D-7)
<TO RESIZE>
(J119) ADIN[0-9]
TO MAIN CN (N-7)
<TO SD CARD>
(J35) SD_DOOR_SW
TO MAIN CN (F-7)
<TO RESIZE/LENS DRIVE>
(J108) RESIZE_HD
(J107) RESIZE_VD
TO MAIN CN (F-7)
<TO TG/AFE/RESIZE>
(J106) RESIZE_FCK
A
1 2
TP3003
ADM[0-15]
ADM0
ADM1
ADM2
ADM3
ADM4
ADM5
ADM6
ADM7
ADM8
ADM9
ADM10
ADM11
ADM12
ADM13
ADM14
ADM15
R3091
47k
2.8
0
0
Q3010
R3199
UNR32A500L
47k
(RESET)
USB_DET_L
1.8
IC3003 C0JBAU000024 0
Q3006
(AND GATE)
0 UNR32A300L
1.2 OUT_Y GND 0
4 3 (USB HOST CONTROL)
IN_A 1.2
2
1.8 Vcc NC
5 1
AADR[1-16]
ADAT[0-15]
AADR1
AADR2
AADR3
AADR4
ADIN[0-9]
3 4 5
: VIDEO MAIN SIGNAL PATH IN REC MODE
: VIDEO MAIN SIGNAL PATH IN PLAYBACK MODE
A B C E F G
D
IC3001
MN2WS0056SP1
(VIDEO/AUDIO/PROCESSOR)
C3018
0.1u[KB] 3.0
AB4 VDDIO8
-
ADM[0]
AA7
1.0
ADM[1]
Y7
-
W7 ADM[2]
-
V7 ADM[3]
-
ADM[4]
AA8
-
ADM[5]
Y8
-
W8 ADM[6]
-
V8 ADM[7] MICROCONTROLLER
0
VSSIO8 INTERFACE
W11
-
ADM[8]
AA9
-
Y9 ADM[9]
-
W9 ADM[10]
-
ADM[11]
V9
-
ADM[12]
AA10
-
ADM[13]
Y10
-
W10 ADM[14]
-
ADM[15]
3.0 V10
VDDIO8
AB5
TP3004 R3013 0
XAVALE
AB9
100k 2.8
AB7 XWEH
2.8
AB6 XWEL
2.8
XRE
AA6
2.8
XCS
Y6
C3020 2.8
W6 XWAIT
0.1u[KB] 2.8
V6 CAMMIIRQ
1.2
VDD
AB8
2.8
XRST
AB10
TP3029 C3021 2.8
P12 P80
0.01u[KB] 2.8
P11 P81
R3197 -
P82
P10
10k 1.8
P83
N9
1.8
R3171 1k
M9 P84
0
U11 VSSIO7
1.2
XSCS[0]
U9
C3073
R3037 XSCS[1]
T9
22p 120
R9 XSCS[2]
P9 XSCS[3]
XSCS[4]
U10
XSCS[5]
T10
TP3014
R10 XSCS[6]
R11 XSCS[7]
0.9
XSWE[0]
T8
XSWE[1]
TP3015 R8
0 MEMORY
T12 VSS
2.8
INTERFACE
R13 XARD
XAWE
T13
1.8
VDDIO7
TP3017 AA11
T11 AADR[0]
0
V11 AADR[1]
-
AADR[2]
Y11
-
AADR[3]
U12
-
W12 AADR[4]
0
V12 VSSIO7
1.8
VDDIO7
AB17
NC
M10
C3023 M11 NC
0.1u[KB]
N11 NC
AA21 AA22 AB21 AB22 AA12 AB12 U13 V13 W13 U14 V14 W14 Y13 AA13 AB13 AB11 Y14 AA14 AB14 W15 Y15 AA15 W16 Y16 Y12 AA16 AB16 T14 V15 U15 T15 R15 V16 U16 T16
1.8
0
0
Q3007
UNR32AE00L
(VBUS DET.)
6 7
39
: AUDIO MAIN SIGNAL PATH IN REC MODE
: AUDIO MAIN SIGNAL PATH IN PLAYBACK MODE
TO
MAIN (VIDEO (1/4))
SECTION
11
12
AB15 U17 T17 Y17 W17 V17 Y18 W18 V18
13
14
15
16
17
18
LOCATION MAP
19
20
21
1.8 0
22
1/4 2/4
Q3008
1.8
UNR31A400L
(VBUS DET.)
23
24 3/4 4/4
25
26
27
28
SDR-S26
MAIN (VIDEO (3/4))
SCHEMATIC DIAGRAM
8 9 10
SDR-S26P