Table of Contents
Advertisement
Quick Links
General Description
The Cypress S29CD-J and S29CL-J devices are Floating Gate products fabricated in 110-nm process technology. These burst-
mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks,
using separate data and address pins. These products can operate up to 75 MHz (32 Mb) or 66 MHz (16 Mb), and use a single V
of 2.5V to 2.75V (S29CD-J) or 3.0V to 3.6V (S29CL-J) that make them ideal for today's demanding automotive applications.
Distinctive Characteristics
Single 2.6V (S29CD-J) or 3.3V (S29CL-J) for read/program/
erase
110 nm Floating Gate Technology
Simultaneous Read/Write operation with zero latency
x32 Data Bus
Dual Boot Sector Configuration (top and bottom)
Flexible Sector Architecture
– CD016J and CL016J: Eight 2k Double word, Thirty 16k
Double word, and Eight 2k Double Word sectors
– CD032J and CL032J: Eight 2k Double word, Sixty-two 16k
Double Word, and Eight 2k Double Word sectors
VersatileI/O™ control (1.65V to 3.6V)
Programmable Burst Interface
– Linear for 2, 4, and 8 double word burst with wrap around
Secured Silicon Sector that can be either factory or
customer locked
20 year data retention (typical)
Cycling Endurance: 1 million write cycles per sector (typical)
Command set compatible with JEDEC (JC42.4) standard
Cypress Semiconductor Corporation
Document Number: 002-00948 Rev. *C
32/16 Mbit, 2.6/3.3 V, Dual Boot,
Simultaneous Read/Write, Burst Flash
Supports Common Flash Interface (CFI)
Extended Temperature range
Persistent and Password methods of Advanced Sector
Protection
Unlock Bypass program command to reduce programming
time
ACC input pin to reduce factory programming time
Data Polling bits indicate program and erase operation
completion
Hardware (WP#) protection of two outermost sectors in the
large bank
Ready/Busy (RY/BY#) output indicates data available to
system
Suspend and Resume commands for Program and Erase
Operation
Offered Packages
– 80-pin PQFP
– 80-ball Fortified BGA (13 x 11 mm and 11 x 9mm versions)
– Pb-free package option available
– Known Good Die
•
198 Champion Court
,
•
San Jose
CA 95134-1709
S29CD032J
S29CD016J
S29CL032J
S29CL016J
CC
•
408-943-2600
Revised November 08, 2017
Advertisement
Table of Contents
Subscribe to Our Youtube Channel
Related Manuals for Cypress S29CD032J
Summary of Contents for Cypress S29CD032J
- Page 1 Simultaneous Read/Write, Burst Flash General Description The Cypress S29CD-J and S29CL-J devices are Floating Gate products fabricated in 110-nm process technology. These burst- mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks, using separate data and address pins.
- Page 2 18 µs Sector Erase 1.0 s Notice for the 32Mb S29CD-J and S29CL-J devices only: Refer to the application note “Recommended Mode of Operation for Cypress ® 110 nm S29CD032J/S29CL032J Flash Memory” publication number S29CD-CL032J_Recommend_AN for programming best practices. Document Number: 002-00948 Rev. *C...
-
Page 3: Table Of Contents
8.6 Hardware Data Protection Methods......43 Products ................ 74 PSoC® Solutions ............74 Secured Silicon Sector Flash Memory Region ..44 Cypress Developer Community ........74 9.1 Secured Silicon Sector Protection Bit ......45 Technical Support ............74 Document Number: 002-00948 Rev. *C... -
Page 4: Ordering Information
0 = 5-1-1-1, 6-1-1-1, and above 1 = 4-1-1-1 (40 MHz only) Device Number/Description S29CD032J/S29CD016J (2.5 volt-only), S29CL032J/S29CL016J (3.3 Volt-only) 32 or 16 Mbit (1M or 512k 32-Bit) CMOS Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory Manufactured on 110 nm floating gate technology Document Number: 002-00948 Rev. -
Page 5: Valid Combinations
S29CD032J S29CD016J S29CL032J S29CL016J Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S29CD-J/CL-J Valid Combinations... -
Page 6: Input/Output Descriptions And Logic Symbols
S29CD032J S29CD016J S29CL032J S29CL016J 2. Input/Output Descriptions and Logic Symbols Table identifies the input and output package connections provided on the device. Symbol Type Description Address lines for S29CD-J and S29CL-J (A18-A0 for 16 Mb and A19-A0 for 32 Mb). A9 supports... -
Page 7: Block Diagram
S29CD032J S29CD016J S29CL032J S29CL016J 3. Block Diagram –DQ0 Erase Voltage Input/Output Generator Buffers RESET# State Control Command Register PGM Voltage Generator Data Chip Enable Output Enable Y-Decoder Y-Gating Timer Detector Cell Matrix X-Decoder Burst Burst ADV# State Address IND/ Control... -
Page 8: Block Diagram Of Simultaneous Read/Write Circuit
S29CD032J S29CD016J S29CL032J S29CL016J 4. Block Diagram of Simultaneous Read/Write Circuit –A0 Upper Bank Address Upper Bank X-Decoder –A0 STATE RESET# CONTROL Status & –DQ0 COMMAND REGISTER Control ADV# –DQ0 X-Decoder Lower Bank –A0 Lower Bank Address Document Number: 002-00948 Rev. *C... -
Page 9: Physical Dimensions/Connection Diagrams
S29CD032J S29CD016J S29CL032J S29CL016J Physical Dimensions/Connection Diagrams 80-Pin PQFP Connection Diagram 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 DQ16 DQ15 DQ17 DQ14 DQ18 DQ13 DQ19 DQ12 DQ20 DQ11 DQ21 DQ10 DQ22... -
Page 10: Pqr080-80-Lead Plastic Quad Flat Package Physical Dimensions
S29CD032J S29CD016J S29CL032J S29CL016J PQR080–80-Lead Plastic Quad Flat Package Physical Dimensions 0.20 MIN. FLAT SHOULDER PIN S PIN R 7˚ TYP. 0˚MIN. 0.30 ± 0.05 R PIN ONE I.D. GAGE 0.25 PLANE 7˚ TYP. 0˚-7˚ C A B S D S... -
Page 11: 80-Ball Fortified Bga Connection Diagram
S29CD032J S29CD016J S29CL032J S29CL016J 80-Ball Fortified BGA Connection Diagram DQ29 DQ20 DQ16 DQ30 DQ26 DQ24 DQ23 DQ18 IND/WAIT# DQ19 DQ31 DQ28 DQ25 DQ21 DQ27 RY/BY# DQ22 DQ17 DQ10 DQ11 ADV# DQ12 DQ14 RESET# DQ13 DQ15 Notes 6. On 16 Mb device, ball D3 (A19) is NC. -
Page 12: Laa080-80-Ball Fortified Ball Grid Array (13 X 11 Mm) Physical Dimensions
S29CD032J S29CD016J S29CL032J S29CL016J LAA080–80-ball Fortified Ball Grid Array (13 x 11 mm) Physical Dimensions 0.20 A1 CORNER ID. (INK OR LASER) NXφb CORNER 0.20 1.00±0.5 TOP VIEW φ0.25 M φ0.10 CORNER BOTTOM VIEW 0.25 SEATING PLANE 0.15 C SIDE VIEW... -
Page 13: Lad080-80-Ball Fortified Ball Grid Array (11 X 9 Mm) Physical Dimensions
S29CD032J S29CD016J S29CL032J S29CL016J LAD080–80-ball Fortified Ball Grid Array (11 x 9 mm) Physical Dimensions NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER PACKAGE LAD 080 ASME Y14.5M-1994. JEDEC 2. ALL DIMENSIONS ARE IN MILLIMETERS. D X E 11.00 mm x 9.00 mm 3. -
Page 14: Product Overview
S29CD032J S29CD016J S29CL032J S29CL016J Product Overview The S29CD-J and S29CL-J families consist of 32 Mb and 16 Mb, 2.6 volt-only (CD-J) or 3.3 volt-only (CL-J), simultaneous read/ write, dual boot burst mode Flash devices optimized for today's automotive designs. These devices are organized in 1,048,576 double words (32 Mb) or 524,288 double words (16 Mb) and are capable of linear burst read (2, 4, or 8 double words) with wraparound. - Page 15 S29CD032J S29CD016J S29CL032J S29CL016J Notes 8. Secured Silicon Sector overlays this sector when enabled. 9. The bank address is determined by A18 and A17. BA = 00 for Bank 0 and BA = 01, 10, or 11 for Bank 1.
- Page 16 S29CD032J S29CD016J S29CL032J S29CL016J Table 3. S29CD032J/CL032J (Top Boot) Sector and Memory Address Map x32 Address Range Sector Size x32 Address Range Sector Size Sector Sector Group Sector Sector Group (A19:A0) (KDwords) (A19:A0) (KDwords) Bank 0 (Note 15) Bank 1 continued (Note 15) 00000h–007FFh...
- Page 17 S29CD032J S29CD016J S29CL032J S29CL016J Table 3. S29CD032J/CL032J (Top Boot) Sector and Memory Address Map (Continued) x32 Address Range Sector Size x32 Address Range Sector Size Sector Sector Group Sector Sector Group (A19:A0) (KDwords) (A19:A0) (KDwords) Bank 0 (Note 15) Bank 1 continued...
- Page 18 S29CD032J S29CD016J S29CL032J S29CL016J Table 4. S29CD032J/CL032J (Bottom Boot) Sector and Memory Address Map Sector Size x32 Address Range Sector Size x32 Address Range Sector Sector Group Sector Sector Group (A19:A0) (KDwords) (A19:A0) (KDwords) Bank 0 (Note 18) Bank 0 continued...
-
Page 19: Device Operations
S29CD032J S29CD016J S29CL032J S29CL016J 7. Device Operations This section describes the read, program, erase, simultaneous read/write operations, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command... -
Page 20: Asynchronous Read
S29CD032J S29CD016J S29CL032J S29CL016J Asynchronous Read All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs. -
Page 21: Hardware Reset (Reset#)
S29CD032J S29CD016J S29CL032J S29CL016J Hardware Reset (RESET#) The RESET# pin is an active low signal that is used to reset the device under any circumstances. A logic “0” on this input forces the device out of any mode that is currently executing back to the reset state. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the device. - Page 22 S29CD032J S29CD016J S29CL032J S29CL016J The device outputs the initial word subject to the following operational conditions: t specification: The time from the rising edge of the first clock cycle after addresses are latched to valid data on the device IACC outputs.
- Page 23 S29CD032J S29CD016J S29CL032J S29CL016J The IND/WAIT# signal is controlled by the OE# signal. If OE# is at V , the IND/WAIT# signal floats and is not driven. If OE# is at , the IND/ WAIT# signal is driven at V until it transitions to V , indicating the end of the burst sequence.
- Page 24 S29CD032J S29CD016J S29CL032J S29CL016J Figure 4. Initial Burst Delay Control 1st CLK 2nd CLK 3rd CLK 4th CLK 5th CLK ADV# Address 1 Latched Addresses Valid Address Three CLK Delay DQ31-DQ0 Four CLK Delay DQ31-DQ0 Five CLK Delay DQ31-DQ0 Notes 32.
- Page 25 S29CD032J S29CD016J S29CL032J S29CL016J Table 9 describes the Configuration Register settings. Table 9. Configuration Register Configuration Register CR15 = Read Mode (RM) 0 = Synchronous Burst Reads Enabled 1 = Asynchronous Reads Enabled (Default) CR14 = Reserved for Future Enhancements These bits are reserved for future use.
-
Page 26: Autoselect
Table 11. S29CD-J and S29CL-J Flash Family Autoselect Codes (High Voltage Method) Description WE# A19 to A11 A10 A6 A5 to A4 A3 DQ7 to DQ0 Manufacturer ID: Cypress 0001h Read Cycle 1 007Eh 08h or 36h for CD016J 46h for CL016J... -
Page 27: Versatilei/O
A hardware reset immediately terminates the program operation; the program command sequence should be re-initiated once the device has returned to the read mode, to ensure data integrity. For the 32Mb S29CD-J and S29CL-J devices only: Refer to the application note “Recommended Mode of Operation for Cypress ® 110 nm S29CD032J/S29CL032J Flash Memory”... - Page 28 S29CD032J S29CD016J S29CL032J S29CL016J Figure 5. Program Operation START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? Increment Address Last Address? Programming Completed Note 38.See Table 30 Table 35 for program command sequence.
- Page 29 S29CD032J S29CD016J S29CL032J S29CL016J 7.7.3 Chip Erase Chip erase is a six-bus cycle operation as indicated by Command Definitions on page 67. The Chip Erase command is used to erase the entire flash memory contents of the chip by issuing a single command. However, chip erase does not erase protected sectors.
- Page 30 S29CD032J S29CD016J S29CL032J S29CL016J 7.7.4 Erase Suspend / Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation.
- Page 31 S29CD032J S29CD016J S29CL032J S29CL016J 7.7.6 Accelerated Program Operations Accelerated programming is enabled through the ACC function. This method is faster than the standard program command sequences. The device offers accelerated program operations through the ACC pin. When the system asserts V (12V) on the ACC pin, the device automatically enters the Unlock Bypass mode.
-
Page 32: Write Operation Status
S29CD032J S29CD016J S29CL032J S29CL016J Write Operation Status The device provides several bits to determine the status of a program or erase operation. The following subsections describe the function of DQ7, DQ6, DQ2, DQ5, DQ3, and RY/BY#. 7.8.1 DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. - Page 33 S29CD032J S29CD016J S29CL032J S29CL016J 7.8.2 DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
- Page 34 S29CD032J S29CD016J S29CL032J S29CL016J Table 12. DQ6 and DQ2 Indications If device is and the system reads then DQ6 and DQ2 at an address within sectors selected for does not toggles. erasure, toggle, erase suspended, at an address within sectors not selected returns array returns array data.
- Page 35 S29CD032J S29CD016J S29CL032J S29CL016J 7.8.5 DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed.
-
Page 36: Reset Command
S29CD032J S29CD016J S29CL032J S29CL016J Table 13. Write Operation Status Operation RY/BY# (Note 46) (Note 45) (Note 46) DQ7# Toggle No toggle Embedded Program Algorithm Standard Mode Toggle Toggle Embedded Erase Algorithm Reading within Erase No toggle Toggle Suspended Sector Erase... -
Page 37: Advanced Sector Protection/Unprotection
DYB N 4. N = 23 for S29CD016J/CL016J, 5. PPBs programmed individually, 7. Protect effective only if PPB Lock Bit is 31 for S29CD032J/CL032J. but cleared collectively. unlocked and corresponding PPB is “0” (unprotected). 6. 0 = Sector Group Unprotected;... -
Page 38: Advanced Sector Protection Overview
S29CD032J S29CD016J S29CL032J S29CL016J Advanced Sector Protection Overview As shipped from the factory, all devices default to the persistent mode when power is applied, and all sector groups are unprotected. The device programmer or host system must then choose which sector group protection method to use. Programming (setting to “0”) any one of the following two one-time programmable, non-volatile bits locks the device permanently in that mode: ... -
Page 39: Persistent Protection Bits
S29CD032J S29CD016J S29CL032J S29CL016J Persistent Protection Bits The Persistent Protection Bits are unique and nonvolatile. A single Persistent Protection Bit is assigned to a maximum for four sectors (see the sector address tables for specific sector protection groupings). All eight-Kbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. - Page 40 S29CD032J S29CD016J S29CL032J S29CL016J 8.2.2 Erasing PPB The All PPB Erase command is used to erase all the PPBs in bulk. There are no means for individually erasing a specific PPB. The first three cycles of the PPB Erase command are standard unlock cycles. The fourth cycle executes the erase pulse to all the PPBs.
-
Page 41: Persistent Protection Bit Lock Bit
S29CD032J S29CD016J S29CL032J S29CL016J Persistent Protection Bit Lock Bit The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set to “1”, it locks all PPBs; when set to “0”, it allows the PPBs to be changed. There is only one PPB Lock Bit per device. -
Page 42: Password Protection Method
S29CD032J S29CD016J S29CL032J S29CL016J Password Protection Method The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a 64-bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power-up and reset, the PPB Lock Bit is set “1”... -
Page 43: Hardware Data Protection Methods
S29CD032J S29CD016J S29CL032J S29CL016J Hardware Data Protection Methods The device offers several methods of data protection by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describe these methods. 8.6.1 WP# Method The Write Protect feature provides a hardware method of protecting the two outermost sectors of the large bank. -
Page 44: Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is a 256-byte flash memory area that is either programmable at the customer, or by Cypress at the request of the customer. See Table 16 for the Secured Silicon Sector address ranges. -
Page 45: Secured Silicon Sector Protection Bit
S29CD032J S29CD016J S29CL032J S29CL016J Secured Silicon Sector Protection Bit The Secured Silicon Sector can be shipped unprotected, allowing customers to utilize that sector in any manner they choose. Please note the following: The Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. The Secured Silicon Sector Protection Bit must be used with caution as once locked, there is no procedure available for unlocking the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. -
Page 46: Electronic Marking
S29CL016J 10. Electronic Marking Electronic marking has been programmed into the device, prior to shipment from Cypress, to ensure traceability of individual products. The electronic marking is stored and locked within a one-time programmable region. Detailed information on Electronic Marking will be provided in a data sheet supplement. -
Page 47: Electrical Specifications
S29CD032J S29CD016J S29CL032J S29CL016J 12. Electrical Specifications 12.1 Absolute Maximum Ratings Table 17. Absolute Maximum Ratings Parameter Rating Storage Temperature, Plastic Packages –65 °C to +150 °C Ambient Temperature with Power Applied –65 °C to +145 °C (Note 47) for 2.6 V devices (S29CD-J) –0.5V to +3.6V... -
Page 48: Operating Ranges
S29CD032J S29CD016J S29CL032J S29CL016J 13. Operating Ranges Table 18. Operating Ranges Parameter Range Industrial Devices –40°C to +85°C Ambient Temperature (T Extended Devices –40°C to +125°C for 2.6V regulated voltage range (S29CD-J devices) 2.50V to 2.75V Supply Voltages for 3.3V regulated voltage range (S29CL-J devices) 3.00V to 3.60V... -
Page 49: Dc Characteristics
S29CD032J S29CD016J S29CL032J S29CL016J 14. DC Characteristics Table 19. DC Characteristic, CMOS Compatible Parameter Description Test Conditions Unit 1.0 µA Input Load Current to V IO max –25 µA WP# Input Load Current to V LIWP IO max µA A9, ACC Input Load Current ;... -
Page 50: Zero Power Flash
S29CD032J S29CD016J S29CL032J S29CL016J 14.1 Zero Power Flash Figure 14. I Current vs. Time (Showing Active and Automatic Sleep Currents) 1000 1500 2000 2500 3000 3500 4000 Time in ns Note 56.Addresses are switching at 1 MHz. Figure 15. Typical I vs. -
Page 51: Test Conditions
S29CD032J S29CD016J S29CL032J S29CL016J 15. Test Conditions Figure 16. Test Setup Device Under Test 16. Test Specifications Table 20. Test Specifications Test Condition All Options Unit 1 TTL gate Output Load Output Load Capacitance, C (including jig capacitance) Input Rise and Fall Times 0.0V –... -
Page 52: Ac Characteristics
S29CD032J S29CD016J S29CL032J S29CL016J 17. AC Characteristics 17.1 V and V Power-up Table 22. V and V Power-up Parameter Description Test Setup Speed Unit Setup Time µs Setup Time µs VIOS RESET# Low Hold Time µs RSTH Figure 18. V... - Page 53 S29CD032J S29CD016J S29CL032J S29CL016J Figure 19. Conventional Read Operations Timings Addresses Stable Addresses High Z High Z Output Valid Outputs RESET# RY/BY# Figure 20. Asynchronous Command Write Timing ADV# Stable Address Addresses Data Valid Data IND/WAIT# Notes 60. All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/RESET command. Only a single array access occurs after the F0h command is entered.
-
Page 54: Synchronous Operations
S29CD032J S29CD016J S29CL032J S29CL016J 17.3 Synchronous Operations Table 24. Burst Mode for 32 Mb and 16 Mb Parameter Speed Options Description Unit 75 MHz, 66 MHz, 56 MHz, 40 MHz, JEDEC Std. 0J/1J Burst Access Time Valid Clock to Output Delay... - Page 55 S29CD032J S29CD016J S29CL032J S29CL016J Figure 21. Burst Mode Read (x32 Mode) ADVCS ADV# AAVH Addresses BACC Data Da+1 Da+2 Da + 3 Da + 7 IACC AAVS IND# INDS INDH Figure 22. Synchronous Command Write/Read Timing ADVCS ADVP ADV# Valid Address...
-
Page 56: Hardware Reset (Reset#)
S29CD032J S29CD016J S29CL032J S29CL016J 17.4 Hardware Reset (RESET#) Table 25. Hardware Reset (RESET#) Parameter All Speed Description Test Setup Unit Options JEDEC Std. RESET# Pin Low (During embedded Algorithms) to Read or Write µs READY (See Note) RESET# Pin Low (Not during embedded Algorithms) to Read or... -
Page 57: Write Protect (Wp#)
S29CD032J S29CD016J S29CL032J S29CL016J 17.5 Write Protect (WP#) Figure 24. WP# Timing Program/Erase Command Data WPWS Valid WP# BUSY WPRH RY/BY# 17.6 Erase/Program Operations Table 26. Erase/Program Operations Parameter All Speed Description Unit Options JEDEC Std. Write Cycle Time (Note 67) - Page 58 S29CD032J S29CD016J S29CL032J S29CL016J Figure 25. Program Operation Timings Program Command Sequence (last two cycles) Read Status Data (last two cycles) Addresses 555h WHWH1 Status Data BUSY RY/BY# Note 70.PA = program address, PD = program data, D is the true data at the program address.
- Page 59 S29CD032J S29CD016J S29CL032J S29CL016J Figure 27. Back-to-back Cycle Timings Valid RA Addresses Valid PA Valid PA Valid PA GHWL Valid Valid Valid Valid Data SR/W WE# Controlled Write Cycle Read Cycle CE# Controlled Write Cycles Figure 28. Data# Polling Timings (During Embedded Algorithms) ‘...
- Page 60 S29CD032J S29CD016J S29CL032J S29CL016J Figure 29. Toggle Bit Timings (During Embedded Algorithms) Addresses High Z DQ6/DQ2 Valid Status Valid Status Valid Status Valid Data (first read) (second read) (stops toggling) BUSY RY/BY# Note 73.VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
- Page 61 S29CD032J S29CD016J S29CL032J S29CL016J Figure 32. Sector Protect/Unprotect Timing Diagram RESET# SA, A6, Valid* Valid* Valid* A1, A0 Sector Protect/Unprotect Verify Data 60h/68h** 40h/48h*** Status Sector Protect: 150 µs 1 µs Sector Unprotect: 15 ms Notes 79.* Valid address for sector protect: A[7:0] = 3Ah. Valid address for sector unprotect: A[7:0] = 3Ah.
-
Page 62: Alternate Ce# Controlled Erase/Program Operations
S29CD032J S29CD016J S29CL032J S29CL016J 17.7 Alternate CE# Controlled Erase/Program Operations Table 27. Alternate CE# Controlled Erase/Program Operations Parameter Description All Speed Options Unit JEDEC Std. Write Cycle Time (Note 80) AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time... -
Page 63: Erase And Programming Performance
S29CD032J S29CD016J S29CL032J S29CL016J 17.8 Erase and Programming Performance Table 28. Erase and Programming Performance Parameter (Note 84) (Note 85) Unit Comments Sector Erase Time Excludes 00h programming prior to erasure 16 Mb = 23 16 Mb = 230 (Note 87) -
Page 64: Common Flash Memory Interface (Cfi)
32. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100. Contact a Cypress representative for copies of these documents. Table 30. CFI Query Identification String... - Page 65 S29CD032J S29CD016J S29CL032J S29CL016J Table 32. Device Geometry Definition Addresses Data Description Device Size = 2 byte (see description) 0015h = 16 Mb device 0016h = 32 Mb device Flash Device Interface description (for complete description, please refer to CFI publication 100)
- Page 66 S29CD032J S29CD016J S29CL032J S29CL016J Table 33. CFI Primary Vendor-Specific Extended Query (Continued) Addresses Data Description Sector Protect/Unprotect scheme (1 byte) 01 =29F040 mode, 02 = 29F016 mode 03 = 29F400 mode, 04 = 29LV800 mode 0006h 05 = 29BDS640 mode (Software Command Locking)
-
Page 67: Command Definitions
S29CD032J S29CD016J S29CL032J S29CL016J 19. Appendix 2 19.1 Command Definitions Table 34. Memory Array Command Definitions (x32 Mode) Bus Cycles (Notes 93–96) Command (Notes) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data... - Page 68 S29CD032J S29CD016J S29CL032J S29CL016J Table 35. Sector Protection Command Definitions (x32 Mode) Bus Cycles (Notes 108–111) Command (Notes) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset Secured Silicon Sector Entry...
-
Page 69: Revision History
S29CD032J S29CD016J S29CL032J S29CL016J 20. Revision History Document Title: S29CD032J, S29CD016J, S29CL032J, S29CL016J, 32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/ Write, Burst Flash Document Number: 002-00948 Orig. of Submission Rev. ECN No. Description of Change Change Date Spansion Publication Number: S29CD-J_CL-J_00... - Page 70 S29CD032J S29CD016J S29CL032J S29CL016J Document Title: S29CD032J, S29CD016J, S29CL032J, S29CL016J, 32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/ Write, Burst Flash Document Number: 002-00948 Orig. of Submission Rev. ECN No. Description of Change Change Date Asynchronous Command Write Timing In figure, changed tOEH to tWEH; changed tWPH to tOEP.
- Page 71 S29CD032J S29CD016J S29CL032J S29CL016J Document Title: S29CD032J, S29CD016J, S29CL032J, S29CL016J, 32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/ Write, Burst Flash Document Number: 002-00948 Orig. of Submission Rev. ECN No. Description of Change Change Date Global Data sheet format reorganized.
- Page 72 S29CD032J S29CD016J S29CL032J S29CL016J Document Title: S29CD032J, S29CD016J, S29CL032J, S29CL016J, 32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/ Write, Burst Flash Document Number: 002-00948 Orig. of Submission Rev. ECN No. Description of Change Change Date Global Removed “Preliminary” Changed all instances of VCCQ to VIO Distinctive Characteristics Removed “or without”...
- Page 73 S29CD032J S29CD016J S29CL032J S29CL016J Document Title: S29CD032J, S29CD016J, S29CL032J, S29CL016J, 32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/ Write, Burst Flash Document Number: 002-00948 Orig. of Submission Rev. ECN No. Description of Change Change Date Absolute Maximum Ratings Corrected Address, Data, Control Signals identifiers to correctly distinguish different ratings between CL016L, CL032J, CD016J, and CD032J.
-
Page 74: Sales, Solutions, And Legal Information
("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products.
Need help?
Do you have a question about the S29CD032J and is the answer not in the manual?
Questions and answers