Cypress S29GL01GP Manual

General Description
The Cypress S29GL01G/512/256/128P are Mirrorbit
offer a fast page access time of 25 ns with a corresponding random access time as fast as 90 ns. They feature a Write Buffer that
allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than
standard programming algorithms. This makes these devices ideal for today's embedded applications that require higher density,
better performance and lower power consumption.
Distinctive Characteristics
 Single 3V read/program/erase (2.7-3.6 V)
 Enhanced VersatileI/O™ control
– All input levels (address, control, and DQ input levels) and
outputs are determined by voltage on V
to V
CC
 90 nm MirrorBit process technology
 8-word/16-byte page read buffer
 32-word/64-byte write buffer reduces overall programming time for
multiple-word updates
 Secured Silicon Sector region
– 128-word/256-byte sector for permanent, secure identification
through an 8-word/16-byte random Electronic Serial Number
– Can be programmed and locked at the factory or by the
customer
 Uniform 64 Kword/128 Kbyte Sector Architecture
– S29GL01GP: One thousand twenty-four sectors
– S29GL512P: Five hundred twelve sectors
– S29GL256P: Two hundred fifty-six sectors
– S29GL128P: One hundred twenty-eight sectors
 100,000 erase cycles per sector typical
Performance Characteristics
Density Voltage Range
Regulated V
128 & 256 Mb Full V
VersatileIO V
Regulated V
512 Mb Full V
VersatileIO V
Regulated V
1 Gb Full V
VersatileIO V
Notes
Access times are dependent on V
1.
See Ordering Information
Regulated V
: V = 3.0–3.6 V.
CC
CC
Full V
: V = V = 2.7–3.6 V.
CC
CC IO
VersatileIO V
: V = 1.65–V
IO
IO
2. Contact a sales representative for availability.
Cypress Semiconductor Corporation
Document Number: 002-00886 Rev. *B
1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash
with 90 nm MirrorBit Process Technology
®
Flash products fabricated on 90 nm process technology. These devices
input. V range is 1.65
IO IO
Maximum Read Access Times (ns)
Random Access
(1)
Time (t
ACC
90
CC
100/110
CC
110
IO
100
CC
110
CC
120
IO
110
CC
120
CC
130
IO
and V operating ranges.
CC IO
page for further details.
, V = 2.7–3.6 V.
CC CC
• 198 Champion Court
 20-year data retention typical
 Offered Packages
– 56-pin TSOP
– 64-ball Fortified BGA
 Suspend and Resume commands for Program and Erase
operations
 Write operation status bits indicate program and erase operation
completion
 Unlock Bypass Program command to reduce programming time
 Support for CFI (Common Flash Interface)
 Persistent and Password methods of Advanced Sector Protection
 WP#/ACC input
– Accelerates programming time (when V
throughput during system production
– Protects first or last sector regardless of sector protection
settings
 Hardware reset input (RESET#) resets device
 Ready/Busy# output (RY/BY#) detects program or erase cycle
completion
Page Access Time
) (t )
PACC
25
25
25
• San Jose
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
is applied) for greater
HH
CE# Access Time OE# Access Time
(t )
CE
90
100/110
110
100
110
120
110
120
130
,
CA 95134-1709 • 408-943-2600
Revised May 22, 2017
(t )
OE
25
25
25