8.2
Diagram
I2S Post Amplifier & SPIDF Out
Block diagram
BCLK
SDATA
Interface
LRCIN
Pinning information
I2C Control
Interface
Input
Audio Signal
Processing
VDDLA
1
N.C.
2
N.C.
3
N.C.
4
N.C.
5
6
PLL
MCLK
7
CLK_OUT
8
9
DGND
DVDD
10
DEF
11
SDATA
12
Figure 8-3 Internal block diagram and pin configuration
IC Data Sheets
B17, AD82587 (IC U602)
PLL
Internal
System
AD82587
SDM
PCM to PWM
MONO
AD82587
TPM8.3L LA
PLL
Logic
Interface
Clock
Loudspeaker
Driver
VDDRA
36
N.C.
35
N.C.
34
N.C.
33
N.C.
32
N.C.
31
N.C.
30
N.C.
29
N.C.
28
DVDD
27
26
DGND
25
SDA
8.
EN 29
ERROR
L
R
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2011-Sep-30