Data Transfer - Control Data 3234 Series Hardware Reference Manual

The checkword is the 12-bit code left in the cyclic encoder after the last bit of address
or data has entered the encoder. This is then written immediately following the ad-
dress when the address is originally written or at the end of the sector for each write
function (six checkwords are written per sector in the strip file). DUJ;ing subsequent
address verification or read operations the address or data being read is again fed
into the encoder
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and if the original data was written and read correctly, the two check-
words cancel each other. The encoder is then in a clear state. (If any stage of the
encoder is set upon completion of the operation l an error has occurred in either the
original writing on the storage unit or during the subsequent read operation, and a
checkword error indication is generated.)
The theory behind the operation of the cyclic encoder (cyclic code) involves a mathe-
lnatical formula.
t
The error detection capability of the cyclic encoder falls within the
following limits l where a burst equals the number of bits between any two bits in error.
1. If a burst is 12 bits or less l all errors are detected.
2. If a burst is 13 bits, an undetected error occurs approximately every
2-
11
(one out of every 2048 errors is undetected).
3. If a burst is 14 bits or greater, an ·undetected error occurs approximately
-12 .
every 2 (one out of every 4096 errors is undetected).
DATA TRANSFER
Data is addressed and written in a storage unit in discrete blocks (sectors); however
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the data channel can read or record as little as one byte or as many bytes as neces-
sary to reach the end of file or end of cell (in the case of the strip file). When
reading or writing, the operation must commence at the start of a sector. When
writing,
if
less than a full sector is writtenl the remainder of the sector is automati-
cally filled with zeros. The nominal data transfer rate is:
Disk file
Disk drive
Strip file (3234-A/B/C)
98
1
000 bytes per second
100
1
000 bytes per second
36
1
000 bytes per second
t
For a general description of cyclic code theory refer to "Error Correcting Codes!! by
W. Wesley Peterson, MIT Press. For a detailed description of the type of cyclic
encoder used in this controller refer to "A Study of Methods of Error Detection
During Transmission of Binary Inform at ion
II
by Carl Superko, Control Data Corpora-
tion.
1-14
60333300 B