MSI K9A2GM V2 Series Manual page 18

Advance DRAM Configuration -> CAS Latency (CL)
When the DRAM Timing sets to [Manual], the field is adjustable.This controls the CAS
latency, which determines the timing delay (in clock cycles) before SDRAM starts a read
command after receiving it.
Advance DRAM Configuration -> TRCD
When the DRAM Timing sets to [Manual], the field is adjustable. When DRAM is refreshed,
both rows and columns are addressed separately. This setup item allows you to determine
the timing of the transition from RAS (row address strobe) to CAS (column address strobe).
The less the clock cycles, the faster the DRAM performance.
Advance DRAM Configuration -> TRP
When the DRAM Timing sets to [Manual], this field is adjustable. This setting controls the
number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient
time is allowed for the RAS to accumulate its charge before DRAM refresh, refresh may be
incomplete and DRAM may fail to retain data. This item applies only when synchronous
DRAM is installed in the system.
Advance DRAM Configuration -> TRAS
When the DRAM Timing sets to [Manual], this setting determines the time RAS takes to
read from and write to a memory cell.
Advance DRAM Configuration -> TRTP
When the DRAM Timing sets to [Manual], this setting controls the time interval between a
read and a precharge command.
Advance DRAM Configuration -> TRC
When the DRAM Timing sets to [Manual], the field is adjustable. The row cycle time
determines the minimum number of clock cycles a memory row takes to complete a full
cycle, from row activation up to the precharging of the active row.
Advance DRAM Configuration -> TWR
When the DRAM Timing sets to [Manual], the field is adjustable. It specifies the amount of
delay (in clock cycles) that must elapse after the completion of a valid write operation,
before an active bank can be precharged. This delay is required to guarantee that data in
the write buffers can be written to the memory cells before precharge occurs.
Advance DRAM Configuration -> TRRD
When the DRAM Timing sets to [Manual], the field is adjustable. Specifies the
active-to-active delay of different banks.
Advance DRAM Configuration -> TWTR
When the DRAM Timing sets to [Manual], the field is adjustable. This item controls the Write
Data In to Read Command Delay memory timing. This constitutes the minimum number of
clock cycles that must occur between the last valid write operation and the next read
command to the same internal bank of the DDR device.
Advance DRAM Configuration -> 1T/2T Memory Timing
When the DRAM Timing sets to [Manual], the field is adjustable. This field controls the
SDRAM command rate. Selecting [1T] makes SDRAM signal controller to run at 1T
(T=clock cycles) rate. Selecting [2T] makes SDRAM signal controller run at 2T rate.
Advance DRAM Configuration -> SoftWare Memory Hole
When the DRAM Timing sets to [Manual], the field is adjustable. This field allows you to
enable or disable SoftWare Memory Hole.
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