Silicon Laboratories Si5332-AM1 Reference Manual
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Silicon Laboratories Si5332-AM1 Reference Manual

Automotive grade device
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Si5332-AM1/2/3 Automotive Grade Device
Reference Manual
The Si5332-AM1/2/3 is a high-performance, low-jitter clock generator capable of synthe-
sizing five independent banks of user-programmable clock frequencies up to 333.33
MHz, while providing up to 12 differential or 24 single-ended output clocks. The Si5332
supports free run operation using an external crystal as well as lock to an external clock
signal. The output drivers are configurable to support common signal formats, such as
LVPECL, LVDS, HCSL, and LVCMOS. Separate output supply pins allow supply voltag-
es of 3.3 V, 2.5 V, 1.8 V and 1.5 V (CMOS only) to power the multi-format output drivers.
The core voltage supply (VDD) accepts 3.3 V, 2.5 V, or 1.8 V and is independent from
the output supplies (VDDOs). Using its two-stage synthesis architecture and patented
high-resolution Multisynth technology, the Si5332 can generate three fully independent/
non-harmonically-related bank frequencies from a single input frequency.
VDDA
VDD_XTAL
XA/CLKIN_1
10-30 MHz
PFD
÷ P
1-31
XB
10-50 MHz
CLKIN_2
nCLKIN_2
CLKIN_3
nCLKIN_3
silabs.com | Building a more connected world.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
÷N
0
10-250 MHz
÷N
1
10-250 MHz
10-255
LF
÷O
0
10-312.5 MHz
2.375-2.625 GHz
÷O
1
10-312.5 MHz
÷O
2
10-312.5 MHz
÷M
/M
n
d
÷O
3
10-312.5 MHz
10-255
÷O
4
10-312.5 MHz
8-255
10-50 MHz
10-250 MHz
10-250 MHz
10-250 MHz
RELATED DOCUMENTS
• Any-Frequency 6/8/12-output
programmable clock generators
• Offered in three different package sizes,
supporting different combinations of output
clocks and user configurable hardware
input pins
• 32-pin QFN, up to 6 outputs
• 40-pin QFN, up to 8 outputs
• 48-pin QFN, up to 12 outputs (planned
future device)
• Multisynth technology enables any
÷R
OUT0
frequency synthesis on any output up to
250 MHz using N dividers.
OUT1
÷R
VDDOA
• Output frequencies up to 333.33 MHz
OUT2
÷R
using O dividers.
• Highly configurable output path featuring a
cross point mux
÷R
OUT3
VDDOB
• Up to three independent fractional
÷R
OUT4
synthesis output paths
• Up to five independent integer dividers
÷R
OUT5
• Down and center spread spectrum
• Input frequency range:
÷R
OUT6
• External crystal: 16 MHz to 50 MHz
VDDOC
÷R
• Differential clock: 10 MHz to 250 MHz
OUT7
• LVCMOS clock: 10 MHz to 170 MHz
÷R
OUT8
• Output frequency range:
VDDOD
• Differential: 5 MHz to 333.33 MHz
÷R
OUT9
• LVCMOS: 5 MHz to 170 MHz
• User-configurable clock output signal
÷R
OUT10
format per output: LVDS, LVPECL, HCSL,
VDDOE
LVCMOS
÷R
OUT11
1-63
• Easy device configuration using our
ClockBuilder Pro™
tool available for download from our web
site
• Temperature range: –40 to +105 °C
• Pb-free, RoHS-6 compliant
• For more information, refer to the
Automotive Grade Data Sheet
(CBPro™) software
Si5332
Preliminary Rev. 0.1

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  • Page 1 Si5332-AM1/2/3 Automotive Grade Device Reference Manual The Si5332-AM1/2/3 is a high-performance, low-jitter clock generator capable of synthe- sizing five independent banks of user-programmable clock frequencies up to 333.33 RELATED DOCUMENTS MHz, while providing up to 12 differential or 24 single-ended output clocks. The Si5332 supports free run operation using an external crystal as well as lock to an external clock •...

  • Page 2: Table Of Contents

    Table of Contents 1. Overview ....... . . 3 2. Power Supply Sequencing ......4 3.

  • Page 3: Overview

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Overview 1. Overview In addition to clock generation, the input clocks can bypass the synthesis stage, enabling the Si5332 to be used as a high-performance clock buffer or a combination of a buffer and a generator. The Multisynth dividers have two sets of divide ratio registers, an A set and a B set.

  • Page 4: Power Supply Sequencing

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Power Supply Sequencing 2. Power Supply Sequencing The Si5332 VDD_core voltages are VDD_DIG, VDD_XTAL, and VDDA. These 3 VDD_core pins must all use the same voltage. Power supply sequencing between VDD_core and any VDDOx pin is allowed in any order. However, if desiring to minimize the “bring-up” time, it is recommended that VDD_core is powered up first;...

  • Page 5: Input Clocks

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Input Clocks 3. Input Clocks The Si5332 has three input clock nodes: the XA/XB pair, the CLKIN_2/CLKIN_2# pair, and the CLKIN_3/CLKIN_3# pair. XA/XB supports a crystal input or an external clock input whereas the CLKIN_x/CLKIN_x# pairs support ONLY external clock inputs.

  • Page 6: External Input Clock On Clkin_X/Clkin_X

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Input Clocks 3.1.3 External Input Clock on CLKIN_x/CLKIN_x# When supplying differential input clocks into the CLKIN_x/CLKIN_x# inputs, AC or DC coupling can be used. The figures below show the AC and DC coupled differential input clock connection to the Si5332 clock inputs. (There are some restrictions to observe when using DC coupled input clocks as described further below.) The input clock Format Termination shown in below figures is dependent on...
  • Page 7 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Input Clocks The figure below shows how to connect single-ended input clocks, such as LVCMOS. The single-ended clock must be connected to the positive CLKIN input as shown below. VDD Core Controlled 0.1 µF...

  • Page 8: Calculating Crystal Loading Capacitance

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Input Clocks 3.2 Calculating Crystal Loading Capacitance Crystals will resonate at their specified frequency (i.e., be “on-frequency”) if the capacitive loading across the crystal’s terminals is the same as specified by the crystal manufacturer’s loading capacitance (CL) specification. The total loading capacitance presented to the crystal must factor in all capacitance sources such as parasitic “stray”...
  • Page 9 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Input Clocks × × 4.85 pF 9.7 pF Equation 2 Substituting Equation 1 for CL into Equation 2 will solve for CL in single equation form: × Crystal CL − − Equation 3 Equation 3 can now be used to determine the CL...

  • Page 10: Gpio

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual GPIO 4. GPIO Si5332 features universal General Purpose Input/Output (GPIO) hardware pins whose functions must be programmed in NVM to as- sume a pre-defined function in ClockBuilder Pro during custom configuration file development. Table 4.1. Available GPIO Pin Functions...

  • Page 11: Output Clock Terminations

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Output Clock Terminations 5. Output Clock Terminations The Si5332 supports output formats of LVCMOS, LVDS, LVPECL, and HCSL with some additional format specific features. Each out- put driver is individually programmable to any of the supported formats by use of the following registers.

  • Page 12: Dc-Coupled Output Clock Terminations

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Output Clock Terminations 5.1 DC-Coupled Output Clock Terminations 1.43 V to 3.46 V Zo = 50 Ω OUTx Set output driver to 50 Ω mode. Zo = 50 Ω OUTx Figure 5.1. LVCMOS Termination, Option 1 1.43 V to 3.46 V...
  • Page 13 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Output Clock Terminations 1.71 V to 3.46 V Zo = R OUTx LVDS LVDS driver receiver Zo = R OUTx Figure 5.3. LVDS/LVDS Fast Termination, Option 1 1.71 V to 3.46 V Zo = R...
  • Page 14 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Output Clock Terminations 2.25 V to 3.46 V 2.25 V to 3.46 V Zo = 50 Ω OUTx LVPECL LVPECL driver receiver Zo = 50 Ω OUTx Figure 5.5. LVPECL Termination, Option 1 Table 5.3. LVPECL Termination, Option 1...
  • Page 15 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Output Clock Terminations Table 5.4. LVPECL Termination, Option 2 VDD Standard Resistance Resistance Value 29.5 54 or 0 1.71 V to 3.46 V Zo = 42.5 Ω or 50 Ω OUTx HCSL HCSL driver receiver Zo = 42.5 Ω...

  • Page 16: Ac-Coupled Output Clock Terminations

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Output Clock Terminations 5.2 AC-Coupled Output Clock Terminations 1.71 V to 3.46 V Zo = 42.5 Ω 0.1 µF or 50 Ω OUTx = Zo HCSL HCSL driver receiver Zo = 42.5 Ω or 50 Ω...

  • Page 17: Programming The Volatile Memory (Registers)

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Programming the Volatile Memory (Registers) 6. Programming the Volatile Memory (Registers) The process described in this section is very complex to implement and/or calculate. A device register solution is most easily calculated using CBPro and then exporting the resulting register file to simply download into the device. Using CBPro to craft your register set- ting solution is the most highly recommended approach.

  • Page 18: Programming The Pll

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Programming the Volatile Memory (Registers) 6.1 Programming the PLL The PLL programming involves three distinct constraints: 1. The minimum and the maximum frequencies possible for the PFD (Phase Frequency Detector) at lock. This is set by the reference frequency that sets the input divider P and the active input clock as selected by the IN SEL pins or registers.
  • Page 19 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Programming the Volatile Memory (Registers) Si5332 12-Output Part Si5332 8-Output Part Si5332 6-Output Part Output Frequency The Output Frequency Output Pair Output Pair Output Pair Variable for Solver Group (Future Device) OUT7 OUT5 OUT8...
  • Page 20 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Programming the Volatile Memory (Registers) Note: All these register fields are 15 bits wide. Therefore, the fraction will need to truncate up to this precision. This section fully deter- mines the VCO frequency, the P-divider and the feedback divider for this plan given the choice of using O-dividers {HSDIV} for M-2 output clocks and N-dividers {ID} for two output clocks.

  • Page 21: Programming The Clock Path

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Programming the Volatile Memory (Registers) 6.2 Programming the Clock Path Given a valid VCO frequency for the M unique frequencies, segregate the N-M equal frequencies into outputs from each group Gx in Table 6.2 Output Frequency Variables Grouping and Mapping to Actual Output Pins on page 18.
  • Page 22 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Programming the Volatile Memory (Registers) The ida fraction is represented in register fields IDPA_INTG, IDPA_RES and IDPA_DEN: × vcoFreq IDxA_INTG = floor Foutxa × IDxA_RES × vcoFreq IDxA_INTG IDxA_DEN Foutxa × silabs.com | Building a more connected world.

  • Page 23: Programming The Output Clock Frequency

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Programming the Volatile Memory (Registers) 6.3 Programming the Output Clock Frequency register fields are programmed as shown in the table below. This last step completes the settings of all dividers that will result in the frequency plan. When a valid divider solution space cannot be determined, that frequency plan is not realizable in the Si5332.
  • Page 24 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Programming the Volatile Memory (Registers) Divider Value Register Field Description Driver divider ratio. 0 = disabled OUT10_DIV 1–63 = divide value Driver divider ratio. 0 = disabled OUT11_DIV 1–63 = divide value silabs.com | Building a more connected world.

  • Page 25: Programming The Output Clock Format

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Programming the Volatile Memory (Registers) 6.4 Programming the Output Clock Format The following tables provide the method to fully define every driver. Table 6.7. Driver Set Up Options Driver Register Field Description Software interpreted driver configuration. See Table 6.8 Driver...
  • Page 26 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Programming the Volatile Memory (Registers) drvxy_MODE Driver Mode Reserved Reserved Reserved silabs.com | Building a more connected world. Preliminary Rev. 0.1 | 26...

  • Page 27: Programming For Frequency Select Operations

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Programming the Volatile Memory (Registers) 6.5 Programming for Frequency Select Operations Every has a Bank A and a Bank B divider. The register field names that begin with denote Bank B hsdiv hsdivxb idxb dividers.

  • Page 28: Programming Spread Spectrum

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Programming the Volatile Memory (Registers) 6.6 Programming Spread Spectrum Spread spectrum clocking (SSC) is available only on the Multisynth outputs. Each Multisynth can implement spread spectrum in either the main divider or the backup divider (the FS option). Therefore, the user can program a maximum of four different spread spectrum “profiles”...
  • Page 29 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Programming the Volatile Memory (Registers) Table 6.10. SCC Register Fields Spread spectrum enable. This is the only bank configuration field which may be changed dynamical- ly while the bank is selected as the active bank. Users may freely enable/disable spread spectrum.

  • Page 30: Si5332 Pinout And Package Variant

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Si5332 Pinout and Package Variant 7. Si5332 Pinout and Package Variant There are three versions of the Si5332 available for customers. The pinout for each is shown in the figures below. Figure 7.1. 12-Output Si5332 7x7 mm QFN Package Note: Planned future product not yet released.
  • Page 31 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Si5332 Pinout and Package Variant Figure 7.2. 8-Output Si5332 6x6 mm QFN Package Figure 7.3. 6-Output Si5332 5x5 mm QFN Package silabs.com | Building a more connected world. Preliminary Rev. 0.1 | 31...

  • Page 32: Recommended Schematic And Layout Practices

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Recommended Schematic and Layout Practices 8. Recommended Schematic and Layout Practices The Si5332 schematic and layout design can be referenced from the respective EVB design for Si5332. For each package, the User’s Guide (links below) outlines the EVB design and provides links to schematic and layout references for each package type.

  • Page 33: Register Map

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map 9. Register Map All common registers are listed in the table below. The registers that are specific to the 32-QFN part are listed in Table 9.2 Si5332 32- QFN Registers on page 43.
  • Page 34 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length DEVICE_REV Device revision READY/ ACTIVE DEVICE_GRADE Device grade information FACTORY_OPN_ID0 The Orderable part number identification, OPN ID-0. Example: For Si5332AD98765-AM1, ID-0 = 5.
  • Page 35 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length OMUX0_SEL1 Selects output mux clock source for output READY/ ACTIVE clocks in group G0:OUT0 for AM1, AM2: 0 = HSDIV0 1 = HSDIV1...
  • Page 36 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length OMUX2_SEL1 Selects output mux clock source for output READY/ ACTIVE clocks in group G2: OUT2 for AM1; OUT2, OUT3 for AM2: 0 = HSDIV0...
  • Page 37 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length OMUX4_SEL1 Selects output mux clock source for output READY/ ACTIVE clocks in group G4: OUT4 for AM1; OUT6 for AM2: 0 = HSDIV0...
  • Page 38 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length HSDIV2B_DIV O2 divider value for bank B HSDIV3A_DIV O3 divider value for bank A HSDIV3B_DIV O3 divider value for bank B HSDIV4A_DIV...
  • Page 39 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length ID0A_INTG The terms of an a + b/c desired divider set- READY if divider is ting must be processed into ID0A_INTG, currently driving the output, else, ID0A_RES, and ID0A_DEN register terms.
  • Page 40 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length ID0B_INTG The terms of an a + b/c desired divider set- READY if divider is ting must be processed into ID0B_INTG, currently driving the output, else, ID0B_RES, and ID0B_DEN register terms.
  • Page 41 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length ID1A_SS_ENA Spread spectrum enable. This is the only READY if divider is bank configuration field which may be currently driving the changed dynamically while the bank is se- output, else, lected as the active bank.
  • Page 42 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length IDPA_INTG The terms of an a + b/c desired divider set- READY ting must be processed into IDPA_INTG, IDPA_RES, and IDPA_DEN register terms.
  • Page 43 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Table 9.2. Si5332 32-QFN Registers Register Field Name Address Base R/W/RW Description Device Mode Length OUT0_MODE Software interpreted driver configu- READY ration. See Table 6.7 Driver Set Up Options on page OUT0_DIV Driver divider ratio.
  • Page 44 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length OUT1_CMOS_INV Sets the polarity of the two outputs READY in dual CMOS mode. 0 = no inversion 1 = OUT1b inverted OUT1_CMOS_SLEW...
  • Page 45 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length OUT3_MODE Software interpreted driver configu- READY ration. See Table 6.7 Driver Set Up Options on page OUT3_DIV Driver divider ratio. READY 0 = disabled...
  • Page 46 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length OUT4_CMOS_SLEW Controls CMOS slew rate from fast READY to slow. 00 = fastest 01 = slow 10 = slower 11 = slowest OUT4_CMOS_STR CMOS output impedance control.
  • Page 47 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length OUT4_OE Output enable control for OUT4 READY/ ACTIVE CLKIN_2_CLK_SEL 0 = disabled READY 1 = differential 2 = CMOS DC 3 = CMOS AC...
  • Page 48 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Table 9.3. Si5332 40-QFN Registers Register Field Name Address Base R/W/RW Description Device Mode Length OUT0_MODE Software interpreted driver configu- READY ration. See Table 6.7 Driver Set Up Options on page OUT0_DIV Driver divider ratio.
  • Page 49 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length OUT1_CMOS_INV Sets the polarity of the two outputs READY in dual CMOS mode. 0 = no inversion 1 = OUT1b inverted OUT1_CMOS_SLEW...
  • Page 50 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length OUT3_MODE Software interpreted driver configu- READY ration. See Table 6.7 Driver Set Up Options on page OUT3_DIV Driver divider ratio. READY 0 = disabled...
  • Page 51 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length OUT4_CMOS_SLEW Controls CMOS slew rate from fast READY to slow. 00 = fastest 01 = slow 10 = slower 11 = slowest OUT4_CMOS_STR CMOS output impedance control.
  • Page 52 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length OUT6_SKEW Skew control. Programmed as an READY unsigned integer. Can add delay of 35 ps/step up to 280 ps. OUT6_STOP_HIGHZ Driver output state when stopped.
  • Page 53 Si5332-AM1/2/3 Automotive Grade Device Reference Manual Register Map Register Field Name Address Base R/W/RW Description Device Mode Length OUT7_CMOS_SLEW Controls CMOS slew rate from fast READY to slow. 00 = fastest 01 = slow 10 = slower 11 = slowest OUT7_CMOS_STR CMOS output impedance control.

  • Page 54: Revision History

    Si5332-AM1/2/3 Automotive Grade Device Reference Manual Revision History 10. Revision History Revision 0.1 September 20, 2019 • Initial release. silabs.com | Building a more connected world. Preliminary Rev. 0.1 | 54...
  • Page 55 Trademark Information Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, ClockBuilder®, CMEMS®, DSPLL®, EFM®, EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®, Gecko OS, Gecko OS Studio, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress®...

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