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L
- J
, 1 0 - O
O W
I T T E R
C
G
L O C K
E N E R A T O R
Features
Generates free-running or
synchronous output clocks
MultiSynth™ technology enables
any-frequency synthesis on any-
output with 0 ppm frequency
accuracy with respect to the input
Highly configurable outputs
compatible with LVDS, LVPECL,
LVCMOS, HCSL, or programmable
voltage swing and common mode
Excellent jitter: <100 fs RMS typ
Input frequency range:
External crystal: 25, 48-54 MHz
Differential clock: 10 to 750 MHz
LVCMOS clock: 10 to 250 MHz
Output frequency range:
Differential: 100 Hz to 800 MHz
LVCMOS: 100 Hz to 250 MHz
Output-output skew: <100 ps
Adjustable output-output delay
Optional zero delay mode
Independent glitchless on-the-fly
output frequency changes
Applications
Clock tree generation replacing
XOs, buffers, signal format
translators
Any-frequency synchronous clock
translation
Clocking for FPGAs, processors,
memory
Description
The any-frequency, any-output Si5341/40 clock generators combine a wide-band
PLL with proprietary MultiSynth fractional synthesizer technology to offer a
versatile and high performance clock generator platform. This highly flexible
architecture is capable of synthesizing a wide range of integer and non-integer
related frequencies up to 800 MHz on 10 differential clock outputs while
delivering sub-100 fs rms phase jitter performance and 0 ppm error. Each of the
clock outputs can be assigned its own format and output voltage enabling the
Si5341/40 to replace multiple clock ICs and oscillators with a single device
making it a true "clock tree in a chip".
The Si5341/40 can be quickly and easily configured using ClockBuilder Pro
software. Custom part numbers are automatically assigned using a
ClockBuilderPro
for fast, free, and easy factory programming, or the Si5341/40
can be programmed in-circuit via I
Preliminary Rev. 0.9 7/14
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
, A
U T P U T
NY
DCO mode with frequency
increment and decrement as low as
0.001 ppb/step
Core voltage:
V
: 1.8 V ±5%
DD
V
: 3.3 V ±5%
DDA
Independent output supply pins:
3.3V, 2.5V, or 1.8V
Built-in power supply filtering
Status monitoring: LOS, LOL
2
Serial Interface: I
or 4-wire)
In-circuit programmable with non-
volatile OTP memory (2x
programmable)
TM
ClockBuilder Pro
simplifies device configuration and
assigns customer part numbers
Si5341: 4 input, 10 output, 64 QFN
Si5340: 4 input, 4 output, 44 QFN
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
Ethernet switches/routers
OTN framers/mappers/processors
Test equipment & instrumentation
Broadcast video
2
C and SPI serial interface.
Copyright © 2014 by Silicon Laboratories
-F
, A
R E Q U E N C Y
C or SPI (3-wire
software utility
IN1
IN1
IN_SEL0
IN_SEL1
SYNC
RST
X1
XA
XB
X2
OE
INTR
VDDA
IN2
IN2
SCLK
IN1
IN1
IN_SEL0
X1
XA
XB
X2
VDDA
VDDA
IN2
IN2
S i5341/40
-O
NY
U T P U T
Ordering Information:
See section 7
Pin Assignments
Si5341 64QFN
Top View
1
2
3
4
5
6
7
GND
8
Pad
9
10
11
12
13
14
15
16
Si5340 44QFN
Top View
1
33
2
32
3
31
4
30
5
29
GND
6
28
Pad
27
7
26
8
9
25
10
24
11
23
Si5341/40
FINC
48
47
LOL
46
VDD
45
OUT6
OUT6
44
43
VDDO6
42
OUT5
41
OUT5
VDDO5
40
39
I2C_SEL
38
OUT4
37
OUT4
VDDO4
36
OUT3
35
34
OUT3
33
VDDO3
INTR
VDD
OUT2
OUT2
VDDO2
LOS_XAXB
LOL
VDDS
OUT1
OUT1
VDDO1
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Table of Contents
Related Manuals for Silicon Laboratories Si5341
Summary of Contents for Silicon Laboratories Si5341
- Page 1 VDDA clock outputs can be assigned its own format and output voltage enabling the OUT1 VDDA Si5341/40 to replace multiple clock ICs and oscillators with a single device OUT1 VDDO1 making it a true “clock tree in a chip”. The Si5341/40 can be quickly and easily configured using ClockBuilder Pro software.
- Page 2 Si5341/40 Functional Block Diagram Si5341/40 IN_SEL ÷INT ÷INT ÷INT ÷INT FB_IN Multi ÷INT OUT0 Synth Multi ÷INT OUT1 Synth Multi ÷INT OUT2 Synth Multi ÷INT OUT3 Synth Multi ÷INT OUT4 Synth ÷INT OUT5 ÷INT OUT6 C/SPI ÷INT OUT7 Control/ ÷INT...
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Page 3: Table Of Contents
8. Package Outlines ............40 8.1. Si5341 9x9 mm 64-QFN Package Diagram .......40 8.2. -
Page 4: Typical Application Schematic
1x 125 MHz On-a-Chip” LVPECL ÷ 2x 125 MHz 3.3V LVCMOS 2x 125 MHz 3.3V LVCMOS 200MHz 2x 200 MHz 2.5V LVCMOS 2x 200 MHz 2.5V LVCMOS Figure 1. Using The Si5341 to Replace a Discrete Clock Tree Preliminary Rev. 0.9... -
Page 5: Electrical Specifications
— Notes: 1. Si5341 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors. 2. Si5340 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors. 3. Differential outputs terminated into an AC coupled 100 load. - Page 6 Si5341/40 Table 3. Input Specifications = 1.8 V ±5%, V = 3.3 V ±5%, T = –40 to 85 °C) Parameter Symbol Test Condition Units Differential or Single-Ended - AC Coupled (IN0/IN0, IN1/IN1, IN2/IN2, FB_IN/FB_IN) Input Frequency Range — IN_DIFF Voltage Swing <...
- Page 7 = 3.3 V ±5%, V = 3.3 V ±5%, 1.8 V ±5%, T = –40 to 85 °C) Parameter Symbol Test Condition Units Si5341 Control Input Pins (I2C_SEL, IN_SEL[1:0], RST, OE, SYNC, A1, SCLK, A0/CS, FINC, FDEC) Input Voltage -0.1 — 0.3xV DDIO 0.7xV —...
- Page 8 Si5341/40 Table 5. Differential Clock Output Specifications (Continued) = 1.8 V ±5%, V = 3.3V ±5%, V = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T = –40 to 85 °C) Parameter Symbol Test Condition Units Output Voltage Swing Normal Swing Mode = 3.3 V,...
- Page 9 = 3.3 V ±5%, V = 3.3 V ±5%, 1.8 V ±5%, T = –40 to 85 °C) Parameter Symbol Test Condition Units Si5341 Status Output Pins (LOL, INTR) Output Voltage = –2 mA x 0.75 — — DDIO = 2 mA —...
- Page 10 Si5341/40 Table 7. LVCMOS Clock Output Specifications = 1.8 V ±5%, V = 3.3 V ±5%, V = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T = –40 to 85 °C) Parameter Symbol Test Condition Units Output Frequency 0.0001...
- Page 11 Si5341/40 Table 7. LVCMOS Clock Output Specifications (Continued) = 1.8 V ±5%, V = 3.3 V ±5%, V = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T = –40 to 85 °C) Parameter Symbol Test Condition Units...
- Page 12 Si5341/40 Table 8. Performance Characteristics = 1.8 V ±5%, V = 3.3 V ±5%, T = –40 to 85 °C) Parameter Symbol Test Condition Units PLL Loop Bandwidth — — Initial Start-Up Time Time from power-up to when the —...
- Page 13 Si5341/40 Table 9. I C Timing Specifications (SCL,SDA) Parameter Symbol Test Condition Units Standard Mode Fast Mode 100 kbps 400 kbps SCL Clock Frequency SMBus Timeout — When Timeout is Enabled Hold time — — µs HD:STA (repeated) START condition Low period of the —...
- Page 14 Si5341/40 Figure 2. I C Serial Port Timing Standard and Fast Modes Preliminary Rev. 0.9...
- Page 15 Si5341/40 Table 10. SPI Timing Specifications = 1.8 V ±5%, V = 3.3V ±5%, T = –40 to 85 °C) Parameter Symbol Units SCLK Frequency — — SCLK Duty Cycle — SCLK Rise & Fall Time Tr/Tf — — SCLK High & Low Time SCLK Period —...
- Page 16 1. The Si5341/40 is designed to work with crystals that meet the specifications in Table 11. 2. Refer to the Si5341/40 Family Reference Manual for recommended 48 to 54 MHz crystals. Crystal frequencies from 24.97 to 54.06 MHz are supported, but jitter performance is best from 48 to 54 MHz.
- Page 17 Si5341/40 Table 12. Thermal Characteristics Parameter Symbol Value Units Test Condition Si5341 - 64QFN Thermal Resistance Still Air °C/W Junction to Ambient Air Flow 1 m/s 19.4 Air Flow 2 m/s 18.3 Thermal Resistance Junction to Case ...
- Page 18 Si5341/40 1,2,3,4 Table 13. Absolute Maximum Ratings Parameter Symbol Test Condition Value Units Storage Temperature Range –55 to +150 °C DC Supply Voltage –0.5 to 3.8 –0.5 to 3.8 –0.5 to 3.8 Input Voltage Range IN0-IN2, FB_IN -0.85 to 3.8 IN_SEL[1:0], -0.5 to 3.8...
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Page 19: Detailed Block Diagrams
OUT6 ÷R OUT6 Mode ÷ VDDO7 OUT7 FB_IN ÷R ÷P OUT7 FB_IN ÷ VDDO8 OUT8 ÷R OUT8 I2C_SEL ÷ VDDO9 SDA/SDIO OUT9 ÷R SPI/ OUT9 A1/SDO Frequency Status SCLK Control Monitors A0/CS Figure 4. Si5341 Block Diagram Preliminary Rev. 0.9... - Page 20 Si5341/40 Free Run Si5340 Mode Clock ÷P Generator 25MHz, 48-54MHz Dividers/ MultiSynth XTAL Drivers VDDO0 OUT0 ÷R ÷ OUT0 Synchronous Mode VDDO1 OUT1 ÷R ÷ OUT1 ÷P ÷ VDDO2 OUT2 ÷R ÷ ÷P OUT2 VDDO3 OUT3 ÷P ÷R ÷ OUT3...
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Page 21: Functional Description
4. Functional Description The high-resolution fractional MultiSynth™ dividers enables true any-frequency input to any-frequency on The Si5341/40 combines a wide band PLL with next any of the outputs. The output drivers offer flexible generation MultiSynth technology to offer the industry’s output formats which are independently configurable on most versatile and high performance clock generator. -
Page 22: Frequency Configuration
4.1.3. Synchronous Mode information on PCB layout recommendations for the If one of the input pins (IN0-IN2) is selected, the Si5341/ crystal to ensure optimum jitter performance. Refer to 40 will operate in synchronize mode if there is a valid Table 11 for crystal specifications. - Page 23 Si5341/40 ÷P Differential XO Connection ÷P 2xCL XTAL ÷P Single-ended XO Connection Crystal Resonator Connection Figure 7. Crystal Resonator and External Reference Clock Connection Options 4.3.2. Input Clocks (IN0, IN1, IN2) Three input clocks are available to synchronize the PLL when operating in synchronous mode. Each of the inputs can be configured as differential, single-ended, or LVCMOS.
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Page 24: Fault Monitoring
Free-run mode (default) 4.4. Fault Monitoring The Si5341/40 provides fault indicators which monitor loss of signal (LOS) of the inputs (IN0, IN1, IN2, XA/XB, FB_IN) and loss of lock (LOL) for the PLL. This is shown in Figure 9. Si5341/40 ÷P... -
Page 25: Outputs
Si5341/40 4.5. Outputs The Si5341 supports 10 differential output drivers which can be independently configured as differential or LVCMOS. The Si5340 supports 4 output drivers independently configurable as differential or LVCMOS. 4.5.1. Output Signal Format The differential output swing and common mode voltage are both fully programmable and compatible with a wide variety of signal formats including LVDS and LVPECL. - Page 26 Si5341/40 4.5.4. Programmable Common Mode Voltage For Differential Outputs The common mode voltage (V ) for the differential Normal and High Swing modes is programmable in 100 mV increments from 0.7 V to 2.3 V depending on the voltage available at the output’s VDDO pin. Setting the common mode voltage is useful when DC coupling the output drivers.
- Page 27 – t 4.5.12. Output Skew Control (t The Si5341/40 uses independent MultiSynth dividers (N ) to generate up to 5 unique frequencies to its 10 - t outputs through a crosspoint switch. By default all clocks are phase aligned. A delay path (t ) associated with each of these dividers is available for applications that need a specific output skew configuration.
- Page 28 ÷R OUT9 External Feedback Path Figure 13. Si5341 Zero Delay Mode Setup 4.5.14. Sync Pin (Synchronizing R Dividers) All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable phase alignment across all output drivers. Resetting the device using the RST pin or asserting the hard reset bit will have the same result.
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Page 29: Power Management
Consult the Si5341/40 Family Reference Manual and ClockBuilder Pro configuration utility for details. 4.7. In-Circuit Programming The Si5341/40 is fully configurable using the serial interface (I C or SPI). At power-up the device downloads its default register values from internal non- volatile memory (NVM). -
Page 30: Register Map
A high level map of the registers is shown in “5.2. High-Level Register Map” . Refer to the Si5341/40 Family Reference Manual for a complete list of registers descriptions and settings. - Page 31 Si5341/40 Table 16. High-Level Register Map (Continued) 16-Bit Address Content 8-bit Page 8-bit Register Address Address Range Set Page Address 02–05 XTAL Frequency Adjust 08–2F Input Divider (P) Settings Input Divider (P) Update Bits 35–3D PLL Feedback Divider (M) Settings PLL Feedback Divider (M) Update Bit 47–6A...
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Page 32: Pin Descriptions
Connect these pins directly to the XTAL ground pins. X1, X2, and the XTAL ground pins should be separated from the PCB ground plane. Refer to the Si5341/40 Family Reference Manual for layout guidelines. These pins should be left disconnected when connect- ing XA/XB pins to an external reference clock (REFCLK). - Page 33 Si5341/40 Table 17. Si5341/40 Pin Descriptions (Continued) Pin Name Pin Number Function Pin Type Clock Inputs These pins accept an input clock for synchronizing the device. They support both differential and single-ended clock signals. Refer to "4.3.2. Input Clocks (IN0, IN1, IN2)" on page 23 for input termination options.
- Page 34 Si5341/40 Table 17. Si5341/40 Pin Descriptions (Continued) Pin Name Pin Number Function Pin Type Outputs OUT0 Output Clocks These output clocks support a programmable signal swing & OUT0 common mode voltage. Desired output signal format is configu- rable using register control. Termination recommendations are OUT1 provided in "4.5.2.
- Page 35 Si5341/40 Table 17. Si5341/40 Pin Descriptions (Continued) Pin Name Pin Number Function Pin Type Serial Interface I2C_SEL I2C Select This pin selects the serial interface mode as I C (I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is internally pulled high. See Note 2.
- Page 36 Si5341/40 Table 17. Si5341/40 Pin Descriptions (Continued) Pin Name Pin Number Function Pin Type Control/Status INTR Interrupt This pin is asserted low when a change in device status has occurred. This pin must be pulled-up using an external resistor of at least 1 k.
- Page 37 Si5341/40 Table 17. Si5341/40 Pin Descriptions (Continued) Pin Name Pin Number Function Pin Type FINC — Frequency Increment Pin This pin is used to step-up the output frequency of a selected out- put. The affected output and its frequency change step size is reg- ister configurable.
- Page 38 Pin Name Pin Number Function Pin Type Power Core Supply Voltage The device core operates from a 1.8V supply. See the Si5341/40 Family Reference Manual for power supply filtering recommenda- tions. — VDDA Core Supply Voltage 3.3V This core supply pin requires a 3.3V power source.
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Page 39: Ordering Guide
Si5341/40 7. Ordering Guide Ordering Number of Output Clock Supported Package Temperature Part Number Input/Output Frequency Range Frequency Range (OPN) Clocks (MHz) Synthesis Modes (Typical Jitter) Si5341 Si5341A-A-GM 3/10 0.0001 to 800 MHz Integer (100 fs) 64-Lead -40 to 85 °C... -
Page 40: Package Outlines
Si5341/40 8. Package Outlines 8.1. Si5341 9x9 mm 64-QFN Package Diagram Figure 14 illustrates the package details for the Si5341. Table 18 lists the values for the dimensions shown in the illustration. Figure 14. 64-Pin Quad Flat No-Lead (QFN) Table 18. Package Dimensions Dimension 0.80... -
Page 41: Si5340 7X7 Mm 44-Qfn Package Diagram
Si5341/40 8.2. Si5340 7x7 mm 44-QFN Package Diagram Figure 15 illustrates the package details for the Si5340. Table 19 lists the values for the dimensions shown in the illustration. Figure 15. 44-Pin Quad Flat No-Lead (QFN) Table 19. Package Dimensions Dimension 0.80... -
Page 42: Pcb Land Pattern
Si5341/40 9. PCB Land Pattern Figure 16 illustrates the PCB land pattern details for the devices. Table 20 lists the values for the dimensions shown in the illustration. Si5341 Si5340 Figure 16. PCB Land Pattern Preliminary Rev. 0.9... - Page 43 Si5341/40 Table 20. PCB Land Pattern Dimensions Dimension Si5347 (Max) Si5346 (Max) 8.90 6.90 8.90 6.90 0.50 0.50 0.30 0.30 0.85 0.85 5.30 5.30 5.30 5.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines.
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Page 44: Top Marking
Si5341g- Base part number and Device Grade for Low Jitter, Any-Frequency, 10- output Clock Generator. Si5340g- Si5341: 10-output, 64-QFN Si5340: 4-output, 44-QFN g = Device Grade (A, B, C, D). See "7. Ordering Guide" on page 39 for more information. -
Page 45: Device Errata
Si5341/40 11. Device Errata Please log in or register at www.silabs.com to access the device errata document. Preliminary Rev. 0.9... -
Page 46: Appendix-Advance Product Information Revision History
Added register map information Added package outline, land patterns, ordering guide, top markings Reduced MultiSynth from 10 to 5 Combined Si5341 and Si5340 data sheets Added application diagram 0.21 Minor updates from review cycle July 2013 ... - Page 47 Moved the register descriptions to the Si53451/40 Reference Manual. Jun 2014 Moved the majority of the contents of the Serial Interface section to the Si5341/40 Reference Manual. Changed the output delay specification from “1 ps steps with a range of 8.32 ns”...
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Page 48: Contact Information
Silicon Laboratories products are not designed, intended, or authorized for use in applications intend- ed to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur.
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