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5
XS10 PCMCIA\111410271
INCLK_CI
20
30
MCLKI_A15__19
D0
INVALID_CI
19
31
MIVAL_A16__18
D1
INSYNC_CI
46
32
MISTRT_A17__45
D2
INDATA0_CI
47
2
MDI0_A18__46
D3
INDATA1_CI
48
3
MDI1_A19__47
D4
INDATA2_CI
49
4
MDI2_A20__48
D5
INDATA3_CI
50
5
MDI3_A21__49
D6
INDATA4_CI
53
6
MDI4_A22__52
D7
INDATA5_CI
54
MDI5_A23__53
INDATA6_CI
55
29
D
MDI6_A24__54
A0
INDATA7_CI
56
28
MDI7_A25__55
A1
27
A2
CI_OUTCLK
57
26
MCLKO_VS2__56
A3
CI_OUTVALID
62
25
MOVAL_BVD2__61
CTX_A4__24
CI_OUTSYNC
63
24
MOSTRT_BVD1__62
ITX_A5__23
CI_OUTDATA0
64
23
MDO0_D8__63
ETX_A6__22
CI_OUTDATA1
65
22
MDO1_D9__64
QTX_A7__21
CI_OUTDATA2
66
12
MDO2_D10__65
CRX_A8__11
CI_OUTDATA3
37
11
MDO3_D11__36
DRX_A9__10
CI_OUTDATA4
38
8
MDO4_D12__37
A10
CI_OUTDATA5
39
10
MDO5_D13__38
A11
CI_OUTDATA6
40
21
MDO6_D14__39
A12
CI_OUTDATA7
41
13
MDO7_D15__40
A13
14
A14
CI_REG#
61
R_E_G__60_60_60
CI_CE1#
7
3V
36
C_E_1__6_6_6
C_D_1__35_35_35
CI_CE2#
42
67
C_E_2__41_41_41
C_D_2__66_66_66
CI_OE#
9
43
O_E__8_8_8
VS1
CI_WE#
15
59
W_E__14_14_14
W_A_I_T__58_58_58
CI_IORD#
44
33
I_O_I_S_1_6__WP__32_32_32
I_O_R_D__RFU__43_43_43
CI_IOWR#
45
18
I_O_W_R__RFU__44_44_44
VPP-1_17_17_17
60
52
I_N_P_A_C_K__59_59_59
VPP-2_51_51_51
CI_IREQ#
16
I_R_E_Q__READY__15_15_15
58
C
RESET
68
GND1
35
GND2
34
51
GND3
VCC1
1
17
GND4
VCC2
卧式回流端子
PCM_A0
A0_CI
PCM_CD1_N
R480
0R
R481
PCM_A1
A1_CI
PCM_CD2_N
R483
0R
R484
PCM_A2
A2_CI
PCM_IORD_N
R486
0R
R487
PCM_A3
A3_CI
PCM_IOWR_N
R488
0R
R489
PCM_A4
A4_CI
R490
0R
PCM_A5
A5_CI
PCM_REG_N
R491
0R
R492
PCM_A6
A6_CI
PCM_CE_N
R493
0R
R494
PCM_A7
A7_CI
PCM_OE_N
R495
0R
R496
PCM_A8
A8_CI
PCM_WE_N
R497
0R
R498
PCM_A9
A9_CI
R499
0R
PCM_A10
A10_CI
PCM_IRQA_N
R500
0R
R501
PCM_A11
A11_CI
PCM_WAIT_N
R505
0R
R506
PCM_A12
A12_CI
R507
0R
PCM_A13
A13_CI
PCM_RESET
B
R508
0R
R509
PCM_A14
A14_CI
R510
0R
PCM_D0
D0_CI
R511
0R
PCM_D1
D1_CI
R512
0R
PCM_D2
D2_CI
R513
0R
PCM_D3
D3_CI
R514
0R
PCM_D4
D4_CI
R515
0R
PCM_D5
D5_CI
R516
0R
PCM_D6
D6_CI
R517
0R
PCM_D7
D7_CI
R518
0R
A
5
4
Parrel TS interface
D0_CI
D1_CI
TS_VLD
R455
0R
D2_CI
TS_SYNC
R456
0R
D3_CI
TS_D0
R457
0R
D4_CI
TS_D1
R458
0R
D5_CI
TS_D2
R459
0R
D6_CI
TS_D3
R460
0R
D7_CI
TS_D4
R461
0R
TS_D5
R462
0R
A0_CI
TS_D6
R463
0R
A1_CI
TS_D7
R464
0R
A2_CI
A3_CI
A4_CI
TS_CLK
R465
0R
A5_CI
A6_CI
A7_CI
Closed to Main Chip
A8_CI
A9_CI
A10_CI
A11_CI
A12_CI
A13_CI
A14_CI
TS_MOVLD
R466
0R
CI_CD1#
TS_MOSYNC
R467
0R
CI_CD2#
TS_MDO0
R468
0R
TS_MDO1
R469
0R
CI_WAIT#
VCC_PCMCIA
TS_MDO2
R470
0R
TS_MDO3
R471
0R
TS_MDO4
R472
0R
TS_MDO5
R473
0R
TS_MDO6
R474
0R
CI_RST
TS_MDO7
R475
0R
VCC_PCMCIA
TS_MOCLK
R476
0R
C438
VCC_PCMCIA VCC_PCMCIA VCC_PCMCIA
10p/50V
R502
CI_CD1#
0R
CI_CD2#
4.7k
0R
Closed to Main Chip
CI_IORD#
0R
CI_IOWR#
0R
CI_CE2#
CI_REG#
0R
CE2#一般NC
CI_CE1#
0R
CI_OE#
0R
CI_WE#
0R
CI_IREQ#
0R
CI_WAIT#
0R
CI_RST
0R
4
3
NET
INVALID_CI
INSYNC_CI
INDATA0_CI
INDATA1_CI
TS_MDO[7:0]
INDATA2_CI
TS_MDO[7..0]
TS_MOCLK
INDATA3_CI
TS_MOCLK
TS_MOSYNC
INDATA4_CI
TS_MOSYNC
TS_MOVLD
TS_MOVLD
INDATA5_CI
INDATA6_CI
TS_D[7:0]
INDATA7_CI
TS_D[7..0]
TS_CLK
TS_CLK
TS_SYNC
TS_SYNC
TS_VLD
INCLK_CI
TS_VLD
PCM_CD_N
PCM_RESET
PCM_RESET
PCM_WAIT_N
C437
PCM_REG_N
10p/50V
PCM_OE_N
PCM_WE_N
PCM_IORD_N
Closed to CI SLOT
PCM_IOWR_N
PCM_CE_N
PCM_IRQA_N
CI_OUTVALID
PCM_A[14:0]
CI_OUTSYNC
PCM_D[7:0]
CI_OUTDATA0
CI_OUTDATA1
CI_OUTDATA2
CI_OUTDATA3
CI_OUTDATA4
CI_OUTDATA5
CARD DETECT
CI_OUTDATA6
CI_OUTDATA7
+5V_Normal
CI_OUTCLK
Closed to CI SLOT
R478
R477
1k
1k
PCM_CD1_N
PCM_CD2_N
R503
R504
4.7k
4.7k
PCM_CD1_N
PCM_CD2_N
GND
GND
CI_WAIT#
CI_IREQ#
GND
NC
NC
GND
NC
NC
Closed to CI SLOT
CI Power
+5V_Normal
C435
100u/16V/NC
3
2
PCM_CD_N
PCM_WAIT_N
PCM_REG_N
PCM_OE_N
PCM_WE_N
PCM_IORD_N
PCM_IOWR_N
PCM_CE_N
PCM_IRQA_N
PCM_A[14..0]
PCM_D[7..0]
PCM_CD_N
R479
10k
R482
10k
R485
100k
C439
1n/50V
PCM_CD_N
L
0V
H
2.5V
H
2.5V
H
5V
VCC_PCMCIA
R454
C436
100n/16V
100k
Title
Title
Title
MSD6586
MSD6586
MSD6586
Size
Size
Size
Document Number
Document Number
Document Number
PCMCIA
PCMCIA
PCMCIA
B
B
B
Date:
Date:
Date:
Tuesday, May 09, 2017
Tuesday, May 09, 2017
Tuesday, May 09, 2017
2
1
D
C
B
A
Rev
Rev
Rev
Ver.B
Ver.B
Ver.B
Sheet
Sheet
Sheet
15
15
15
of
of
of
18
18
18
1
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