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General Standards Corporation PCIe-24DSI32 Reference Manual

24-bit, 32-channel delta-sigma, 200 ksps analog input pcie board
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PCIe-24DSI32
Rev: 042514
PCIe-24DSI32
24-BIT, 32-CHANNEL DELTA-SIGMA, 200 KSPS
ANALOG INPUT PCIe BOARD
________________________
REFERENCE MANUAL
_____________________________________________________________________________
General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com

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  • Page 1 PCIe-24DSI32 Rev: 042514 PCIe-24DSI32 24-BIT, 32-CHANNEL DELTA-SIGMA, 200 KSPS ANALOG INPUT PCIe BOARD ________________________ REFERENCE MANUAL _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 2: Table Of Contents

    Settling Delays and the Channels Ready Flag Input Data Buffer 3.5.1 General Characteristics 3.5.2 Data Organization 3.5.2.1 Channel Tags 3.5.2.2 Input Data Format 3.5.3 Buffer Control Register 3.5.3.1 Status Flag and Threshold 3.5.3.2 Buffer Clearing and Disabling _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...
  • Page 3 Board Configuration Register 3-22 3.12 External Independent Burst Triggering 3-23 3.13 Settling TIme Considerations PRINCIPLES OF OPERATION General Description Analog Inputs Autocalibration Sampling Clocks Power Control Appendix A Local Register Quick Reference _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...
  • Page 4 Direct External Clocking 3-14 3.8.1 Interrupt Event Selection 3-18 3.9.1 Typical DMA Register Configuration; Block Mode 3-16 3.9.2 Typical DMA Register Configuration; Demand Mode 3-16 3.10.1 Channel Order 3-20 3.11.1 Board Configuration Register 3-22 _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 5: Introduction

    INTRODUCTION 1.1 General Description The PCIe-24DSI32 board provides 24-bit analog input capability for the PCIe bus at sample rates up to 200 KSPS per channel. In addition to providing 32 analog input channels, this product supports multiboard clocking and synchronization. The board is functionally and mechanically compatible with the PCI Express Specification revision 1.0a.

  • Page 6: Functional Overview

    Hardware sync and clock input/output signals permit multiple boards to be connected together for phase- locked operation from a common clock. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 7: Installation And Maintenance

    The system I/O connector is designed to mate with a 100-pin dual-ribbon connector, equivalent to AMP #749621-9. This insulation displacement (IDC) cable connector accepts two 50-wire 0.050-inch ribbon cables, with the pin numbering convention shown in Table 2.2.2 and in Figure 2.2.2. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 8: System I/O Connections

    INPUT CH 14 HI INPUT CH 30 HI INPUT CH 15 LO INPUT CH 31 LO INPUT CH 15 HI INPUT CH 31 HI INPUT RETURN INPUT RETURN INPUT RETURN INPUT RETURN _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 9: Analog Input Configuration

    Vcm which, for optimum performance, must not exceed the maximum value indicated in the product specification. a. Differential Analog Input b. Single-ended Analog Input Source Figure 2.3.1. Input Configurations _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 10: Single-Ended Input Sources

    2.4.1 Interboard Connections Figure 2.4.1 illustrates how multiple PCIe-24DSI32 boards can be daisy-chained together in an initiator-target sequence to provide common clocking between boards. CLOCK OUTPUT HI/LO lines from an initiator are connected to the CLOCK INPUT HI/LO lines on a target board, and the SYNC output and input pairs are connected similarly.

  • Page 11: Multiboard Synchronization

    This procedure describes the adjustment of the internal reference. For applications in which the system must not be powered down, the adjustment can be performed while the board is installed in an operating system. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 12: Equipment Required

    PCIe-24DSI32 2.6.1 Equipment Required Table 2.6.1 lists the equipment requirements for calibrating the PCIe-24DSI32 board. Alternative equivalent equipment may be used. Table 2.6.1. Reference Adjustment Equipment EQUIPMENT DESCRIPTION MANUFACTURER MODEL Digital Multimeter, 5-1/2 digit, 0.005% Hewlett Packard 34401A accuracy for DC voltage measurements at +10 Volts.
  • Page 13 4. Verify that the digital multimeter indication is +9.9000 VDC ±0.0009 VDC. If the indication is not within this range, adjust the REFERENCE ADJUSTMENT trimmer until the digital multimeter indication is within the specified range. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 14: Control Software

    SECTION 3.0 CONTROL SOFTWARE 3.1 Introduction The PCIe-24DSI32 board is compatible with the PCI Express local bus specification revision 1.0a, and a PLX PEX8311 adapter controls the one-lane interface. Configuration-space registers are initialized internally to support the location of the board on any 32-longword boundary in memory space.

  • Page 15: Board Control Register

    THRESHOLD FLAG OUT Routes the threshold flag to the AUX LVDS output. D23-31 (Reserved) * Cleared automatically. R/W = Read/Write; RO = Read-Only. ** Changes to 0000 783Ch when the input buffer fills. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 16: Configuration And Initialization

     All control registers are initialized; all defaults are invoked,  The local interrupt request is asserted as an initialization-completed event. Upon completion of initialization, the INITIALIZE control bit is cleared automatically. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 17: Analog Input Configuration

    Any one of three input voltage ranges can be selected for all channels. RANGE[1..0] control bits in the BCR select the input range, as shown in Table 3.4.3. Table 3.4.3. Analog Input Range Selection RANGE[1..0] ANALOG INPUT RANGE ±2.5 Volts ±2.5 Volts ±5 Volts ±10 Volts _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 18: Settling Delays And The Channels Ready Flag

    If the input channels are not scan-synchronized (Paragraph 3.10), the order in which channel data accumulates in the buffer is not generally predictable. Therefore, a channel tag that identifies each input channel is attached to associated data values in the buffer. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 19: Input Data Format

    BUFFER UNDERFLOW *** Reports buffer underflow (Read on empty) D[31..26] (Reserved) ** Clears automatically. *** Clear by writing LOW, or by board reset. * Changes to 0103 FFFEh when the buffer fills. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 20: Status Flag And Threshold

    BUFFER OVERFLOW and BUFFER UNDERFLOW status bits in the buffer control register report overflow (write on full) or underflow (read on empty) events. Once set, these status bits remain HIGH until cleared by writing LOW directly, or by a board reset. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 21: Input Sampling Control

    Table 3.6.1.2-2. The Group-0 assignment selects the sample rate source for all groups, while Group 1-3 assignments enable or disable the specific channel groups. Disabled groups do not provide data to the input data buffer. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...
  • Page 22 Figure 3.6.1.1. ADC Clock and Sync Organization, 32 Channels Table 3.6.1.1. Channel Groups CHANNEL 32-CHAN 16-CHAN 8-CHAN GROUP BOARD BOARD BOARD 00-07 00-03 00,01 08-15 04-07 02,03 16-23 08-11 04,05 24-31 12-15 06,07 _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 23: Sample Clock Generation

    This integer controls the sample rate for active channels. Table 3.6.1.3. Rate Divisor Register Offset: 0000 0010h Default: 0000 0005h BIT FIELD: FUNCTION D[07..00] RATE DIVISOR (Ndiv) D[31..08] (Reserved) _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com 3-10...

  • Page 24: Rate Generator Control

    Nvco and Nref each has a maximum range from 30 to 1000, and Fref is the frequency of the reference oscillator, which has a standard frequency of 32.768MHz. Table 3.6.2.1-3 summarizes the sample rate control parameters. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com 3-11...

  • Page 25: Pll Nref Register

    Table 3.6.2.1-3. Summary of PLL Sample Rate Control Parameters PARAMETER NOTATION RANGE VCO Frequency Range 20-55 MHz Fgen VCO Factor Nvco 30-1000 Reference Factor Nref 30-1000 Rate Divisor Ndiv 0 - 25 Reference Frequency Standard value = 32.768MHz Fref _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com 3-12...
  • Page 26 Nvco Fgen Fref Nref 32,768,000 Hz 31,457,280 Hz. Finally, use Equation 3-1 to verify the sample rate Fsamp: Fgen Fsamp 512 * DIVISOR 31,457,280 Hz 15,360 Hz . 512 * 4 _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com 3-13...

  • Page 27: Legacy Rate Generator

    Ndiv. Table 3.6.3. Direct External Clocking Sample Rate External Clock Divisor Integer Fsamp (KSPS) Frequency Ndiv 2-50 256 * Fsamp 2 thru 25 50-100 128 * Fsamp 100-200 64 * Fsamp _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com 3-14...

  • Page 28: Harmonically Locked Channels

    3.6.6 Multiboard Operation Multiple PCIe-24DSI32 boards can be connected together to share a common sampling clock and synchronization command. One of the boards is designated as the initiator, and the remaining boards are designated as targets.

  • Page 29: External Sync

    The SOFTWARE SYNC control bit in the BCR can be used also to clear the buffers on the initiator and target boards simultaneously, by first setting the CLEAR BUFFER ON SYNC control bit HIGH in the BCR. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com 3-16...

  • Page 30: Autocalibration

    INTERRUPT REQUEST FLAG bit is set in the BCR. The request remains asserted until the PCIe bus clears the BCR request flag. A local interrupt request is generated automatically at the end of initialization. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com 3-17...

  • Page 31: Enabling The Pci Interrupt

    The PCIe interrupt is enabled by setting the PCI Interrupt Enable and PCI Local Interrupt Enable control bits HIGH in the runtime Interrupt Control/Status Register described in the PLX reference manual. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com 3-18...

  • Page 32: Dma Operation

    If this occurs, the next sample set flushes the retained data through the PEX8311 adapter to the PCI bus, and no samples are lost. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com 3-19...

  • Page 33: Scan Synchronization

    SYNCHRONIZE SCAN control bit HIGH in the BCR. Table 3.10.1. Channel Order (Active channels 00-07) CHANNEL ORDER SAMPLE EVENT NON-SYNCHRONIZED SYNCHRONIZED SCANS SCANS (Typical) 34567012 01234567 Tn+1 56701234 01234567 Tn+2 01234567 01234567 Tn+3 45670123 01234567 Tn+4 12345670 01234567 _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com 3-20...
  • Page 34 NOTE: If autocalibration is executed while scan-synchronized, repeat the global buffer clear sequence (Steps 3 through 5). To simplify this operation, the CLEAR BUFFER ON SYNC control bit can be allowed to remain HIGH while scan- synchronized. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com 3-21...

  • Page 35: Board Configuration Register

    I/O Pin B1: AUX INPUT LO I/O Pin B2: AUX INPUT HI I/O Pin B3: DGND I/O Pin B4: DGND I/O Pin B5: AUX OUTPUT LO I/O Pin B6: AUX OUTPUT HI. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com 3-22...

  • Page 36: Settling Time Considerations

    100 milliseconds. Low-frequency filters will extend the settling interval by an amount that depends upon the filter characteristics. In general, the longest settling delay consistent with application requirements should be implemented. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com 3-23...
  • Page 37 PCIe-24DSI32 _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com 3-24...

  • Page 38: Principles Of Operation

    PRINCIPLES OF OPERATION 4.1 General Description The PCIe-24DSI32 board contains sixteen dual delta-sigma 24-Bit A/D converters and all supporting functions necessary for adding analog I/O capability to a PCIe expansion system. A PCIe interface adapter (Figure 4.1) provides the interface between the controlling PCIe bus and an internal local controller through a 32-bit local bus.

  • Page 39: Analog Inputs

    4.4 Sampling Clocks An internal sample rate generator provides a frequency range of 20-55 MHz, which is divided down by a software-specified integer to provide sample rates from 2.0 KSPS to 200 KSPS. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 40: Power Control

    PCIe bus to produce preregulated DC voltages that subsequently are postregulated with linear regulators to the required supply voltages. Linear regulators ensure that the final power voltages delivered to the analog networks are well-regulated and free of noise. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 41: Appendix A Local Register Quick Reference

    PCIe-24DSI32 APPENDIX A LOCAL REGISTER QUICK REFERENCE _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 42: Board Control Register

    * Changes to 0000 783Ch when the input buffer fills. ** Changes to 0103 FFFEh when the buffer fills. *** Maintenance register. Shown for reference only. **** May be 0000 0190h in earlier firmware revisions. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...
  • Page 43 THRESHOLD FLAG OUT Routes the threshold flag to the AUX LVDS output. D23-31 (Reserved) * Cleared automatically. R/W = Read/Write; RO = Read-Only. ** Changes to 0000 783Ch when the input buffer fills. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 44: Analog Input Function Selection

    RESERVED (Zero) CHANNEL TAG ZERO-PAD CHANNEL DATA VALUE DATA WIDTH 16 Bits D[31..29] D[28..24] D[23..16] D[15..0] 18 Bits D[31..29] D[28..24] D[23..18] D[17..0] 20 Bits D[31..29] D[28..24] D[23..20] D[19..0] 24 Bits D[31..29] D[28..24] D[23..0] _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 45: Buffer Control Register

    * Changes to 0103 FFFEh when the buffer fills. Table 3.6.1.1. Channel Groups INPUT CHANNELS CHANNEL 32-CHANNEL 16-CHANNEL 8-CHANNEL GROUP BOARD BOARD BOARD 00-07 00-03 00,01 08-15 04-07 02,03 16-23 08-11 04,05 24-31 12-15 06,07 _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...
  • Page 46 (Reserved) * Applies to all channel groups. Disabling Group-0 disables all groups. Table 3.6.1.3. Rate Divisor Register Offset: 0000 0010h Default: 0000 0005h BIT FIELD: FUNCTION D[07..00] RATE DIVISOR (Ndiv) D[31..08] (Reserved) _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...
  • Page 47 Table 3.6.2.2-1. Legacy Rate Control Register Offset: 0008h Default: 0000 0000h * BIT FIELD MODE DESIGNATION FUNCTION D[16..00] RATE CONTROL (Nrate) Frequency control factor; 0-511 D[31..17] (Reserved) * Default frequency is 25.6MHz. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 48: Interrupt Event Selection

    DMA Descriptor Counter Transfer direction; Local bus to PCI bus 0000 000Ah (Analog inputs) DMA Command Status Command and Status Register 0000 0001h 0000 0003h (See Text) * Determined by specific transfer requirements. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...

  • Page 49: Channel Order

    Default: 000X XXXXh BIT FIELD DESCRIPTION D00-D11 Firmware Revision D12-D15 (Reserved status flags). High if the board contains only 16 input channels. High if the board contains only 8 input channels. D18-D31 (Reserved) _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com...
  • Page 50 General Standards Corp. reserves the right to make any changes, without notice, to this product to improve reliability, performance, function, or design. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without prior written consent of General Standards Corp. _____________________________________________________________________________ General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com A-10...
  • Page 51 General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com Web Site: http://www.GeneralStandards.com MAN-PCIe-24DSI32...

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