Watchdog Timer Registers - Asus AAEON BOXER-6614 User Manual

A.1

Watchdog Timer Registers

I/O Base Default Value
Address
0xA00
Register Offset
Watchdog 0x00
WDTRST#
Enable
Pulse Width 0x05
Signal Polarity 0x05
Counting Unit 0x05
Output Signal 0x05
Type
Watchdog 0x05
Timer Enable
Timeout Status 0x05
Timer Counter 0x06
Appendix A – Watchdog Timer Programming
Table 1: Watch dog relative IO address
Note
I/O Base address for Watchdog operation.
This address is assigned by SIO LDN7, register
0x60‐0x61.
Table 2: Watchdog relative register table
BitNum
7
0:1
2
3
4
5
6
Value Note
1 Enable/Disable
time out output via WDTRST#
0: Disable
1: Enable
01 Width of Pulse signal
00: 1ms (do not use)
01: 25ms
10: 125ms
11: 5s
Pulse width is must longer than
16ms.
0 0: low active
1: high active
Must set this bit to 0
0 Select time unit.
0: second
1: minute
1 0: Level
1: Pulse
Must set this bit to 1
1 0: Disable
1: Enable
1 1: timeout occurred. Write a 1 to
clear timeout status
Time of watchdog timer
(0~255)
89