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Terasic THDB-SUM T T T T HDB HDB- - - - SUM Terasic HSMC to Santa Cruz Daughter Board User Manual Document Version 1.3 JULY. 29, 2009 by Terasic...
............................... 18 NTERFACE SMA C ................................19 ONNECTOR I2C S EEPROM ..............................20 ERIAL ................................21 OWER UPPLY DEMONSTRATION ..................................22 THDB-SUM B III S ................22 ONNECTING OARD TO YCLONE TART OARD APPENDIX ......................................24 ................................24 EVISION ISTORY THDB-SUM W ..................
1 1 1 1 Introduction THDB-SUM (HSMC to Santa Cruz / USB / Mictor Daughter Board) is an adapter board to convert High Speed Mezzanine Connector (HSMC) interface to Santa Cruz (SC), USB, Mictor, and SD Card interface. It allows users to use these interface on a host board with a HSMC connector.
Introduction Getting Help Here are some places to get help if you encounter any problem: Email to support@terasic.com Taiwan & China: +886-3-550-8800 Korea : +82-2-512-7661 Japan: +81-428-77-7000...
Architecture Architecture This chapter describes the architecture of the THDB-SUM board including its PCB and block diagram. Layout and Componets The picture of the TDRB-SUM board is shown in Figure 2.1 and Figure 2.2. It depicts the layout of the board and indicates the location of the connectors and key components.
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Architecture HSMC Connector (J1) SD Card Socket (J7) Figure 2.2. The THDB-SUM Back side – HSMC connector view The following components are provided on the THDB-SUM board : • HSMC expansion connector (J1) • Santa Cruz Headers(J3,J4,J5) • Mictor connector (J2) •...
HSMC connector. Also, the JTAG interface of the HSMC connector is shown in the Figure 3.4. If users don’t need to use the JTAG interface on the THDB-SUM board, please short the header JP0 to loopback the TDI and TDO signals on the HSMC connector.
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Board Components HSMC_SCL HSMC_SDA HSMC_TMS HSMC_TCK HSMC_TDI HSMC_TDO SD Wpn SD DAT1 Figure 3.1. The pin-outs of Bank 1 on the HSMC connector...
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Board Components MICTOR_D14 MICTOR_D0 MICTOR_D15 MICTOR_D1 V C C 33 MICTOR_D16 MICTOR_D4 MICTOR_D17 MICTOR_D5 V C C 33 MICTOR_D18 MICTOR_D2 MICTOR_D19 MICTOR_D3 V C C 33 MICTOR_D20 MICTOR_D6 MICTOR_D21 MICTOR_D13 V C C 33 MICTOR_D22 MICTOR_D12 MICTOR_D23 MICTOR_D11 V C C 33 MICTOR_D24 MICTOR_D10 HSPROTO_IO23...
This section describes the Santa Cruz connector on the THDB-SUM board The THDB-SUM board comes with Santa Cruz connectors (J3, J4 and J5) to connect to a daughter board with Santa Cruz interface. On the THDB-SUM, the pin of SC connector not directly connects with HSMC connector.
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Board Components Open : 3.3V Open : 2.5V Close : 5V Close : 3.3V HSMC Connector (J1) VCCA VCCB PROTO_RESET HSPROTO_RESET PROTO_CARDSEL HSPROTO_CARDSEL Level PROTO_IO[40..0] HSPROTO_IO[40..0] Shifters Santa Cruz (U3~U8) Connectors (J3~J5) Figure 3.6 The diagram of the logic level transform block Table 3.2 The configuration of the logic level on the HSPROTO_IO JP3 setting Logic level of the HSPROTO_IO BUS...
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Board Components Figure 3.7 Santa Cruz connector pin-outs Table 3.4 The pin assignments of the Santa Cruz connector J3 HSMC Pin SC Pin Number SC Signal Name HSMC Signal Name HSMC Pin Name Number PROTO_IO40 HSPROTO_IO40 HSMC_TX_N0 PROTO_IO29 HSPROTO_IO29 HSMC_TX_P1 PROTO_IO30 HSPROTO_IO30 HSMC_TX_N1...
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Board Components Table 3.6 The pin assignments of the Santa Cruz connector J5 HSMC Pin SC Pin Number SC Signal Name HSMC Signal Name HSMC Pin Name Number PROTO_RESET HSPROTO_RESET HSMC_RX_P0 PROTO_IO0 HSPROTO_IO0 HSMC_RX_N0 PROTO_IO1 HSPROTO_IO1 HSMC_RX_P1 PROTO_IO2 HSPROTO_IO2 HSMC_RX_N1 PROTO_IO3 HSPROTO_IO3 HSMC_RX_P2...
This section describes the USB On-The-Go transceiver on the THDB-SUM board The THDB-SUM is equipped with a NXP ISP1504C USB On-The-Go transceiver (U11) and Mini USB AB type receptacle connector (J8) to provide USB interface to the HSMC interface host board. The ISP1504 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Universal Serial Bus Specification Rev.
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Board Components HSMC Connector (J1) Jack-Mini- USB-AB (J8) VBUS USB _D[7..0] DATA[7..0] USB_CS_n USB_RESET_n RESET Close = Host Open = Peripheral HSPROTO_IO Switch ISP1504C (U1,U2) (U11) USB_DIR USB_STP USB_NXT USB_CLKOUT CLOCK XTAL1 XTAL1 XTAL2 XTAL2 26MHZ Open Figure 3.8 The block diagram of the USB OTG transceiver and HSMC connector Table 3.8 The pin assignments of the USB OTG Transceiver U11 USB Pin HSMC Pin...
Board Components Mictor Connector This section describes how to use the Mictor connector on the THDB-SUM board The Mictor connector (J2) can be used for logic analysis on the HSMC-interfaced host board by connecting an external scope or a logic analyzer to it.
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Cyclone III start board using Mictor interface is shown below: 1. Connecting the THDB-SUM board to the Cyclone III Start Board. 2. Removing the jumpers of JP1 and JP2 of the Cyclone III Start Board to connect the JTAG interface between Cyclone III FPGA and the THDB-SUM board.
This section describes the SD Card Interface on the THDB-SUM board The THDB-SUM has a SD card socket and can be accessed as optional external memory in both SPI and 1-bit SD mode. Table X shows the pinout of the SD card socket with HSMC connector.
SD_WP_N HSMC_CLKIN0 SMA Connector This section describes the SMA connector on the THDB-SUM board The THDB-SUM board provides a SMA connector (J6) for external clock input. The pin assignments of the SMA connector are shown in Table 3.11. Table 3.11 The pin assignments of the SMA Connector J6...
This section describes the I2C Serial EEPROM on the THDB-SUM board The THDB-SUM board provides an EEPROM (U10) which can be configured by the I2C interface. The size of the EEPROM is 128 bit that can store the board information or user’s data. The detailed pin description...
Board Components Power Supply This section describes the power supply on the THDB-SUM board The power distribution on the THDB-SUM board is shown in Figure 3.14. VCC50 REG3 Santa Cruz Connector (J3~J5) REG2 HSMC Connector (J1) VHSMC VCCA VCCB VCC33...
Users MUST short Pin 1 and Pin 2 of the JP3 on the THDB-SUM to force the voltage level to 2.5V to match the 2.5V IO pins of the Cyclone III board. Configure JP4 of the THDB-SUM according to the logic level of the Santa Cruz daughter board (refer to Table 3.2)
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Demonstration close loop via R3) and HSMC_CLKIN_p2/n2 (form a close loop via R4). Therefore, using any one of the signal in a LVDS pair under single-ended mode will prevent users from using the other signal in the same pair.
DEC 2, 2009 Corrections for tables 3.1 & 3.7. Modify Ch.4 section Always Visit THDB-SUM Webpage for New Main board We will be continuing providing interesting examples and labs on our THDB-SUM webpage. Please visit www.altera.com or SUM.terasic.com for more information.
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