Harman Kardon AVR 171/230 Service Manual page 94

Harman Kardon
2.17 SSM Interface
Name
SSMD[7:0]
SSMCLK
SSMCMD
SSMCP
SSMWP
2.18 External PLL Pins
Name
VCO[1:0]
PDOUT[1:0]
2.19 Global Pins
Name
NRESET
XTALI
XTALO
RREF
TEST1
HIGHZ
n.c.
dat_DM860A_1_1_datasheet.doc
Pin(s) Type
D12, C12, B12,
A12, D11, C11,
B11, A11
C10
A13
D10
D9
Pins Type Description
J2, K2 I External oscillator inputs, typically coming from an external VCO.
Together with the external loop-filter and the internal clock dividers,
each PDOUT/VCO pair can form a complete PLL.
J1, K1 O Phase discriminator outputs. These signals are charge-pump type
outputs. Each of them can be used to feed the loop-filter of a PLL
structure.
Pin(s) Type Description
D13 I Reset (active low). When asserted, the chip is placed in the
reset state and the peripheral pins are configured as inputs.
After deassertion of NRESET, the chip is clocked by XTALI and
starts booting from the port configured by the FCLE, FALE pins.
The NRESET signal must be asserted after power-up.
K3 I Oscillator circuit input. Internal system clock will be derived
from XTALI (internal clock multiplier)
J3 O Oscillator circuit output
C7 I Reference current. Connect a 3.0 kOhm ±1% resistor to GND.
B10 I Reserved. Connect to VDD for normal operation.
A10 I Reserved. Connect to VDD for normal operation.
E4, F4, G4, – Pins must be left unconnected (18x)
H4, J4, V1,
A4, A5, B4,
B5, C8, C9
CONFIDENTIAL
Description
I/O Data lines
O Clock output
O Command output
I Card power input (high = off)
I Write protect input (low = protect)
Data Sheet: DM Series
DM860A Networked Media Processor
th
Version 1.1 – July 11 2011 - Page 22 of 70
AVR 171 Service Manual
Page 94 of 174