Harman Kardon AVR 171/230 Service Manual page 90

Harman Kardon
2.10 External Memory Interface
Name Pin(s)
D[15:0] T18, R18, P17,
P18, N15, N16,
N17, N18, M15,
M16, M17, M18,
L15, L16, L17, L18
A[12:0] E18, E17, E16,
E15, D18, D17,
D16, C18, C17,
C16, B18, A18,
A17
A13_RAS F15
A14_CAS F16
A15_BA0 F17
A16_BA1 F18
A17_DQM0 G15
A18_DQM1 G16
A[23:19] H17, H16, H15,
G18, G17
NCS[3:0] H18, J17, J16, J15
NOE K17
NWE K16
NWAIT K18
MEMCLK K15
MEMCKE J18
dat_DM860A_1_1_datasheet.doc
Type Description
I/O Data bus for external memory and peripheral access
O Address bus for external memory and peripheral access
O SRAM: address output
SDRAM: row access strobe
O SRAM: address output
SDRAM: column access strobe
O SRAM: address output
SDRAM: bank select
O SRAM: address output
SDRAM: bank select
O SRAM: address output
SDRAM: data mask
SRAM: address output
O
SDRAM: data mask
O Address bus for external memory and peripheral access
O Chip select signals. The active memory range for NCS[n]
(active low) can be configured.

NCS[0] supports SRAM, can be used for booting

NCS[1] supports SDRAM or SRAM

NCS[2] supports SRAM

NCS[3] supports SRAM
O Output enable, asserted (low) for read operations
O Write enable, asserted (low) for write operations
I External wait line. If NWAIT is asserted, memory access will
be stalled. Can be configured as either low-active (default) or
high-active.
O SDRAM system clock
O SDRAM clock enable
CONFIDENTIAL
Data Sheet: DM Series
DM860A Networked Media Processor
th
Version 1.1 – July 11 2011 - Page 18 of 70
AVR 171 Service Manual
Page 90 of 174