This allows recording and triggering on a higher level like protocol level. Input/Output Lines The PowerIntegrator offers 12 connectors with 16-data + 1-data/clock channels. For using a 16+1channel probe (standard probe) only one of this connectors is used. For using a 32+2channel probe (MICTOR/SAMTEC probe) two of this connectors are used.
Probe signals are sampled on the rising or falling edge of a target clock signal (CLKA, CLKB, CLKJ, CLKK). The selected target clock feeds an PowerIntegrator internal PLL which gives the option to vary the sampling time in a range of -3 … +6 ns in steps of 250 ps. To make the PLL circuit work the target clock has to be active always and it has to run on a fixed frequency in the range of 6 …...
Trigger Counter = 1 Trigger Delay After the trigger condition has been latched, a trigger delay is used before stopping the PowerIntegrator. The delay can be defined with an absolute time (1 ms to 10 s) or in percentage of the trace storage.
Trigger Outputs When reaching the trigger state (trigger latch is true), other systems like oscilloscopes can be triggered by the PowerIntegrator. The trigger output signals are true as long as the PowerIntegrator is running and the trigger latch has been set.
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