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QEI ePAQ-9410 User Manual

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EPAQ-9410
Hardware Programming Reference 0.16
________________________________________________________________________
ePAQ-9410
Hardware Programming
Reference 0.16
User's Manual
October 2019

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Summary of Contents for QEI ePAQ-9410

  • Page 1 EPAQ-9410 Hardware Programming Reference 0.16 ________________________________________________________________________ ePAQ-9410 Hardware Programming Reference 0.16 User’s Manual October 2019...
  • Page 2 The information in this document has been carefully checked and is believed to be accurate. However, no responsibility is assumed or implied for inaccuracies. Further more, QEI reserves the right to make changes to any products herein described to improve reliability, function or design. QEI does not assume liability arising out of the application or use of any product or circuit described herein;...
  • Page 3 EPAQ-9410 Hardware Programming Reference 0.16 ________________________________________________________________________ Revisions Revision Description Date Release to Production October 2019 ________________________________________________________________________ Copyright © 2019 QEI Page 2...

  • Page 4: Table Of Contents

    Bit-Bang CH [0,1] Register ..............23 3.10.12 Bit-Bang [0,1] RTS# Control Register ............ 23 3.10.13 DUART [A,B] Register................24 3.10.14 SR CPLD Revision 0 Register ..............25 3.10.15 SR CPLD Revision 1 Register ..............25 ________________________________________________________________________ Copyright © 2019 QEI Page 3...
  • Page 5 Install additional files ..................32 Bring-up procedure ....................32 Equipment list ....................32 Visual inspection ....................33 ePAQ-9410 Motherboard Initial Power Up ............34 ePAQ-9410 ProcFull Initial Power Up .............. 35 Initial programming.................... 35 CPLD programming ................... 35 Modem ports ...................... 36 5.7.1...
  • Page 6 EPAQ-9410 Hardware Programming Reference 0.16 ________________________________________________________________________ 5.21 RTC ........................ 47 5.22 Supercap ......................47 ________________________________________________________________________ Copyright © 2019 QEI Page 5...
  • Page 7 AD and LM CPLD sections 0.10 3/7/12 updated SR CPLD section added “boot modes”, “CAPTURE and COMPARE”, 0.11 3/20/12 GPIO_BIT_BANG_OUT_CH[0,1] 0.12 10/18/12 updated NAND flash section 0.13 10/19/12 bring-up procedure WIP 0.16 10/3/19 CPLD/USB/Ethernet enables ________________________________________________________________________ Copyright © 2019 QEI Page 6...

  • Page 8: Introduction

    EPAQ-9410 Hardware Programming Reference 0.16 ________________________________________________________________________ 1 Introduction This document describes hardware functionality of ePAQ-9410 ProcFull board Rev B and ePAQ-9410 Mother Board Rev B. 2 References 1. ePAQ-9410/9420 Multifunction Gateway Functional Specification, 05-055104- 001 ePAQ-94XX MultiFunction Gateway Spec Rev H13.pdf, REV.H13, 6/27/2011 2.
  • Page 9 Drives Diag LED 1, high active GP_SPARE_0 ProcFull Not used GP_SPARE_1 MotherBoard Provisional for JTAG-TDO GP_SPARE_2 MotherBoard Provisional for JTAG-TDI GP_SPARE_3 MotherBoard Provisional for JTAG-TCLK GP_SPARE_4 MotherBoard Provisional for JTAG-TMS GP_SPARE_5 ProcFull Not used ________________________________________________________________________ Copyright © 2019 QEI Page 8...

  • Page 10: Boot Modes

    CSI_HSYNC BT_USB_SRC[1] 100/10K not used, should be recycled as GPIO CSI_D15 BT_USB_SRC[0] 100/10K 3.2 Boot Modes The ePAQ-9410 system supports four boot modes as follows: Boot mode BOOT_MODE[1:0] BT_MEM_CTRL[1:0] BT_MEM_TYPE[1:0] NOR FLASH Serial Download SD Card Startup/JTAG The NOR FLASH boot mode is the normal, field mode of operation. The Serial Download boot mode is for initial programming of the NOR FLASH.

  • Page 11: Capture And Compare

    ________________________________________________________________________ These boot modes are among many possible boot modes and configurations supported by IMX357 CPU. The ePAQ-9410 design only supports the boot modes listed above. The supported boot modes are selected by the configuration switch U1. NOR FLASH Boot Mode...

  • Page 12: Sdram

    The hardware design supports a stuffing option when a more dense flash part could be placed into U6, for example MT29F16G08AJADAWP, at the expense of second NOR flash chip in U13. This configuration was not thoroughly reviewed or tested. ________________________________________________________________________ Copyright © 2019 QEI Page 11...

  • Page 13: Spi Flash

    DISABLE_2_H write-only 0x00 0x15 DISABLE_3_H DISABLE_3_H write-only 0x00 0x16 MSTR_RS422_TXEN MSTR_RS422_TXEN write-only 0x00 0x17 BIT_BANG_RS232_ENA BIT_BANG_RS232_ENA write-only 0x00 0x18 AD CPLD Revision AD_REVISION read-only 0x07 0x19 ETHER_CONFIG_MODE ETHER_CONFIG_MODE write-only 0x1A ETHERNET_CPLD_RESET# ETHERNET_CPLD_RESET# write-only ________________________________________________________________________ Copyright © 2019 QEI Page 12...

  • Page 14: Heartbeat Register

    Access type: write-only LED_OFF Heartbeat LED is the top row left column LED in the 2 rows by 3 columns LED array located on the ePAQ-9410 front panel. It is right above the Power LED which is bottom- left. LED_OFF: LED control...

  • Page 15: L2 Led Register

    Register Name: LED_3 Address: 0xB401_0012 Access type: write-only L3 LED is the bottom row middle column LED in the 2 rows by 3 columns LED array located on the ePAQ-9410 front panel. LED_OFF LED_OFF: LED control 0 = LED on 1 = LED off 3.7.5...

  • Page 16: Sw10 High Ip Address Register

    Refers to SW1, four Front Panel Option DIP switches. Left to right: SW1-1, SW1-2, SW1-3, SW1-4. “ON” is down. FP_DIP_SW4 FP_DIP_SW3 FP_DIP_SW2 FP_DIP_SW1 FP_DIP_SW1: DIP switch SW1-1 0 = ON (down) 1 = OFF (up) ________________________________________________________________________ Copyright © 2019 QEI Page 15...

  • Page 17: Ad Cpld Revision Register

    0xB400_0038 0xB400_003F 8 Bytes QUAD UART 2, Channel D Under Linux, the individual channels of QUAD UART are mapped to devices as follows: Channel Linux name QUAD UART 1, Channel A /dev/sttyS0 GPIO_1_9 ________________________________________________________________________ Copyright © 2019 QEI Page 16...

  • Page 18: Duart

    0x00 0x14 reserved 0x15 reserved 0x16 reserved 0x17 reserved 0x18 SR CPLD Revision 0 SR_REVISION_0 read-only 0x19 SR CPLD Revision 1 SR_REVISION_1 read-only 0x1A reserved 0x1B reserved 0x1C reserved 0x1D reserved 0x1E reserved ________________________________________________________________________ Copyright © 2019 QEI Page 17...

  • Page 19: Irig-B Bus Register

    The IRIG_FIBER_TX_SEL bits controls the configuration of the IRIG_FIBER_TX_NI signal internal to the SR CPLD. The IRIG_FIBER_TX_NI is the Non-Inverted counterpart of the IRIG_FIBER_TX signal. Similarly, the IRIG_FIBER_RX_NI is the non-inverted counterpart of the IRIG_FIBER_RX signals. ________________________________________________________________________ Copyright © 2019 QEI Page 18...

  • Page 20: Irig-B_Rs485_Txd Register

    {IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} = {1'b1, 1'b1}; reserved/unused TEST0: {IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} = {1'b0, 1'b0}; TEST1: {IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} = {1'b1, 1'b0}; IrigOut: {IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} = {IRIG_SIGNAL_BUS, 1'b0}; ~IrigOut: {IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} = {~IRIG_SIGNAL_BUS, 1'b0}; CH8: {IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} = ________________________________________________________________________ Copyright © 2019 QEI Page 19...

  • Page 21: Irig-B_Output_To_Micro Register

    COAX IRIG port J9 for IRIG-B input vs. IRIG-B output mode of operation. IRIG_B_MOD_OUT_EN_H 0 – IRIG-B input mode 1 – IRIG-B output mode 3.10.6 CH8_RXD Register Register Name: CH8_RXD_SEL Address: 0xB402_0006 Access type: write-only ________________________________________________________________________ Copyright © 2019 QEI Page 20...

  • Page 22: Com_Exp_Irig-B Register

    0, COMM_EXP_IRIG-B signal is driven low 1, COMM_EXP_IRIG-B signal is driven high COMM_EXP_IRIG-B = IRIG_SIGNAL_BUS 0x3-0xF reserved for future use, same as 0x0 3.10.8 Telco [1,2] Mode Register Register Name: CH[14,15]_SEL Address: [14]: 0xB402_0008, [15]: 0xB402_000A ________________________________________________________________________ Copyright © 2019 QEI Page 21...

  • Page 23: Telco [1,2] Control Register

    Address: [10]: 0xB402_000C, [11]: 0xB402_000D Access type: write-only RS232_MODE The CH[10,11]_SEL registers control the configuration of the RS232 ports 1 and 2. The RS232 ports 1 and 2 are also known as CH10 and CH11. ________________________________________________________________________ Copyright © 2019 QEI Page 22...

  • Page 24: Bit-Bang Ch [0,1] Register

    //driven by RS232 port 1 BB[0,1]_RXD = CH[10,11]_RXD; //TELCO port routing BB[0,1]_RXD = CH[14,15]_RXD; 0x3-0xF //disabled, 0 BB[0,1]_RXD = 1'b0; 3.10.12 Bit-Bang [0,1] RTS# Control Register Register Name: BB[0,1]_RTS_CTRL Address: [0]: 0xB402_0010, [1]: 0xB402_0011 Access type: write-only ________________________________________________________________________ Copyright © 2019 QEI Page 23...

  • Page 25: Duart [A,B] Register

    {DUART_CH[A,B]_TXD, DUART_CH[A,B]_RTS_L, CH[10,11]_TXCLK_OUT}; //Test: debug duart {DUART_CH[A,B]_RXD, DUART_CH[A,B]_CTS_L, CH[10,11]_RXCLK_IN} = {DUART_CH[A,B]_TXD, 1'b0, CH[10,11]_TXCLK_OUT}; //Test: debug duart {DUART_CH[A,B]_RXD, DUART_CH[A,B]_CTS_L, CH[10,11]_RXCLK_IN} = {DUART_CH[A,B]_TXD, 1'b1, CH[10,11]_TXCLK_OUT}; 0x6-0xF //reserved: disable everything as much as possible {DUART_CH[A,B]_RXD, DUART_CH[A,B]_CTS_L, CH[10,11]_RXCLK_IN} = ________________________________________________________________________ Copyright © 2019 QEI Page 24...

  • Page 26: Sr Cpld Revision 0 Register

    LM_CPLD_REVISION read-only 0x05 0x20 CH_RXD Status CH_RXD_STS read-only 0x21 CH_RXD2 Status CH_RXD2_STS read-only 0x22 CH_TXD Status CH_TXD_STS read-only 0x23 CH_TXD2 Status CH_TXD2_STS read-only 0x24 CH_RTS Status CH_RTS_STS read-only 0x30 CH_RXD Monitor CH_RXD_MON read-only ________________________________________________________________________ Copyright © 2019 QEI Page 25...
  • Page 27 10b – RS485 Driver Enable is controlled by CHn_RTS# QUAD UART output; RS485 driver is enabled when CHn_RTS# is active/asserted (logic 0), RS485 driver is disabled when CHn_RTS# is inactive/deasserted (logic 1) 11b – Reserved, RS485 Driver Disabled ________________________________________________________________________ Copyright © 2019 QEI Page 26...

  • Page 28: Rxd Status Register

    Reading the CH_TXD register returns the momentary state of the CPLD pins as described in the table below CH7_TXD UART3_TXD UART2_TXD CH4_TXD CH3_TXD CH2_TXD CH1_TXD 3.11.4 CH_TXD2 Status Register Register Name: CH_TXD2_STS Addresses: 0xB408_0023 ________________________________________________________________________ Copyright © 2019 QEI Page 27...

  • Page 29: Rts Status Register

    CH3_RTS# CH2_RTS# CH1_RTS# 3.12 System Reset & Watchdog Timer The ePAQ-9410 utilizes a watchdog timer / power-on reset circuit. The functions of this circuit are to provide: a) Initial power-on reset of all circuitry b) Protection against runaway processor c) Full power-on restart in case of watchdog timeout This functionality is supported by hardware circuitry on both the Proc Full and Mother Boards as well as software interaction.

  • Page 30: Bypass Mode

    Note that U124 & U125 are powered from +5V, not affected by this power-on restart. Should the CPU be unable to hold off the watchdog on the ProcFull board, the above process will be repeated approx every 1.6S (1.12S min, 2.4S max). This will result in ________________________________________________________________________ Copyright © 2019 QEI Page 29...

  • Page 31: I2C Busses And Devices

    4.1 Initial Programming via Serial Port Freescale provides a programming utility called “Advanced Toolkit”. Advanced Toolkit V1.17 from Freescale was customized to work with ePAQ-9410 ProcFull board. The customized Advanced Toolkit Utility is used to program U-Boot and U-Boot environment into the NOR Flash via Serial Boot mode. Once the U-Boot is programmed, the board is booted normally from NOR Flash into U-Boot.

  • Page 32: Nor Flash Programming Via Tftp Server

    Run the TFTPD32 server application. Set the Current Directory to point to the folder containing Linux kernel and Linux Root Filesystem programming files. This folder will become the root of TFTP server. ________________________________________________________________________ Copyright © 2019 QEI Page 31...

  • Page 33: Install Additional Files

    Things you will need to complete testing described in this section Equipment: • ATMEL SAM-ICE • Startech Fiber Ethernet Media Converter (MCM110ST2) • Serial Debug Port RS232 driver board (schematic provided separately) • SD Card ________________________________________________________________________ Copyright © 2019 QEI Page 32...

  • Page 34: Visual Inspection

    • Check for unsoldered pins and components that are tombstoned. • Check if components are in their correct orientation. • Check for missing components and that DNI components are not installed ( Use corresponding DNI list for board being inspected). ________________________________________________________________________ Copyright © 2019 QEI Page 33...

  • Page 35: Epaq-9410 Motherboard Initial Power Up

    7:on 8:on Configure the board for the serial boot mode. 5.3 ePAQ-9410 Motherboard Initial Power Up Check if any of the power supplies are shorted to ground by measuring the resistance with a DVM across the following components: For "+24V" measure across C146: PASS/FAIL For "+5V"...

  • Page 36: Epaq-9410 Procfull Initial Power Up

    ________________________________________________________________________ For "+VCC_ISO_5V_CH3" measure across C278: For "+VCC_ISO_5V_CH4" measure across C279: 5.4 ePAQ-9410 ProcFull Initial Power Up Check if any of the power supplies are shorted to ground by measuring the resistance with a DVM across the following components: For "+3_3V" measure across C59: PASS/FAIL For "+3_3V_LATE"...

  • Page 37: Modem Ports

    CH 2 TX/CH 1 RX configuration 1. power cycle the system 2. Configure routing, modems, etc #modem CH1 (CH14) TX is controlled by DUART CHA TX ./mmdump -a 0xB4020000 -o 0x08 -b 0x05 ________________________________________________________________________ Copyright © 2019 QEI Page 36...

  • Page 38: Rs232/Rs485 Ports

    W 0xB4080001: 0x01 root@QEIprocFull:/oe ./mmdump -a 0xb4080000 -o 0x02 -b 0x01 W 0xB4080002: 0x01 root@QEIprocFull:/oe ./mmdump -a 0xb4080000 -o 0x03 -b 0x01 W 0xB4080003: 0x01 root@QEIprocFull:/oe ./mmdump -a 0xb4080000 -o 0x04 -b 0x01 ________________________________________________________________________ Copyright © 2019 QEI Page 37...

  • Page 39: Rs-485 Test

    TX port: yellow only all RX ports: green only PORT 2 TX, PORT 1 RX root@QEIprocFull:/oe ./mmdump -a 0xb4080000 -o 0x01 -b 0x00 W 0xB4080001: 0x00 root@QEIprocFull:/oe ./mmdump -a 0xb4080000 -o 0x02 -b 0x08 ________________________________________________________________________ Copyright © 2019 QEI Page 38...

  • Page 40: Options S1 Dip Switches

    See 3.7.1 Heartbeat Register, 3.7.2 L1 LED Register, 3.7.3 L2 LED Register, 3.7.4 L3 LED Register, 3.7.5 L4 LED Register all LED's are red verify that PWR LED is always on (bottom-left) LED positions: HBT L1 L2 PWR L3 L4 HBT is at 0xB401_000F ________________________________________________________________________ Copyright © 2019 QEI Page 39...

  • Page 41: Irig/Serial

    RX/bottom LED is on ./mmdump -a 0xb4020000 -o 0x00 -b 0x00 observe both LED's are off # CH8 TX/RX ./mmdump -a 0xb4020000 -o 0x01 -b 0x03 ./mmdump -a 0xb4020000 -o 0x06 -b 0x01 ________________________________________________________________________ Copyright © 2019 QEI Page 40...

  • Page 42: Sd Card

    > /dev/ttyS5 observe fox.txt message appear on the terminal LED's: at IRIG PORT 8 (J7B) yellow/left LED is blinking, green is not blinking at RS-232/RS-485 ports 1-4, green LED's are blinking, yellow LED's are ________________________________________________________________________ Copyright © 2019 QEI Page 41...

  • Page 43: Irig Rx Test

    5.16.1 PORT 9 (J7A) external loopback test Install "RS422 LOOPBACK" cable into PORT 9 (J7A) ./setup_all_ports.sh ./mmdump -a 0xB4010000 -o 0x16 -b 0x1 ./mmdump -a 0xB4080000 -o 0x05 -b 0x0 cat /dev/ttymxc1 & cat fox.txt > /dev/ttymxc1 ________________________________________________________________________ Copyright © 2019 QEI Page 42...

  • Page 44: Port 10 (J7D) External Loopback Test

    ./mmdump -a 0xB4080000 -o 0x06 -b 0x1 observe the contents of fox.txt NOT appear on the terminal LED's: only yellow/left is blinking, green/right LED is NOT blinking NOTE: /dev/ttyS4 asserts RTS# when cat command is executed ________________________________________________________________________ Copyright © 2019 QEI Page 43...

  • Page 45: Port 11 J7C External Loopback Test

    ./mmdump -a 0xB4080000 -o 0x07 -b 0x0 observe the contents of fox.txt NOT appear on the terminal LED's: only yellow/left is blinking, green/right LED is NOT blinking 5.17 RS-232 PORT 12 J8B PORT 13 J8A ________________________________________________________________________ Copyright © 2019 QEI Page 44...
  • Page 46 /dev/ttySC1.CTS: 1 J8-B RTS (output) /J8-A CTS (input) ./rts /dev/ttySC1 0 & ./cts /dev/ttySC0 verify output: dev = /dev/ttySC0 /dev/ttySC0.CTS: 0 ./rts /dev/ttySC1 1 & ./cts /dev/ttySC0 verify output: dev = /dev/ttySC0 /dev/ttySC0.CTS: 1 ________________________________________________________________________ Copyright © 2019 QEI Page 45...

  • Page 47: Irig Coax

    Yellow (TX) (Right) and one Green (L/A) (Left) LED. File a bug about inconsistency of LED’s in 05-055104-001 ePAQ-94XX MultiFunction Gateway Spec Rev H16.pdf Not tested: LED patterns under various conditions. QEI says they have tested this and all is well. ________________________________________________________________________ Copyright ©...
  • Page 48 Leakage current may become an issue Bug 237 - bring-up RTC 5.22 Supercap Enable supercap charging via RTC ./rtc -d /dev/spidev0.3 -w 0x8F 0xA5 ./setrtc.sh – initialize RTC with known values ./rtcdump.sh – dump RTC registers ________________________________________________________________________ Copyright © 2019 QEI Page 47...

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