Related Manuals for EDT PCIe8g3 S5 Series
Summary of Contents for EDT PCIe8g3 S5 Series
- Page 1 User’s Guide PCIe8g3 S5 Family PCIe Gen3 x8 boards with Stratix V FPGA and 10G / 40G ports Date: 2017 January 04 Rev.: 0001...
- Page 2 EDT | Engineering Design Team, Inc. 3423 NE John Olsen Ave Hillsboro, OR 97124 U.S.A. Tel: +1-503-690-1234 | Toll free (in U.S.A.): 800-435-4320 Fax: +1-503-690-1243 www.edt.com and Engineering Design Team are trademarks of Engineering Design Team, Inc. All other trademarks, service marks, †...
- Page 3 Documentation is assumed by Buyer. The exclusion of implied warranties is not permitted by some jurisdictions. The above exclusion may not apply to Buyer. Disclaimer. Seller’s Products and Documentation, including this document, are subject to change without notice. Documentation does not represent a commitment from Seller. EDT, Inc.
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Page 4: Table Of Contents
Contents..................................4 Overview ................................... 7 Related Resources............................8 Care and Cautions ............................8 Installation and the EDT Installation Package ......................9 The PCD Device Driver..........................9 Firmware: FPGA Configuration (.bit) Files ....................9 Applications and Utilities ..........................10 Building or Rebuilding an Application......................11 Configuring the S5 .............................. - Page 5 0xA2 Port Status..........................41 0xA3 QSFP Status 2 [Reserved] ......................41 0xA7 Port Information ......................... 42 Registers, Port: Port 4 (QSFP/+) ..........................43 0x840010–0x840098 BAR1 Memory-Mapped ................... 43 0x840010 Synchronization Control...................... 43 0x840014 Frame Count Control [Reserved] ..................43 EDT, Inc.
- Page 6 0x840080 PRBS Mode ........................45 0x840084 PRBS Control 0 ......................... 45 0x840088 PRBS Control 1 ........................46 0x84008C PRBS Control 2 [Reserved] ....................46 0x840090 PRBS Control 3 [Reserved] ....................46 0x840094 PRBS Control 4 [Reserved] ....................47 Revision Log ................................48 EDT, Inc.
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Page 7: Overview
QSFP+ 850 nm 40GbE sel_port * SONET (OC3/12/48) and SDH (STM1/4/16) signal names are used interchangeably. For signal standards, see Related Resources on page For port locations and other board features, see Hardware on page EDT, Inc. 2017 January 04... -
Page 8: Related Resources
Care and Cautions Although EDT products are built to specifications which allow them to withstand a variety of extreme conditions, they are still high-performance components which require proper care for best results. To protect them and your equipment, follow all recommended instructions for care and cautions, including those in the EDT-provided static discharge kit. -
Page 9: Installation And The Edt Installation Package
We recommend powering off the board before replacing any transceiver, despite manufacturers’ claims that transceivers are hot-swappable. Now you’re ready to review the resources included in the EDT installation package. In addition to the files listed below, custom FPGA configuration files can be requested. -
Page 10: Applications And Utilities
Applications and Utilities In addition to the above resources, the EDT installation package includes application and utility files that you can use to initialize and configure the board, access the registers, and perform basic testing. In many cases, C or C++ source is provided so that you can use the files as starting points to write your own applications. -
Page 11: Building Or Rebuilding An Application
Building or Rebuilding an Application In your EDT installation package, executable and PCD source files are in the top-level directory. Therefore, if you need to build or rebuild an application, run make in that directory. Windows users must install a C compiler; we recommend the Microsoft Visual C compiler for Windows. Linux users can use the gcc compiler typically included with the Linux installation. -
Page 12: Fpga
At power-on, the firmware (FPGA configuration or .bit file) is installed automatically via nonvolatile flash memory. Typically you do not need to reconfigure or update the firmware unless... • you are asked to do so by EDT during a support call or email exchange; • you install a new driver; or •... -
Page 13: Initialization And Setup
(0x800000, 810000, 820000, 830000 Receive Framer Status and Control) or demux bitmap register (0x80003C, 81003C, 82003C, 83003C Demux Bitmask), nor will it enable the relevant channel for DMA in registers 0x00 Command 0x10–11 DMA Channel Enable. EDT, Inc. 2017 January 04... -
Page 14: Querying The Transceivers
For details, see the manufacturer’s website for the transceivers you are using (see Related Resources on page Time Code The S5 uses the same timecode interface as the EDT Time Distribution board. For details, see these registers... • Register 0x6D SPI Data •... -
Page 15: Hardware
Port 1 (SFP/+) (optional) Si570 FPGA Si570 for FPGA Si570 configuration Port 4 (QSFP+) status PCIe boot CPLD time to / from select Bank 1: 4 GB DDR3 Lemo code host Not to scale; generic representation only EDT, Inc. 2017 January 04... -
Page 16: Ports And Led Status Indicators
If a port is working properly in all three areas, its LED is steady green. If not, its LED will be blinking. Table 2 summarizes the LED behaviors. Table 2. LED behaviors LED behavior FPGA receive clock locked / ready to receive? Signal being received? Signal being framed? Dim blinking Bright blinking Bright steady EDT, Inc. 2017 January 04... - Page 17 The macro, which works for both indirect and BAR1 memory-mapped addresses, is defined as... STRATIX5_REGXL8(register_address, port_number) ...with the italicized variables being replaced by the appropriate register address and port number, as shown in the access information provided with each register below. EDT, Inc. 2017 January 04...
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Page 18: Registers, Ui
0x03 Interrupt Status above, allowing the driver to disable and re-enable them in one operation without altering their states. A value of 1 enables the interrupts; a value of 0 disables them. 3–0 – [no name] Reserved. EDT, Inc. 2017 January 04... -
Page 19: 0X0D Exended Configuration
6, 7, 4, 5, 2, 3, 0, 1 4, 5, 6, 7, 0, 1 2, 3 0, 1, 2, 3, 4, 5, 6, 7 5, 4, 7, 6, 1, 0, 3, 2 3, 2 1, 0, 7, 6, 5, 4 EDT, Inc. 2017 January 04... -
Page 20: 0X10-11 Dma Channel Enable
A value of 1 in a bit indicates that the corresponding DMA channel’s internal FIFO has overflowed since the channel was last enabled. Data received while the FIFO is in overflow is discarded. To reset, clear and reenable the appropriate channel (see 0x00 Command 0x10–11 DMA Channel Enable). EDT, Inc. 2017 January 04... -
Page 21: 0X60-62 Extended Indirect Register Address
16 = Port 0 SFP active copper PHY. 17 = Port 1 SFP active copper PHY. 18 = Port 2 SFP active copper PHY. 19 = Port 3 SFP active copper PHY. 20 = U2M reference clock (Si5375). EDT, Inc. 2017 January 04... -
Page 22: 0X65 Serial Master Interface Read [7-0]
Access Name Description 15–8 [no name] This register [bits 15–8] works with 0x66 Serial Master Interface Register Address [7–0]. Write the register address on the serial slave that you wish to read. Read the register address. EDT, Inc. 2017 January 04... -
Page 23: 0X6A Serial Master Interface Write [15-8]
Set to send the synchronization trigger. STRATIX5_SYNC_ 0x6D SPI Data Access / Notes: 8-bit read-write / SPI_DATA Access Name Description 7–0 [no name] If read, bits read from the input FIFO. If written, bits write to the output FIFO. EDT, Inc. 2017 January 04... -
Page 24: 0X6E Spi Status And Control
(number of DMA channels used, number of DMA channels required by PCI FPGA) mm/dd/yyyy is the date the FPGA configuration file was created. Replace italicized terms with actual values — for example, sv16_pe8s5_4p 0.0 04/24/2013 (10,10). EDT, Inc. 2017 January 04... -
Page 25: 0X7F Board Id [Reserved]
0x7F Board ID [Reserved] EDT, Inc. 2017 January 04... -
Page 26: Registers, Ui
27–24 R only [no name] Bank C debug information. 23–20 R only [no name] Bank B debug information. 19–16 Bank A debug information. R only [no name] R only [no name] Bank D 100% full. EDT, Inc. 2017 January 04... -
Page 27: 0X000018 W Prbs [Reserved]
[no name] Avalon address width, in bits. 19–10 R only [no name] Data word width in bytes per bank. 9–0 R only [no name] Burst size in number of transfers (four data words per transfer). EDT, Inc. 2017 January 04... -
Page 28: Registers, Port: Ports 0-3 (Sfps)
When set, indicates the transceiver CDR is locked to reference clock. R only [no name] When set, indicates the transceiver is ready to receive. R only [no name] When set, indicates the transceiver is ready to transmit. EDT, Inc. 2017 January 04... -
Page 29: 0X87, 8F, 97, 9F Port Information
0x8F (Port 1): STRATIX5_REGXL8(STRATIX5_PORT_INFO, 1) 0x97 (Port 2): STRATIX5_REGXL8(STRATIX5_PORT_INFO, 2) 0x9F (Port 3): STRATIX5_REGXL8(STRATIX5_PORT_INFO, 3) Access Name Description 7–4 R only [no name] Port type (SFP+ = 0; QSFP = 1). 3–0 R only [no name] Port number. EDT, Inc. 2017 January 04... -
Page 30: Registers, Port: Ports 0-3 (Sfps)
0x810004 (Port 1): STRATIX5_REGXL8(STRATIX5_RX_FILTER, 1) 0x820004 (Port 2): STRATIX5_REGXL8(STRATIX5_RX_FILTER, 2) 0x830004 (Port 3): STRATIX5_REGXL8(STRATIX5_RX_FILTER, 3) Access Name Description 31–8 – – Reserved. S5_RXFILT_IGNR_ Set to ignore all filters (overrides all other bits in this register). ALL_FILT EDT, Inc. 2017 January 04... -
Page 31: 0X800008, 810008, 820008, 830008 Transmit Framer Control [Reserved]
1 = when FIFO is 50% full 2 = when FIFO is 75% full 3 = when FIFO is 100% full The transmit logic waits to transmit until the selected threshold is reached. 11–10 – – Reserved. EDT, Inc. 2017 January 04... -
Page 32: 0X800014, 810014, 820014, 830014 Frame Statistics Count Control
0x80001C (Port 0): STRATIX5_REGXL8(STRATIX5_TX_TEST_PAT, 0) 0x81001C (Port 1): STRATIX5_REGXL8(STRATIX5_TX_TEST_PAT, 1) 0x82001C (Port 2): STRATIX5_REGXL8(STRATIX5_TX_TEST_PAT, 2) 0x83001C (Port 3): STRATIX5_REGXL8(STRATIX5_TX_TEST_PAT, 3) Access Name Description 31–16 – – Reserved. 15–0 [no name] Set the transmit test pattern. EDT, Inc. 2017 January 04... -
Page 33: 0X800020, 810020, 820020, 830020 Last B1 Error
The number of M1 bits found to be in error since the counter was last reset. The M1 byte is sent from the remote receiver of the signal, if that remote receiver has detected a B1 error. In that case, the B1 error mask is copied and sent back as the M1 byte. EDT, Inc. 2017 January 04... -
Page 34: 0X800030, 810088, 820088, 830088 Loss Of Frame Count
The number of times that the framing pattern was not correct, after data has been in frame. Because framing is not lost until the framing pattern has been incorrect four consecutive times, an incorrect framing pattern does not necessarily mean that framing was lost. EDT, Inc. 2017 January 04... -
Page 35: 0X80003C, 81003C, 82003C, 83003C Demux Bitmask
: wm132 80003C 80000FFF : wm132 80003C 8000107F : wm132 80003C 800011FF : wm132 80003C 800012FF : wm132 80003C 800013FF : wm132 80003C 800014FF : wm132 80003C 800015FF : wm132 80003C 800016FF : wm132 80003C 800017FF EDT, Inc. 2017 January 04... -
Page 36: 0X800040, 810040, 820040, 830040 Demux Bitmask Readback
Caution: This bit affects all ports. Set to reset the entire FPGA transceiver reconfiguration interface. Set when the transceiver reconfiguration interface is busy. R only [no name] [no name] Set to reset the port’s transceiver. 15–0 [no name] Reconfiguration register address. EDT, Inc. 2017 January 04... -
Page 37: 0X800068, 810068, 820068, 830068 Transceiver Reconfiguration Write Data
0x800078 (Port 0): STRATIX5_REGXL8(STRATIX5_FREQ_CNT_RX, 0) 0x810078 (Port 1): STRATIX5_REGXL8(STRATIX5_FREQ_CNT_RX, 1) 0x820078 (Port 2): STRATIX5_REGXL8(STRATIX5_FREQ_CNT_RX, 2) 0x830078 (Port 3): STRATIX5_REGXL8(STRATIX5_FREQ_CNT_RX, 3) Access Name Description 31–24 – – Reserved. 23–0 R only [no name] Receive frequency counter value. EDT, Inc. 2017 January 04... -
Page 38: 0X80007C, 81007C, 82007C, 83007C Transmit Frequency Counter
Lane 1 receive PRBS synchronized. 19–18 – – Reserved. [no name] Lane 1 receive PRBS check enable. [no name] Lane 1 receive PRBS generate enable. – – Reserved. R only [no name] Lane 0 transmit PRBS realtime error. EDT, Inc. 2017 January 04... -
Page 39: 0X800088, 810088, 820088, 830088 Prbs Control 1
Lane 2 transmit PRBS check enable. [no name] Lane 2 transmit PRBS generate enable. – – Reserved. R only [no name] Lane 2 receive PRBS realtime error. R only [no name] Lane 2 receive PRBS latched error. EDT, Inc. 2017 January 04... -
Page 40: 0X80008C, 81008C, 82008C, 83008C Prbs Control 2 [Reserved]
Lane 2 receive PRBS check enable. [no name] Lane 2 receive PRBS generate enable. 0x80008C, 81008C, 82008C, 83008C PRBS Control 2 [Reserved] 0x800090, 810090, 820090, 830090 PRBS Control 3 [Reserved] 0x800094, 810094, 820094, 830094 PRBS Control 4 [Reserved] EDT, Inc. 2017 January 04... -
Page 41: Registers, Port: Port 4 (Qsfp)
When set, indicates the transceiver CDR is locked to reference clock. R only [no name] When set, indicates the transceiver is ready to receive. R only [no name] When set, indicates the transceiver is ready to transmit. 0xA3 QSFP Status 2 [Reserved] EDT, Inc. 2017 January 04... -
Page 42: 0Xa7 Port Information
APPENDIX A: Registers for PCIe8g3 S5 Registers, Port: Port 4 (QSFP) 0xA7 Port Information Access / Notes: 8-bit read-only / STRATIX5_REGXL8(STRATIX5_PORT_INFO, 4) Access Name Description 7–4 R only [no name] Port type (QSFP=1). 3–0 R only [no name] Port number. EDT, Inc. 2017 January 04... -
Page 43: Registers, Port: Port 4 (Qsfp/+)
Lane 3 transceiver clock and data recovery (CDR) is locked to reference clock. R only [no name] Lane 2 transceiver clock and data recovery (CDR) is locked to data. R only [no name] Lane 2 transceiver clock and data recovery (CDR) is locked to reference clock. EDT, Inc. 2017 January 04... -
Page 44: 0X840064 Transceiver Reconfiguration Address And Control
[no name] Set to enable to frequency counter. 0x840078 Receive Frequency Counter Access / Notes: 32-bit read-only / STRATIX5_REGXL8(STRATIX5_FREQ_CNT_RX, 4) Access Name Description 31–24 – – Reserved. 23–0 R only [no name] Receive frequency counter value. EDT, Inc. 2017 January 04... -
Page 45: 0X84007C Transmit Frequency Counter
Lane 0 transmit PRBS check enable. [no name] Lane 0 transmit PRBS generate enable. – – Reserved. R only [no name] Lane 0 receive PRBS realtime error. R only [no name] Lane 0 receive PRBS latched error. EDT, Inc. 2017 January 04... -
Page 46: 0X840088 Prbs Control 1
Lane 2 receive PRBS synchronization. 3–2 – – Reserved. [no name] Lane 2 receive PRBS check enable. Lane 2 receive PRBS generate enable. [no name] 0x84008C PRBS Control 2 [Reserved] 0x840090 PRBS Control 3 [Reserved] EDT, Inc. 2017 January 04... -
Page 47: 0X840094 Prbs Control 4 [Reserved]
APPENDIX A: Registers for PCIe8g3 S5 Registers, Port: Port 4 (QSFP/+) 0x840094 PRBS Control 4 [Reserved] EDT, Inc. 2017 January 04... -
Page 48: Revision Log
APPENDIX A: Registers for PCIe8g3 S5 Revision Log Revision Log Below is a history of modifications to this guide. Date Rev. Pg(s) Detail 20170104 PH,RH 0001 Corrected “www.edt.com/downloads/api” to “www.edt.com/api/”. 20140730 PH,SB,TL 0000 Created this new guide. EDT, Inc. 2017 January 04...
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