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Service Information
31
When TP5 is LOW, if a shared memory request is pending prior to the falling edge (B) of the
clock oscillator, the Access Select flip-flop is clocked to determine which processor gets control
of shared memory. The output of the flip-flop is then sent to the various multiplexers that
control signal routing in the memory and hardware register circuitry.
After the multiplexers have had time to settle, the address latches (U39-42) are clocked on the
next rising edge (C) of the clock oscillator (TP5 also goes high). The latched address then
propogates to the RAMs and hardware register address decoding circuits.
On the next falling edge of the system clock (TP5) which is also the next rising edge of the clock
oscillator (E), the shared memory request at the 0 input of the first timing chain flip-flop is
clocked causing the flip-flop to clear. The output change
(Q
output goes low) immediately
disables clocking to the Access Select flip-flop and address multiplexer latches, and releases the
Z-80A WAIT line if the Z-80A is selected. The 3Y or 4Y outputs of the memory control
multiplexer (U32) are set to enable the appropriate data bus transceiver (U44 or U45), and the
shared write control line (SWR) is gated to RAM (U36 pins 4 & 5 both high). This sequence
initiates a memory read or write cycle.
The memory access (read or write) is complete on the next falling edge
(I)
of the system clock
(TP5). At this time, the second timing chain flip-flop is clocked, causing pin 8 to go low. This
disables the SWR line forcing it high (end of write cycle), and sends a DTACK (data acknow-
ledge) to the mainframe if the mainframe has access to shared memory. The controller then
hangs in the same state until the shared memory access request is removed by the processor.
When the processor releases the request line, the 0 input (U17 pin 2) goes high, releasing the
data bus transceivers. The timing chain then resets to its idle state. After the next rising clock
edge to U17 pin 3, the controller is ready to process a new memory request.
Hardware Registers
The four read and four write registers that are implemented completely in hardware (RAM is not
used) are selected when SA2 thru SA14 are all 0 (U36 pin 8 LOW). The hardware register
decoder (U21) combines SAO, SAl, and the shared read line to enable the appropriate register.
Only bit 7 is implemented in write registers 0 and 1. Register 0, interface reset, sets the Reset
flip-flop (U15 pins 8 thru 13). Register 1, interrupt enable, sets or clears the Interrupt Enable
flip-flop (U14 pins 1 thru 6).
The upper nibble (bits 4 thru 7) of read registers 0 and 1 are implemented by the tri-state
multiplexer (U33). SDO thru SD3 are held high (0) by pullup resistors, except that SD2 is pulled
low (1) by U33 pin 3 during reads from register 0 (interface
10).
Read register 0 provides the
Switch R setting (SW2 pin 8) and card identification to the shared data bus. Read register 1
provides the interrupt level switch settings, state of the interrupt request flip-flop, and the state
of the interrupt enable flip-flop.
Register 2 is the modem control and status register. Data written to this register is latched by the
modem control latch (U6). Data inputs are taken from the modem status register buffer (U5).
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