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26
Service Information
The interface communicates with the computer mainframe through interface circuitry that is
treated like memory addresses by the mainframe. Information is exchanged between the inter-
face and computer through shared RAM memory and hardware registers. Access to shared
memory and hardware registers is obtained through the shared memory controller. Data is
transferred on the shared data bus. Interaction between the interface and computer mainframe
is managed by interrupt circuitry and the address comparator connected to the upper bits of the
mainframe memory address bus.
The interface program ROM usually contains operating firmware for the Z-80A interface CPU
which executes the protocol-dependent programs stored in the ROM. Shared memory is used
to exchange information between the interface CPU and the mainframe computer. The inter-
face CPU controls the SIO and CTC chips which perform datacomm serial
110
operations (SIO)
and counter and timing functions (CTC).
It
also performs and controls various other interface
functions on command from the mainframe processor.
The modem control register latch and modem status register buffer hold control and status
information being exchanged between the modem and interface. Line drivers and receivers
convert the internal TTL signals to RS-232C or RS-449 electrical levels for transmission over
the datacomm link. Data format and protocol information are created by the interface CPU with
help from the CTC and SIO support chips. Default switch information is used by the interface
CPU to set up power-up and reset defaults as defined by the firmware in the Program ROM.
Z-80A System Operation
The Z-80A CPU, SIO, and CTC chips as well as the program ROM and default switches are tied
together through the internal Z-80A 16-bit address (ZA) bus and 8-bit data (ZD) bus. These
buses belong exclusively to the interface CPU and are not accessible by the mainframe com-
puter.
Shared RAM and registers are accessed through the shared data (SO) and shared address (SA)
buses. Access to the shared buses is controlled by the shared memory controller. In general,
bus access is granted to the first processor that requests the bus. If the shared memory controller
grants access to one processor and the other processor requests access during the memory
cycle, the controller holds the second processor off until the memory cycle is complete, after
which shared memory access is granted to the second processor. If a Simultaneous-request
conflict occurs, bus access defaults to the mainframe. Only 15 bits of address bus and 8 bits of
data bus are gated to the shared buses from the mainframe. The remaining mainframe address
bus bits are gated to the address comparator to establish select code identification. The address
comparator bits combine with the shared address bus bits to establish the range of mainframe
memory addresses that pertain to a particular interface. Upper-byte mainframe data bus bits (8
thru 15) are not used by the interface.
Select Code Recognition
The Address Decoder (U43) decodes mainframe upper memory address bits to detect card
accesses. The BAS input from the mainframe gates the comparator inputs to ensure that the
address is stable. When the address is recognized, the P
=
Q output is activated causing the IMA
(I'm Addressed) output to return acknowledgement to the mainframe. The DTACK (Data
Acknowledge) output is also enabled, and is activated later by the Shared Memory Controller.
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