IBM 1620 Manual page 31

Data processing system
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Procedure
1)
Operate NPRO to clear all check planes (reset cores
to "0").
2) Tum on read select switch.
3) Tum on A2-CBCR latch by grounding A 1 B20 F
(04.25.03.1). The output of A2-CBCR is used to
set all cores in A2 to the one status.
4) Tum on B2-CBCR latch by grounding A 1 B20 P
(04.25.03.1). The output of B2-CBCR is used to
set all cores in B2 to the one status.
5) Using CE start key, run the machine for a few
seconds.
6) Depress CE stop key. The cores in the A2 and B2
planes should be all set to the one status.
7) Remove ground wires from A2 and B2-CBCR's.
8) Using CE start key, run machine for a few seconds.
The A2 cores are being read out to A2-CBCR. With
A2-CBCR on and RBR-2 off, the comparing AND is
satisfied and at write time the A2 cores wi II be set
to the one status. The B2 cores are being read out
to B2-CBCR. With B2-CBCR on and RBR-2 off,
the XO causes a one to be written back into the
B2 cores.
Single cycle through all 80 buffer positions and
check that the A2 and B2 I ights come on for every
position. If the check is satisfactory, the A2 and
B2 sense amplifiers, read drivers, write drivers,
comparing AND and exclusive OR circuits are
working properly for a no compare condition. Vary
marginal voltage as needed.
To check the comparing AND and the exclusive OR for
a compare conditions and -to check the inhibit drivers,
the RBR-2 latch must be tumed on. With RBR-2 on:
1) The comparing AND will not be satisfied and the
one status of the A2 cores read out to A2-CBCR
will be inhibited from writing back into the A2
plane.
2) The XO circuit will have like inputs to both sides
on one cycle (B2 core reads out to tum on B2-CBCR)
and will therefore inhibit writing back into the
B2 plane.
On the next cyc Ie B2-CBCR wi
II
not be tumed on (no
cores in the one 'status in B2 plane) while RBR-2 is still
on. The XO circuit has unlike inputs and ones will be
written back into B2 plane. To check:
1) Tum on RBR-2 by grounding A1 B18 P (04.25.03.1).
2) Turn on single cycle switch.
3) Tum on read select switch.
3.25
4) Using CE start key, single cycle 00 through 79.
First cycle through
A2 and B2 on
Second cycle through
A2 off and B2 off
Third cycle through
A2 off and B2 on
Fourth cyc Ie through
Same as second
Fifth cycl e through
Same as third
This test can be made at electronic speeds. If failures
develop, scope the associated circuitry for I evels and
timings. Vary the marginal voltage as needed.
INTERLEAVE OPERATION
Reader or punch checks may occur with interleave
troubles.
Indications of Interleave Problems
1)
The 80th character transferred to the 1620 is
missing or incorrect. This could occur if the
punch trans accu scan latch is turned on while
the read disconnect latch is on. The extender
A 1 E09 (04. 10.08.2) to the AND A2 D20 is for
the purpose of preventing this condition. This
appl ies to pre
"J"
suffix 1622's only.
2) Incorrect or missing punching and reading could
occur in the punch operation latch A2 A 16
(04. 10 .09.2) fai Is to tum on during a punch
operation and a read operation is initiated by
the 1620.
3) If an attempt is made to select the read and punch
buffer simultaneously, nothing will be punched and
nothing will be loaded into the read buffer. (Units
read and write "X" drivers are inoperative). A
VRC check will resul t because nothing will be
placed in the SCR. Operating the CE read and
punch select switches at the same time will cause
the condition just described •
. 4) If data being loaded into the read buffer is
simultaneously punched in a card and this data
is not in the punch buffer, the II+S Punch buffer
scan
ll
to A2 B08 H (04.35.01.1) is probably
floating (open).
Interleave Trouble Diagnosis
Run read and punch "off line
ll
simultaneously.
If interleave failures do not occur, the failing inter-
lock is assoc iated with either transfer from or transfer
to the 1620. If failures do occur, they eliminate the
previously mentioned interlocks.
If the failures occur fairly frequently (every 5 or 6
cards), the fai I ing interlock is probably the read row
bit scan and punch buffer scan.

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