Yamaha WXA-50 Service Manual page 51

A B C D E
WXC-50
MAIN 2/3
L 2 0 5
1
4 1
1 2
3 2
3
E X C 2 4 C E 9 0 0 U
NETWORK 7
L 2 0 6
4 1
3 2
E X C 2 4 C E 9 0 0 U
C B 2 0 2
E T H _ R X _ M
2 H R 9 0 3 1 2 5 C Z F 2 8 6 6 0 H A N R U N
Z F 2 8 6 7 0 S U N J U N E T H _ R X _ P
E T H _ T X _ M
E T H _ T X _ P
D G N D
N C P U _
N C P U _ S P I _ S C K
N C P U _ S P I _ M O S I
N C P U _ S P I _ M O S I
R 2 1 4 N C P U _ S P I _ M I S O
N C P U _ S P I _ M I S O
3 3
N C P U _ S P I _ N _ C S
3 N C P U _ S P I _ N _ C S
N C P U _ N _ R S T
N C P U _ N _ R S T
R 2 1 5 N C P U _ M U T E 0
N C P U _ A M U T E
3 3
N C P U _ M U T E 1
N C P U _ R X D
N C P U _ M O S I
R 2 1 6 N C P U _ T X D
N C P U _ M I S O
3 3
R 2 1 9
to MAIN 1/3 3 3 X 4 N C P U _ N _ I N T
N C P U _ N _ I N T
4 D B G _ U A R T _ T X D
N C P U _ A D T _ M U T E
N C P U _ A D T _ M U T E
N C P U _ P H O L D
N C P U _ P H O L D
R 2 1 7
N C P U _
N C P U _ V B U S D R V
R 2 0 1 3 3
U S B _ V B U S
U S B _ V B U S _ P O N I C 2 0 4
2
1 0 0 4 R 2 1 2
+ 5 N 1
1 0 0
T C 7 S E T 0 8 F U
5 V +
I C 2 0 4 I C 2 0 4
D G N D 3 V -
5
D G N D
P R T _ U S B _ V B U S
N C P U _ P O N + 5 V + 5 N
+ 5 N
I C 2 0 6
R 5 5 2 7 K 0 0 1 D - T R
V i n V o u t
1 4
G N D O n
+ 5 V
6 2 G 3
D G N D
R 2 2 2 R 2 1 0
R 2 2 1 1 0 K 4 . 7 K D G N D
C B 2 0 1 1 0 K
U B A - 4 R - D 1 4 C - 2 F L G E N D G N D R 2 1 1
D 2 0 1
1 0 0
G N D
6
V B U S A V R L 1 6 1 A 1 R 1 N T B V O U T V I N R 2 2 0
1
L 2 0 1 n o _ u s e
D - R 5 5 2 4 N 0 0 4 A - T R - F T P 2 0 5
2
1 4
D +
3
USB
2 3
7 G N D
4 E X C 2 4 C E 9 0 0 U
D 2 0 2
F G
5
A V R L 1 6 1 A 1 R 1 N T B
D G N D
D G N D
C A P A C I T O R R E S I S T O R
R E M A R K S P A R T S N A M E R E M A R K S P A R T S N A M E
8
N O M A R K E L E C T R O L Y T I C C A P A C I T O R N O M A R K C A R B O N F I L M R E S I S T O R ( P = 5 )
S O L I D E L E C T R O L Y T I C C A P A C I T O R C A R B O N F I L M R E S I S T O R ( P = 1 0 )
N O M A R K C E R A M I C C A P A C I T O R M E T A L O X I D E F I L M R E S I S T O R
C E R A M I C T U B U L A R C A P A C I T O R M E T A L F I L M R E S I S T O R
P O L Y E S T E R F I L M C A P A C I T O R M E T A L P L A T E R E S I S T O R
P O L Y S T Y R E N E F I L M C A P A C I T O R F I R E P R O O F C A R B O N F I L M R E S I S T O R
M I C A C A P A C I T O R C E M E N T M O L D E D R E S I S T O R
P P O L Y P R O P Y L E N E F I L M C A P A C I T O R S E M I V A R I A B L E R E S I S T O R
S E M I C O N D U C T I V E C E R A M I C C A P A C I T O R C H I P R E S I S T O R
P O L Y P H E N Y L E N E S U L F I D E F I L M
S
C A P A C I T O R
9
N O T I C E ( m o d e l )
J J A P A N
U U . S . A
+ 7 A
C C A N A D A
R G E N E R A L
T C H I N A
K K O R E A
B D 0 0 G A 3 W E F J - E 2
A A U S T R A L I A
V C C V O U T
B B R I T I S H
10 N . C F B
G E U R O P E A N S T A N D A R D
L S I N G A P O R E
N . C G N D
E S O U T H E U R O P E
E N N . C
V T A I W A N
F R U S S I A N
P L A T I N A M E R I C A
S B R A Z I L
H T H A I
A G N D _ D A
11
+ 3 . 3 D A C + 3 . 3 E S D
+ 5 A
I C 2 0 9
R P 1 1 5 H 3 3 1 D - T 1 - F
I C 2 0 1 3 2 1
R P 1 3 0 K 3 3 1 D - T R
L X D C 2 H N 1 2 F - 1 6 2
G
C E / C E G N D 4 5 V i n
( 2 1 2 5 )
R 2 2 3
V D D V O U T
12
2 . 2
C P G N D A G N D
13
2
I C 2 1 0
1
3 N J M 8 0 8 0 R B 1 ( T E 1 )
R 2 1 3 N J M 8 0 8 0 R B 1 ( T E 1 )
5
1 0 K 7
I C 2 1 0
6
A G N D
C 2 2 9
R 3 5 4
1 . 0
1 / 2 5
14 8 V +
4 V -
R 3 5 5 C 2 3 0
1 . 0 1 / 2 5
+ 5 D S P + 3 . 3 D S P + 1 . 8 D S P
+ 5 V + 5 V
15
I C 2 0 8 I C 2 1 2
R P 1 3 2 H 3 3 1 D - T 1 - F R P 1 1 5 H 1 8 1 D - T 1 - F
I C 2 0 2 3 2 1
R 5 5 2 7 K 0 0 1 D - T R 3 2 1
V i n V o u t
1 4 4 5
4 5
G N D O n
2 G 3
16
D G N D D G N D D G N D
17
IC201: RP130K331D-TR
IC202, 206: R5527K001D-TR LOAD
CMOS-based positive voltage regulator
Small, ultra-low RON load switch with a soft-start
NC
VIN VOUT
V 4 1 V 1 4
DD OUT
18
IN A
Charge Soft Reverse
Pump Start Detector GND
Vref
Current Limit
CE GND
3 2 ON 3 2 GND
19
Pin No. Symbol Description IN B
Pin No. Symbol Description
1 V Supply Input Pin
IN
1 V OUT Output Pin
2 GND Ground Pin IN A
2 GND Ground Pin
3 ON ON/OFF Control Pin, Active High
3 CE Chip Enable
4 V OUT Switch Output Pin GND
4 V DD Input Pin
20
★ All voltages are measured with a 10MΩ/V DC electronic voltmeter. ● 電圧は、内部抵抗 10MΩの電圧計で測定したものです。
★ Components having special characteristics are marked ⚠ and must be replaced ● ⚠印のある部品は、安全性確保部品を示しています。部品の交換が必要な場合、
with parts having specifications equal to those originally installed.
★ Schematic diagram is subject to change without notice.
● 本回路図は標準回路図です。改良のため予告なく変更することがあります。
F G H I J K
S T 2 0 1
Z P 5 1 4 5 0
H 9
D G N D
C 2 0 5
D G N D to Network module
C B 2 0 4
1 0 / 1 0
1 3 4 2 0 3 5 6 0 W 3
C 2 0 7
1 2
R 2 4 5 0 . 1 / 1 0 ( B J )
N C P U _ A D T _ M C K R
3 4
1 0 K
5 6
N C P U _ A D T _ S D R 0 A D T 2 _ S D O
7 8
N C P U _ A D T _ W C K R A D T 2 _ W C K G P I O 5
1 0 9
S P I _ S C K N C P U _ A D T _ B C K R A D T 2 _ B C K G P I O 4
1 2 1 1
G P I O 3
1 4 1 3
INPUT SELECTOR
N C P U _ Z _ A U P _ M C K X D V S S
1 6 1 5
A D T _ S D O G P I O 2
1 8 1 7
N C P U _ Z _ A U P _ B C K X A D T _ B C K G P I O 1
2 0 1 9
N C P U _ Z _ A U P _ W C K X A D T _ W C K G P I O 0
2 2 2 1
N C P U _ Z _ A U P _ S D X 0 P L L V D D
2 4 2 3 + 3 . 3 D S P
2 6 2 5
D G N D
N C P U _ A U P _ M C K X R 2 4 2
2 8 2 7
2 2 0
3 0 2 9
N C P U _ A U P _ B C K X N M _ B C K
3 2 3 1
1 6 1 5 1 4 1 3 1 2 1 1 1 0 9
N C P U _ A U P _ W C K X N M _ W C K
3 4 3 3 I C 2 1 6 T C 7 4 V H C 1 5 7 F T ( E L
R 2 0 3
N C P U _ A U P _ S D X 0 N M _ S D 0 1 2 3 4 5 6 7 8 N M S _ M C K
3 6 3 5
1 0 0
N C P U _ A U P _ S D X 3 N M S _ B C K
3 8 3 7
N C P U _ A U P _ S D X 2 D G N D D G N D N M S _ W D L D I R _ X M C K O 2
4 0 3 9
V B U S D R V N C P U _ A U P _ S D X 1 N M _ S D 1 N M S _ D D R
4 2 4 1
4 4 4 3
U S B _ D M A P _ S C L R 2 4 1
4 6 4 5 2 2 0 X 4
A P _ S D A
4 8 4 7
S E L E C T = H : Y = B = D S D
+ 3 . 3 V M M C
S E L E C T = L : Y = A = P C M
5 0 4 9
U S B _ D P D B G _ U A R T _ R X D
5 2 5 1
R 2 3 8
S E L _ P C M / D S D
5 4 5 3
1 0 0
5 6 5 5
+ 5 W L A N + 5 N E T
5 8 5 7
+ 5 W L A N + 5 N E T iPod
6 0 5 9
AUTHENTICATION
D G N D D G N D
+ 5 N
+ 3 . 3 V M M C
NETWORK IN
I C 2 1 5
+ 3 . 3 V M M C
M F I 3 3 7 S 3 9 5 9
G N D V C C
S D A R S T
D G N D
N C S C L
N C N C
A p p l e D G N D
C o P r o c e s s o r
n o _ u s e
I 2 C A d d r = 2 0 h / 2 1 h ( R S T = L o w )
W X C
o n l y
No replacement part available.
サービス部品供給なし
A D T _ W C K
A D T _ S D O
A D T _ B C K
DIR
N M S _ D D R D I R
S E N 7 A N M S _ W D L
N M S _ B C K
+ 5 A
N M S _ M C K
M i r r o r
R 2 3 2
P R T _ P S 1
1 0 K
R 2 3 6
+ 3 . 3 D I R
0
R 2 3 7
0
+ 5 A
+ 1 . 2 E S V
+ 5 D I R
L 2 1 0
B K P 1 0 0 5 H S 6 8 0 - T
I C 2 1 4
G N D
1
4
E N 3 V o u t
2
A G N D
No replacement part available.
サービス部品供給なし
A G N D
R 2 4 9 R 2 5 0
P R T _ P S 1
+ 3 . 3 E S A
2 . 2 K 2 . 2 K i n t e r n a l i m p . = 1 0 K
+ 5 A
2 . 4 V r m s t o 3 V p p = - 7 d B
D S P _ P O N R 9 0 1 2 , 9 0 2 1 = 2 . 2 k
R 9 0 6 9 , 9 0 7 0 = 2 . 2 k
R 2 2 4
1 0
R 2 2 5 R 2 3 3
1 0 0 6 . 8 K
ANALOG IN
A G N D
+ 9 o p a
+ 5 D S P
DIGITAL IN
D G N D
C 3 4 7
2 2 0 P ( S L )
1 0 / 1 0
R 2 3 4
1 0 0 C 2 3 7
0 . 1 / 1 0 ( B J )
D G N D
3 2 1
U 2 0 1
5 4
J S R 2 B 1 5
L
O P T I N
OPT IN
IC203: TC7S14FU
Schmitt inverter
VCC
1 5
IC220: PCM5101APWR
A Y
106 dB audio stereo DAC with 32-bit, 384 kHz PCM interface
2
L H
3 4 H L Current
OUT Y
Segment 6
2
DIN (I S) 14 DAC
Current
Segment 7
IC204: TC7SET08FU
DAC
2 input AND gate
Zero
Data
Advanced Mute Control
Detector
1 5 VCC
A B Y
Clock Halt
Detection
L L L
2
L H L 1
LRCK 15
H L L Power 8
BCK 13
PLL Clock
3 4 OUT Y Supply 20
H H H
SCK 12 UVP/Reset POR Ch. Pump
3,9,19
5 4 2
パーツリストに記載されている部品を使用してください。
L M N O P Q
No replacement part available.
サービス部品供給なし
to MAIN 1/3
D i g i t a l 1 / 2
+ 3 . 3 D S P
+ 1 . 8 D S P
4 3 1 2
5 6 7 8
+ 3 . 3 D S P
D G N D
C 2 1 2
R 2 6 2
2 . 2 K R 2 6 5
1 0 / 1 0
R 2 6 8 2 . 2 K
C 2 1 3 2 . 2 K
R 2 7 0
0 . 1 / 1 0 ( B J ) R 2 0 6 2 . 2 K
2 . 2 K R 2 0 7
D G N D 2 . 2 K
O P E N
C 2 1 6
D S P 2 D V S S
T E S T b
G P I O 1 1 INPUT
D V D D 1 8
R 2 8 7
D G N D 1 0 0 X 4 SELECTOR
I R Q _ N D S P _ S D O 0
D V S S D S P _ W C K 0
+ 3 . 3 D S P
+ 3 . 3 D S P
O P E N D S P _ B C K 0
+ 1 . 8 D S P
C 2 8 1
0 . 1 / 1 0 ( B J )
C 2 1 4
D S P _ S D O 1 D I R _ S D O 2 A V C C
0 . 1 / 1 0 ( B J ) D S P _ W C K 1 D I R _ W C K 2 B S T
D G N D D G N D
D S P _ B C K 1 Y S E L E C T
C 2 7 0 C 2 8 3
D G N D R 2 8 8 G N D Y R 2 9 4
1 0 0 X 4
1 0 0
1 0 / 1 0 1 0 / 1 0 T C 7 W H 1 5 7 F K
S E L E C T = H : Y = B = D I R _ W C K 2 ( D S D L )
S E L E C T = L : Y = A = D I R _ S D O 2
C 2 7 3 C 2 8 4
0 . 1 / 1 0 ( B J ) 0 . 1 / 1 0 ( B J )
+ 3 . 3 D S P
R 2 5 6 D G N D
D I R _ W C K 2
D I R _ S D O 2 G P I O 5 O P E N
C 2 9 3
D I R _ B C K 2 G P I O 4 D S P D V S S
MIX IN
G P I O 3 T E S T b
1 0 0 X 4 D V S S G P I O 1 1
R 2 5 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0
D I R _ S D O 1 G P I O 2 D V D D 1 8
D G N D I C 2 2 3 T C 7 4 V H C 1 5 7 F T ( E L
D I R _ B C K 1 G P I O 1 I R Q _ N 1 2 3 4 5 6
D I R _ W C K 1 G P I O 0 D V S S
P L L V D D O P E N D G N D
1 0 0 X 4
R 2 5 9 D I R _ X M C K O 1
1 0 0 C 2 9 1
R 2 5 8
D I R _ B C K 3 0 . 1 / 1 0 ( B J )
D I R _ W C K 3
D I R _ S D O 3 S E L E C T = H : Y = B = D I R E C T ( D S D )
S E L E C T = L : Y = A = D S P
D G N D
INPUT
1 0 0 X 4
V + 5
SELECTOR
V - 3
D G N D
R 2 0 2
1 0 K
+ 3 . 3 D I R
D G N D
R 2 6 7 D I R _ M I S O
1 0 0
D I R _ M O S I
R 2 7 1 D A _ R - R 2 9 7
1 0 K 3 9 0
D I R _ S C K
D I R _ N _ C S
D A _ R + R 2 9 8
3 9 0
D S P _ S D O 1
D S P _ W C K 1
D S P _ B C K 1
D A _ L + R 2 9 9
R 2 7 2 3 9 0
D I R _ N _ R S T
1 0 0
+ 3 . 3 D S P
D A _ L - R 3 0 0
C 2 7 4 C 2 7 9
3 9 0
1 0 / 1 0 1 0 / 1 0
C 2 7 1 C 2 7 7
D G N D D I R _ N _ I N T DAC
C 2 6 0
R 2 6 6 1 2 P ( C H ) S E N 7 A D A _ S W R - R 3 0 1
6 8 0 1 . 5 K
+ 3 . 3 D I R
D A _ S W L - R 3 0 2
C 2 6 1
2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 . 5 K
I C 2 2 0 P C M 5 1 0 1 A P W R
M i r r o r
1 5 P ( C H ) 1 2 3 4 5 6 7 8 9 1 0
D G N D
+ 3 . 3 D S P
C 2 7 8
L 2 1 1
B K P 1 0 0 5 H S 6 8 0 - T 2 . 2 / 1 0 D A _ S W R + R 3 0 3
+ 3 . 3 D A C
C 2 7 5 C 2 8 2 C 2 8 8 1 . 5 K
D G N D
R 3 0 4
2 . 2 / 1 6 D A _ S W L +
C 2 7 6 C 2 8 9
1 . 5 K
1 0 / 1 0 1 0 / 1 0
R 2 7 8
0
A O U T _ S E L
C 2 8 5 C 2 9 0
2 2 0 0 P 2 2 0 0 P
( C H ) ( C H )
C 2 6 9
1 0 / 1 6
C 2 8 6
R 2 8 4
1 K
1 0 / 1 6
R 2 9 0
1 0 K
Q 2 0 4
6 7 8 9 1 0
M i r r o r
5 4 3 2 1 Q 2 0 5
R 2 9 1
+ 9 o p a
1 0 K
- 9 o p a
C 2 8 7 R 2 8 5
R 2 6 1 1 0 / 1 6 1 K
C 2 6 8 1 INPUT
R 2 7 6 R 2 7 5 C N T 1 = H : O U T = I N 2 = D e l a y e d A u d i o
1 0 / 1 6
C N T 1 = L : O U T = I N 1 = A U X I N
1 0 0 K 1 0 0 K SELECTOR
R 2 5 4 R 2 6 0 C 3 2 6
1 M 1 M C 2 5 8 C 2 6 4
n o _ u s e
C 2 4 7 C 2 5 1
4 7 P ( C H ) 4 7 P ( C H )
C 3 2 8
2 2 0 P ( S L )
C 2 5 9 C 2 6 5
0 . 0 1 ( B )
A G N D
C 3 2 9
2 2 0 0 P 2 2 0 0 P
1 0 0 P ( S L )
R L R
A U X I N A U X O U T S W O U T
AUX SUBWOOFER
IC209: RP115H331D-T1-FE
IC212: RP115H181D-T1-FE
OUT L
CMOS-based positive voltage regulator CMOS-based positive voltage regulator
OUT R
V 4 V V 4 V
DD 5 OUT DD 5 OUT
- -
1 V 1 V
FB FB
+ +
Vref Vref
Current Limit Current Limit
Thermal Shutdown Thermal Shutdown
CPVDD (3.3V)
Reverce Reverce
AVDD (3.3V)
Detector Detector
DVDD (3.3V)
CE 3 2 GND CE 3 2 GND
GND
Pin No. Symbol Description Pin No. Symbol Description
1 V FB Feedback Pin 1 V FB Feedback Pin
2 GND Ground Pin 2 GND Ground Pin
3 3
CE Chip Enable Pin CE Chip Enable Pin
4 V Input Pin 4 V Input Pin
DD DD
5 V OUT Output Pin 5 V OUT Output Pin
R S T U V W
M A I N ( 1 )
MAIN (1) D i g i t a l 2 / 2
2 0 1 - 5 0 0
D A _ R -
D A _ R +
D A _ S W R +
D A _ S W R -
L 2 1 6
B L M 2 1 P G 6 0 0 S N 1 D
L 2 1 8
B K P 1 0 0 5 H S 6 8 0 - T
L 2 1 7 A G N D
B L M 2 1 P G 6 0 0 S N 1 D
A G N D A G N D
C 3 3 5
A G N D
1 0 0 0 P ( B )
C 3 3 2
C 3 4 8
3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 C 3 3 1 C 3 2 7
1 0 0 0 P ( B ) G N D _ D A V C C _ R 1 0 / 1 0
3 7 2 4
C 3 2 5
D G N D D A T A 8 G N D _ A 0 . 1 / 1 0 ( B J )
3 8 S A B R E 9 0 0 6 A S : A D D R A D D R ( 0 x 9 2 ) 2 3
1 0 0 0 P ( B )
D A T A 7 DAC G N D _ D C 3 5 0
3 9 2 2
C 3 3 3
D A T A 6 V D D 1 0 / 1 0
4 0 2 1
C 3 4 9
D A T A 5 D V C C _ B 1 / 2 5
4 1 2 0
C 3 3 6
D A T A 4 1 9 X I 1 0 0 0 P ( B )
4 2
D A T A 3 I C 2 2 8 X O 1 0 P ( C H )
4 3
S A B R E 9 0 0 6 A S - R E E 1 8
D A T A 2 Y G 8 9 2 A 0 S C L D A C _ S C L
4 4 1 7
D A T A 1 S D A D A C _ S D A
4 5 1 6
9 D A C C 3 3 7
D A T A _ C L K G N D _ A / D
4 6 1 5
C 3 3 4
7 8 R 3 1 1 V D D A V C C _ L 1 2 P ( C H )
4 7 1 4
4 7 X 4
D V C C _ T N C
4 8 1 3
D G N D 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2
A G N D
D 2 0 3
1 S S 3 5 5 V M A G N D A G N D A G N D R 3 4 5 D A C _ R S T
D 2 0 4 1 0 0
1 S S 3 5 5 V M
R 3 2 4 D A _ S W L -
n o _ u s e
D A _ S W L +
C 3 1 2 D A _ L +
1 0 0 0 P ( B ) D A _ L -
D G N D A G N D
- 9 o p a
- 9 V
R 3 1 2
1 . 5 K
C 3 0 4
R 3 0 5
1 . 8 K
0 . 0 0 0 3 3
4 V -
C 3 1 9
R 3 3 2 R 3 3 9
2 I C 2 2 4 I C 2 2 4
1 3 3 0 1 0 0
1 0 / 1 6
3 N J M 8 0 6 8 G ( T E 2 )
R 3 3 3 R 3 4 0
C 3 0 5
1 0 K 1 0 K
Q 2 0 8 Q 2 1 1
0 . 0 0 0 3 3 P R E _ R ( C h 2 )
R 3 1 5
1 . 5 K A G N D L
R 3 1 6
A G N D R P R E _ L ( C h 1 )
1 . 5 K
C 3 0 6
R 3 0 7
Q 2 0 9 Q 2 1 2
1 . 8 K R 3 3 4 R 3 4 1
0 . 0 0 0 3 3
N J M 8 0 6 8 G ( T E 2 ) 1 0 K 1 0 K
5
C 3 2 0
7 R 3 3 5 R 3 4 2
I C 2 2 4 I C 2 2 4
6
3 3 0 1 0 0
1 0 / 1 6
A G N D A G N D
8 V + R 3 5 1
1 . 8 K C 3 0 7 1 0 0
R 3 0 8
0 . 0 0 0 3 3
MIX OUT
R 3 1 9
1 . 5 K
+ 9 o p a
+ 9 V
R 3 2 0 R 3 2 1
6 . 8 K 3 3 0
R 3 0 9 C 3 0 8
5 . 6 K 0 . 0 1 5 / 3 5
4 V -
C 3 2 1
R 3 3 6 R 3 4 3
2
I C 2 2 5 I C 2 2 5
1 3 3 0 1 0 0
4 7 / 6 . 3
3
R 3 3 7 R 3 4 4
N J M 8 0 8 0 R B 1 ( T E 1 )
C 3 0 9
1 0 K 1 0 K
Q 2 1 0 Q 2 1 3
0 . 0 1 5 / 3 5
R 3 2 3 R 3 2 2
6 . 8 K 3 3 0
A G N D
N J M 8 0 8 0 R B 1 ( T E 1 )
5
7
I C 2 2 5 I C 2 2 5
6
8 V +
SUBWOOFER OUT
IC228: SABRE9006AS-REEL
8-channel audio DAC
7 30 16 17
CONTROL INTERFACE
38-45
OVERSAMPLING
DATA [8:1]
FILTER
DSD/PCM Jitter
DAC (8x)
Interface De-emphasis, Reduction
DATA_CLK 46 Volume Control,
Soft Mute,
Zero Detect
19
XI (MCLK)
OSC
XO POWER SUPPLY
18
Details of colored lines
Red / full line: Power supply (+)
Red /dashed line: Power supply (-)
Orange: Signal detect
Yellow: Clock IC218: NJM2752RB2 (TE1)
2-input/1-output stereo audio selector
Green: Protection detect
Brown: Reset signal
Blue: Panel key input
LOGIC
IN1A 2
IC224: NJM8068G (TE2)
IN1B 9
2 circuit low noise bipolar input
audio operational amplifier
IN2A 4
7
A OUTPUT 1 8 V+ IN2B
A- INPUT 2 7 B OUTPUT
A+ INPUT 3 6 B- INPUT
V- 4 5 B+ INPUT
X Y Z AA AB
WXA-50/WXC-50
IC213: BD00GA3WEFJ-E2
IC205, 219: YSS952-QZE2
300 mA variable output LDO regulator
Sound producer-2
GND 3 8 Vcc
GPIO0 7
OCP
SOFT
START + GPIO1 6
+
–
1 Vo GPIO2 5 SDSP
2 FB
GPIO3 3
EN 5
TSD
GPIO4 2
GPIO5 1
General Audio
IO Interface
switch (AIF)
GPIO6 32
GPIO7 30
IC214: LXDC2HN12F-162
GPIO8 28
Micro DC-DC converter
GPIO9 27 MDSP2
EN
GPIO10 26
2
GPIO11 21
L
Control IC
VIN 1 3 VOUT
C
FM Synthesizer
4 IC_N 9
GND
XIN
12
Clock
PLL
Registers
Generator
XOUT 13
IC216, 223: TC74VHC157FT
Quad 2-channel multiplexer
IRQ_N 19
SELECT 1 16 Vcc
SCL 15 Microprocessor Interface
1A 2 A S G 15 ST
SDA 16
1B 3 B A 14 4A
1Y 4 Y B 13 4B
2A 5 12 4Y
A Y
2B 6 11 3A
B A
2Y 7 Y Y B 10 3B Preset ROM
GND 8 9 3Y
TESTb 22
IC208: RP132H331D-T1-FE
Voltage regulator
V DD 4 5 V OUT
Vref
Current Limit
Thermal Shutdown
CE 1 2 GND
W 2 0 1
n o _ u s e
B T L S y n c 1
A M P _ E N 2
Pin No. Symbol Description
P R T _ O C 3
1 CE Chip Enable Pin ("H" Active)
P R T _ T H M 4
2 GND Ground Pin
5
3
NC No Connection
A G N D R 6
4 VDD Input Pin
A G N D L 7
5 VOUT Output Pin
8
M T _ N _ P R E
8
P R E _ R
7
P R E _ E
6 IC210, 221, 225: NJM8080RB1 (TE1)
IC222: TC7WH157FK
P R E _ L
5
Dual operational amplifier 2 channel multiplexer
S W _ M O D E
4
D O U T
3
D G N D A 1 8 V CC
2
+ 5 D S P
1 A OUTPUT 1 8 V+
B 2 7 ST
C B 2 0 5
P H I A
A-INPUT 2 7 B OUTPUT
Y 3 6 SELECT
Page 52 P2
A+INPUT 3 B 6 B-INPUT
GND 4 5 Y
to MAIN (4)_W801
V- 4 5 B+INPUT
IC211: R5524N004A-TR-FE
USB High-side power switch
VIN 1 5 VOUT
GATE
CURRENT
EN 3
CONTROL
LIMIT
UVLO
FLG DELAY
4 FLG
THERMAL
SHUTDOWN
2
GND
IC217: PCM9211PTR
216-kHz digital audio interface transceiver (DIX) with stereo ADC and routing
FILT
43
AUXIN0
AUTO
RXIN7
RXIN0 DIR
RXIN0 37 DIR 20 SCKO
DOUT
RXIN1 ADC MAIN
RXIN1 35 PLL 19 BCK
OUTPUT
RXIN2 AUXIN0
RXIN2 33 PORT 18 LRCK
SCKO/BCK/LRCK
RXIN3 AUXIN1
RXIN3 32 17 DOUT
RXIN4 Lock:DIR AUXIN2
RXIN4/ASCKIO 31
Unlock:ADC
30 RXIN5 Clock/Data
RXIN5/ABCKIO
Recovery
RXIN6
RXIN6/ALRCKIO 29
RXIN7 AUTO
RXIN7/ADIN0 28
DIR
RXIN8 Lock ADC
MPIO_A0 3
Detection
DIT
RXIN9 AUXIN0
MPIO_A1 4 MPIO_A
SELECTOR RXIN10 AUXIN1
MPIO_A2 5
RECOUT0
MPIO_A3 6 RXIN11 AUXIN2
DAC [8:1] DITOUT RECOUT1
FILTER
RECOUT0
(8x) DACB [8:1]
MPO0/1 15 MPO0
RECOUT1
SELECTOR
ADC 16 MPO1
DITOUT
AVCC
VREF VINL 47
ADC Mode
AGND ADC
VINR 48 Control
VCOM 44 Com. Supply
AUTO
ADC Standalone DIR
MPIO_C0 7 11 MPIO_B0
8 ADC
MPIO_C1 MPIO_C AUXOUT MPIO_B 12 MPIO_B1
SELECTOR AUXIN0 SELECTOR
MPIO_C2 9 13 MPIO_B2
AUXIN1 AUXIN2
MPIO_C3 10 AUXIN1 14 MPIO_B3
AUXIN2
ADC Clock
(SCK/BCK/LRCK)
Divider
XTI 39
5 OSC
CNT1 XTO 40
XMCKO SBCK/SLRCK
Secondary SCK/LRCK
(To MPIO_A and MPO0/1) (To MPIO_A)
XMCKO Divider
Divider Selector
OUTA
1
REGISTER EXTRA DIR FUNCTIONS
MC/SCL 25 2 1 ERROR/INT0
SPI/I C
Function DIR CS DIR DIR ERROR DETECTION
MDI/SDA 24 INTERFACE 2 NPCM/INT1
Control (48-bit) PC and PD IS Calculator
Non PCM DETECTION
MDO/ADR0 23
Is Calculator
MPIO_A
MS/ADR1 26 GPIO/GPO DIT CS DIR All Port Flags
Data (48-bit) Interrupt IS Calculator DTS-CD/LD Detection MPIO_B
10 OUTB
Validity Flag MPIO_C
User Data
MPO0
POWER SUPPLY Channel Status Data
RST 34 Reset and BFRAME Detection
3 V + MPO1
Mode ADC DIR DIR ALL Interrupt System
MODE 27
Set ANALOG ANALOG ANALOG
Vref 6 Vref
46 45 42 41 36 38 22 21
8
GND VCCAD AGNDAD VCC AGND VDDRX GNDRX DVDD DGND
51