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Table of Contents
Related Manuals for Mesa 4C81
Summary of Contents for Mesa 4C81
- Page 1 4C81 MANUAL Version 2.1...
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Page 3: Table Of Contents
4C81 SERIAL ADAPTER ........ - Page 4 Table of Contents SOFTWARE GENERAL ........... . . 17 BOOTLOADER .
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Page 5: General
12 I/O bits on a 20 pin 2MM header organized as 6 LVDS pairs with grounds between pairs. The 4C81 can run Linux or NetBSD and has a jumper selectable netboot option with NFS support to allow simple system debug and software development. -
Page 6: Hardware Configuration
When W8 is in the right hand position, the 4C81 will boot from NAND flash. When W8 is in the left hand position the 4C81 will attempt a net boot. Network boot is always from Ethernet port 0. -
Page 7: Connectors
CONNECTORS CONNECTOR AND DEFAULT JUMPER LOCATIONS 4C81 MANUAL 3... -
Page 8: Power/Serial Console Connector
TO 4C81 4C81 SERIAL ADAPTER The 4C81 serial adapter converts the DTE pinout of the 4C81 to DCE for direct connection to PC type 9 pin serial ports, and also has a 4 pin .1" 5V power connector. The 5V connector on the serial adapter is pinned out as follows:... -
Page 9: Fpga/Cpld Lvttl Connector
FPGA/CPLD LVTTL CONNECTOR P4 is the FPGA/CPLD LVTTL connector. P4 is a 50 pin .1" header. P4 is compatible with Mesa’s Anything-I/O daughter cards with the restriction that FPGA I/O signals are not 5V tolerant. The CPLD I/O is 5V tolerant. -
Page 10: Fpga/Cpld Lvds Connector
Note that The DCI (internal termination) feature does not work properly on Rev.A cards so if the LVDS feature is used, External termination must be supplied. This is fixed on card rev. B and above. CPLD versions of the 4C81 provide 12 I/O bits on the LVDS pins. ETHERNET CONNECTORS The 4C81 has 2 Ethernet ports. -
Page 11: Jtag Connector
4C81s CPU and FPGA.. P2 connector pinout is as follows: FUNCTION TO 4C81 TO 4C81 FROM 4C81 TO 4C81 /RST TO 4C81 2.5V /ROMCS TO 4C81 (test mode only) /ROMOE TO 4C81 (test mode only) /ROMWE TO 4C81 (test mode only) 4C81 MANUAL 7... -
Page 12: Cpu Operation
PC/104-PLUS bus. SERIAL CONSOLE The 4C81 has a single serial port that is used as console I/O by the boot ROM and Linux or NetBSD. The default communication parameters are: 38400 baud, 8 bits, no parity. -
Page 13: Gpio Bits
CPU OPERATION CPU GPIO BITS The 4C81 CPU chip has 16 GPIO bits that are used for various on card functions. The bit definitions are as follows: GPIO-0 INPUT PCI INTERRUPT GPIO-1 INPUT WLAN RFON SENSE GPIO-2 INPUT FPGA/CPLD IRQ... -
Page 14: Fpga Option
CPU OPERATION FPGA OPTION The 4C81 can be provided with an on card Spartan3 FPGA with 200K or 400K gates. This FPGA can be used for custom I/O or a co-processor. 36 uncommitted FPGA I/O bits are available for user applications. 24 of these I/O bits are designed for single ended 3.3V or 2.5V LVTTL applications and 12 are designed for differential 2.5V LVDS applications. -
Page 15: Fpga Configuration
FROM FPGA Notes: FPGA clock is normally the same as the SDRAM clock = 125 MHz. LED is green LED CR10 on the bottom right hand side of the 4C81 card FPGA CONFIGURATION The FPGA is configured by writing the bit file to the memory region defined for ECSN0. -
Page 16: Example Fpga Config File
In one shot mode, the counters can be programmed to drive an I/O pin. VHDL source and .UCF files for the example are provided with the software distribution image for the 4C81. A detailed register map of the example configuration is provided in the file 4c81ioregisters. -
Page 17: P3 Pinout With Example Fpga Configuration
FPGAPOKE -R 0x24 0x00ffffff -s Would set 24 bit IO PORTA’s DDR register so that all I/O pins were programmed as outputs. FPGAPOKE -R 0x20 0x00aaaaaa -s Would set the 24 output bits to alternate 1's and 0's 4C81 MANUAL 13... -
Page 18: Cpld I/O
IO pins on connectors P3 and P4. CPLD CPU INTERFACE The CPLD connects the low 16 bit half of the 4C81's 32 bit data bus. 6 addresses are connected to the CPLD giving a address span of 64 16 bit words. In addition the CPLD connects to CPU /ECS0, 125 MHz bus clock and read and write strobes, reset and CPU GPIO2 which can be used as an interrupt. -
Page 19: Standard Cpld Configuration
CPU OPERATION STANDARD CPLD CONFIGURATION The 4C81-N (without FPGA option) has a simple CPLD (Xilinx 9572XL-PQ100) to provide 36 GPIO bits on connector P3 and P4. The standard CPLD configuration provides 36 I/O pins, 24 on P4, and 12 on P3. The 24 I/O bits on P4 can be individually programmed as inputs or outputs. -
Page 20: P3 Pinout With Standard Cpld Configuration
GPIO pins on the CPU. To avoid interference from the CPU while externally programming the CPLD, the CPU should be held reset. This is easily done by placing a 2mm jumper on pins 5 and 6 of CPU JTAG connector P2. 4C81 MANUAL 16... -
Page 21: General
NAND flash when updating the kernel. The netboot option can also be used to initialize the NAND flash on a 4C81 with a blank or corrupted NAND flash image. Jumpers W8 and W10 determine the low level boot options:... -
Page 22: Netboot Requirements
SOFTWARE NETBOOT REQUIREMENTS In order for the 4C81 to boot from the network, a NFS and a DHCP server must present and properly configured. The DHCP server must be configured with boot options in dhcpd.conf for the hardware address or address range of the 4C81(s) -
Page 23: Netbsd Software
4C81 that will need to be returned to MESA for repair. All 4C81 boot images have a file name like boot81.xxxk where xxx is the boot file image size. -
Page 24: Nand Flash Updating
NETBSD SOFTWARE NAND FLASH UPDATING The NAND flash on the 4C81 is used as a live read-only file system. It contains the operating system and utility programs. New NAND flash images can be written to the 4C81 with the nandstore utility. Nandstore should only be run when the 4C81 is net booted or running in single user mode. -
Page 25: Netbsd Nand Flash Image
In order to permanently change any program, script or file on the 4C81 NetBSD NAND flash distribution, the filesystem must be temporarily be placed into R/W mode. There are 2 scripts in the /mesa directory of the distribution that change the mode of the filesystem to Read/Write and to Read/Only:... -
Page 26: Enabling Sshd
These passwords must be changed before the 4C81 is deployed in a real application. NETBSD NET BOOT BINARY DISTRIBUTION To net boot the 4C81, you must install the following file sets in the NFS exported directory: 4C81NetBSD.tgz Base distribution including compiler plus NAND image and flash utilities. -
Page 27: Netbsd Toolchain
The NFS base distribution mentioned above can be used to compile applications directly on the 4C81. It’s no speed demon but may be acceptable for small projects. NFS swap may need to be configured for larger projects. Its also possible to cross compile applications and kernels on NetBSD 386, Linux-X86 or Windows (Using Cygwin). -
Page 28: Linux Software
LINUX SOFTWARE GENERAL The 4C81 can be supplied with a version 2.6 Linux system. Linux operation is somewhat different from NetBSD because a different NAND file system is used. This file system is YAFFS. Since the boot loader does not yet support YAFFS, the Linux kernel is first loaded from NOR flash and then launched. - Page 29 NFS booting Linux kernel. If the kcmd variable is not present., the default "root=/dev/mtdblock0,ro" string is passed to the NOR booting kernel. A left-positioned W10 jumper makes the bootloader to ignore SEEPROM contents and use the defaults for both kcmd and netkcmd. 4C81 MANUAL 25...
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Page 30: Specifications
(3.3V power supplied to PC/104-PLUS bus and MiniPCI card by 4C81s on card 3.3V regulator) 5V POWER for PC104+MiniPCI ---- ---- (5V power is feed-through, there is no 5V regulator on 4C81) ENVIRONMENT: OPERATING TEMP. OPERATING TEMP. (-I version) OPERATING HUMIDITY...
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