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Mesa 5i25 Manual

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5I25
ANYTHING I/O
MANUAL
Version 1.10

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Summary of Contents for Mesa 5i25

  • Page 1 5I25 ANYTHING I/O MANUAL Version 1.10...
  • Page 2 This page intentionally not blank...

  • Page 3: Table Of Contents

    5I25 I/O CONNECTOR PIN-OUT ........5...
  • Page 4 Table of Contents SUPPLIED CONFIGURATIONS ........17 HOSTMOT2 .

  • Page 5: General

    The MESA 5I25 SuperPort is a low cost, general purpose programmable I/O card for the PCI bus. The 5I25 is a low profile PCI card and is available with standard or low profile brackets. The 5I25 uses standard parallel port pinouts and connectors for compatibility with most parallel port interfaced motion control / CNC breakout cards, allowing a motion control performance boost while retaining a reliable real time PCI interface.

  • Page 6: Hardware Configuration

    PCI connector towards the person doing the configuration. BREAKOUT POWER OPTION The 5I25 has the option to supply 5V power from the host computer to the breakout board. This option is used by all Mesa breakout boards to simplify wiring. The option uses 4 parallel cable signals that are normally used as grounds for supplying 5V to the remote breakout board (DB25 pins 22,23,24 and 25).

  • Page 7: Preconfig Pullup Enable

    HARDWARE CONFIGURATION PRECONFIG PULLUP ENABLE The Xilinx FPGA on the 5I25 has the option of having weak pull-ups on all I/O pins at power-up or reset. The default is to enable the pull-ups. To enable the built-in pull-ups, (the default condition) jumper W4 should be placed in the UP position. To disable the internal pull-ups, W4 should be in the DOWN position.

  • Page 8: Connectors

    CONNECTORS CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS 5I25...

  • Page 9: 5I25 I/O Connector Pin-Out

    I/O CONNECTORS The 5I25 has 2 I/O connectors, the primary DB25F connector P3 and the secondary 26 pin header connector P2, please see the 5I25IO.PIN file on the 5I25 distribution disk. 5I25 IO connector pinouts are as follows: P3 BACK PANEL DB25F CONNECTOR PINOUT...
  • Page 10 Note: 26 pin header P2 will match standard parallel port pin-out if terminated with flat cable 26 pin receptacle/DB25F cable with pin1s connected (and header pin 26 left open) A cable/bracket hardware kit is available from MESA for the second port. 5I25...

  • Page 11: Jtag Connector Pinout

    EEPROM can be re-programmed using Xilinx’s Impact tool. For reprogramming, the card can be powered in a standard PCI slot or if desired, 3.3V power can be applied via the JTAG connector. P1 JTAG CONNECTOR PINOUT FUNCTION +3.3V 5I25...

  • Page 12: Operation

    OPERATION FPGA The 5I25 use a Xilinx Spartan6 ~400k gate FPGA in a 144 pin QFP package: XC6SLX9-PQ144. FPGA PINOUT The local bus and I/O interface FPGA pinouts are described in the 6i25.ucf file in the /configs/hostmot2/source directory of the 5i25.zip file.

  • Page 13: Configuration

    The 5I25 is configured at power up by a SPI EEPROM. This EEPROM is an 8M bit chip that has space for two configuration files. Since all PCI bus logic on the 5I25 is in the FPGA, a problem with configuration means that PCI access will not be possible. This condition is only fixable by reprogramming the EEPROM via the JTAG connector P1, which is awkward and slow at best.
  • Page 14 FALLBACK CONFIGURATION BLOCK 1 0x30000 FALLBACK CONFIGURATION BLOCK 2 0x40000 FALLBACK CONFIGURATION BLOCK 3 0x50000 FALLBACK CONFIGURATION BLOCK 4 0x60000 FALLBACK CONFIGURATION BLOCK 5 0x70000 RESERVED 0x80000 UNUSED/FREE 0x90000 UNUSED/FREE 0xA0000 UNUSED/FREE 0xB0000 UNUSED/FREE 0xC0000 UNUSED/FREE 0xD0000 UNUSED/FREE 0xE0000 UNUSED/FREE 0xF0000 UNUSED/FREE 5I25...
  • Page 15 USER CONFIGURATION BLOCK 2 0x130000 USER CONFIGURATION BLOCK 3 0x140000 USER CONFIGURATION BLOCK 4 0x150000 USER CONFIGURATION BLOCK 5 0x160000 UNUSED/FREE 0x170000 UNUSED/FREE 0x180000 UNUSED/FREE 0x190000 UNUSED/FREE 0x1A0000 UNUSED/FREE 0x1B0000 UNUSED/FREE 0x1C0000 UNUSED/FREE 0x1D0000 UNUSED/FREE 0x1E0000 UNUSED/FREE 0x1F0000 UNUSED/FREE 5I25...

  • Page 16: Bitfile Format

    -g CRC:enable bitgen options must be set. WARNING: Never write a bitfile that is not designed for a 5I25 into the 5I25s EEPROM as this will likely "brick" the 5i25 card and require he card to be returned to Mesa for repair.

  • Page 17: Spi Interface Description

    OPERATION SPI INTERFACE DESCRIPTION This is the register level description of the simple SPI interface to the 5I25's configuration EEPROM. This hardware is built into all Mesa 5I25 configurations. This information is only needed if you are writing your own programming utility.

  • Page 18: Free Eeprom Space

    JTAG connector. CLOCK SIGNALS The 5I25 has two FPGA clock signals. One is the PCI clock and the other is a 50 MHz crystal oscillator on the 5I25 card. Both clocks a can be multiplied and divided by the FPGAs clock generator block to generate a wide range of internal clock signals.

  • Page 19: Leds

    OPERATION LEDS The 5I25 has 2 FPGA driven user LEDs (User 0 and User 1 = Green), and 2 status LEDs (red). The user LEDs can be used for any purpose, and can be helpful as a simple debugging feature. A low output signal from the FPGA lights the LED. See the 5I25IO.PIN file for FPGA pin locations of the LED signals.

  • Page 20: Interface Cables

    OPERATION INTERFACE CABLES Mesa daughtercards use a male to male DB25 cable to interface to the 5I25. For noise immunity and signal fidelity it is suggested that only IEEE-1284 rated cables be used. IEEE-1284 rated cables have a twisted pair shield wire for each signal wire and an overall shield terminated in the metal connector shell.

  • Page 21: Supplied Configurations

    (four used locally on the 7I77s and two fed through for additional remotes), a watchdog timer and GPIO. 7I77_7I76 7I77_7I76 is a configuration intended to work with a 7I77 six axis analog servo daughtercard on P3 and a 7I76 daughtercard on P2. 5I25...

  • Page 22: I77_7I74

    Each of the configurations has an associated file with file name extension .pin that describes the FPGA functions included in the configuration and the I/O pinout. These are plain text files that can be printed or viewed with any text editor. 5I25...

  • Page 23: Specifications

    PCI supplied 3.3V 5V POWER SUPPLY 4.5V 5.5V PCI supplied 5V 3.3V POWER CONSUMPTION: ---- 400 mA Depends on FPGA Configuration MAX 5V CURRENT TO I/O CONNS 1000 mA Each (PTC Limit) TEMPERATURE RANGE -C version TEMPERATURE RANGE -I version 5I25...

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