Texas Instruments TCM4300 Data Manual
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Texas Instruments TCM4300 Data Manual

Texas Instruments TCM4300 Data Manual

Advanced rf cellular telephone interface circuit (arctic)
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TCM4300
Advanced RF Cellular Telephone Interface Circuit
(ARCTIC )
Data Manual
1996
Mixed-Signal Products

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Summary of Contents for Texas Instruments TCM4300

  • Page 1 TCM4300 Advanced RF Cellular Telephone Interface Circuit (ARCTIC ) Data Manual 1996 Mixed-Signal Products...
  • Page 2 Printed in U.S.A. SLWS010F 10/96...
  • Page 3 TCM4300 Data Manual Advanced RF Cellular Telephone Interface Circuit (ARCTIC ) SLWS010F October 1996 Printed on Recycled Paper...
  • Page 4 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current.

  • Page 5: Table Of Contents

    Parameter Measurement Information 3.1 MCLKOUT Timing Requirements 3.2 TCM4300 to Microcontroller Interface Timing Requirements (Mitsubishi Read Cycle) ..........
  • Page 6 3.9 TCM4300 to Microcontroller Interface Timing Requirements (Motorola 8-Bit Write Cycle) 3.10 Switching Characteristics, TCM4300 to DSP Interface (Read Cycle) 3.11 Switching Characteristics, TCM4300 to DSP Interface (Write Cycle) Principles of Operation ...........
  • Page 7 (Motorola 8-Bit Read Cycle, MTS [1:0] = 01) 3–9 Microcontroller Interface Timing Requirements (Motorola 8-Bit Write Cycle, MTS [1:0] = 01) 3–10 TCM4300 to DSP Interface (Read Cycle) 3–11 TCM4300 to DSP Interface (Write Cycle) 4–1 Power Ramp-Up/Ramp-Down TIming Diagram 4–2...
  • Page 8 List of Tables Table 4–1 TCM4300 Receive Channel Control Signals 4–2 RXIP, RXIN, RXQP, and RXQN Inputs (AV 4–3 Receive (RX) Channel Frequency Response (FM Input in Analog Mode) 4–4 Receive (RX) Channel Frequency Response (RXI, RXQ Input in Digital Mode) 4–5...

  • Page 9: Introduction

    DSP processing load during subscriber standby mode. In the digital mode, the TCM4300 accepts I and Q baseband data and performs A/D and D/A conversion and square-root raised-cosine filtering using dual 10-bit sigma-delta converters. The TCM4300 also has a /4-DQPSK modulation encoder for dibit-to-symbol conversion in the digital transmit mode.

  • Page 10: Tcm4300 Functional Block Diagram

    TCM4300 Functional Block Diagram Low- TXIP Pass Filter TXIN Low- TXQP Pass Filter TXQN Offset Anti- RXIP aliasing RXIN Filter Anti- RXQN aliasing RXQP Filter Low- Wide-band Pass Data Filter Demodulator D/As 09h(D) 0Ah(D) Control Registers 0Bh(D) PWRCONT PAEN OUT1...

  • Page 11: Pin Assignments

    Pin Assignments RSSI RXQN RXQP RXIN RXIP PWRCONT TXIP TXIN TXQP TXQN TXEN TXONIND PAEN PZ PACKAGE (TOP VIEW) DSPA0 DSPA1 DSPA2 DSPA3 DSPCSL DSPRW DSPSTRBL MCLKOUT XTAL MCLKIN MCCLK RSOUTL RSOUTH RSINL MCD7 MCD6 MCD5 MCD4 MCD3 MCD2 MCD1 MCD0 1–3...

  • Page 12: Terminal Functions

    Terminal Functions TERMINAL NAME Automatic frequency control. The AFC DAC output provides the means to adjust system temperature-compensated reference oscillator (TCXO). Automatic gain control. The AGC digital-to-analog converter (DAC) output can be used to control the gain of system receiver circuits. AV DD REF —...
  • Page 13 MCCSL allows the microcontroller to read from or write to the TCM4300. MCCSL Microcontroller interface chip-select. A low at MCCSL in conjunction with a high at the MCCSH allows the microcontroller to read from or write to the TCM4300. MCD0 I/O/Z Microcontroller 8-bit parallel data bus.
  • Page 14 RSSI Received signal strength indicator. RSSI samples received signal strength. RSOUTH Reset out high. An active high is output from RSOUTH for 10 ms after the TCM4300 is powered up. RSOUTL Reset out low. An active low is output from RSOUTL for 10 ms after the TCM4300 is powered up.
  • Page 15 Terminal Functions (Continued) TERMINAL NAME SCEN Speech CODEC enable. A high out from SCEN can enable the speech CODEC. SINT Sample interrupt. SINT is active low. In the analog mode, SINT occurs at 40 kHz; in the digital mode, SINT occurs at 48.6 kHz. SYNCLK Synthesizer clock.

  • Page 16: Electrical Specifications

    2 Electrical Specifications This section lists the electrical specifications, the absolute maximum ratings, the recommended operating conditions and operating characteristics for the TCM4300 Advanced RF Cellular Telephone Interface Circuit. Absolute Maximum Ratings Over Operating Free-Air Temperature Range † (unless otherwise noted)

  • Page 17: Recommended Operating Conditions

    Recommended Operating Conditions Supply voltage, DV DD High-level input voltage, V IH Low-level input voltage, V IL High-level output voltage, V OH Low-level output voltage, V OL High-level output current at 3 V, I OH Low-level output current at 3 V, I OL High-level output current at 5 V, I OH Low-level output current at 5 V, I OL Load capacitance, transmit I and Q channel outputs...

  • Page 18: Terminal Impedance

    2.4.3 Terminal Impedance FUNCTION Receive channel input impedance (single ended), RXIP/N and RXQP/N Transmit channel output impedance (single ended), TXIP/N and TXQP/N FM input impedance, WBD MCLKOUT at 3.3 V MCLKOUT impedance MCLKOUT impedance MCLKOUT at 5 V † All typical values are at DV DD = 5 V, AV DD = 5 V, and T A = 25 C, unless otherwise specified. 2.4.4 RXIP, RXIN, RXQP, and RXQN Inputs (AV PARAMETER...

  • Page 19: Transmit I And Q Channel Outputs

    2.4.5 Transmit I and Q Channel Outputs PARAMETER Peak output voltage full scale centered at VCM Peak output voltage full scale, centered at VCM Nominal output-level (constellation radius) centered Nominal output level (constellation radius) centered at VCM Low-level drift Transmit error vector magnitude (EVM) Resolution S/(N+D) ratio at differential outputs Gain error (I or Q channel)

  • Page 20: Auxiliary D /A Converters Slope (Agc, Afc, Pwrcont)

    2.4.7 Auxiliary D /A Converters Slope (AGC, AFC, PWRCONT) NOMINAL LSB AUXFS[1:0] SLOPE VALUE SETTING 2.5/256 0.0098 Do not use Do not use 4/256 0.0156 4.5/256 0.0176 † The maximum input code is 255. The value shown for 256 is extrapolated. 2.4.8 Auxiliary D /A Converters Slope (LCDCONTR) NOMINAL LSB...

  • Page 21: Operating Characteristics Over Full Range Of Operating Conditions

    Operating Characteristics Over Full Range of Operating Conditions (Unless Otherwise Noted) 2.5.1 Receive (RX) Channel Frequency Response (RXI, RXQ Input in Digital Mode) PARAMETER TEST CONDITIONS 0.125 V peak-to-peak, 0.125 V peak-to-peak, 0.125 V peak-to-peak, Frequency response 0.125 V peak-to-peak, 0.125 V peak-to-peak, 0.125 V peak-to-peak, Peak-to-peak...

  • Page 22: Transmit (Tx) Channel Frequency Response (Analog Mode)

    2.5.4 Transmit (TX) Channel Frequency Response (Analog Mode) PARAMETER TEST CONDITIONS 0 kHz to 8 kHz (see Note 4) 8 kHz to 15 kHz (see Note 4) 20 kHz to 45 kHz (see Note 5) Frequency response Frequency response 45 kHz to 75 kHz (see Note 5) >...
  • Page 23 2–8...

  • Page 24: Parameter Measurement Information

    This section contains the timing waveforms and parameter values for MCLKOUT and several microcontroller interface configurations possible when using the TCM4300. The timing parameters are contained in Section 3.1 through Section 3.11. The timing waveforms are shown in Figures 3–1 through 3–11.

  • Page 25: Tcm4300 To Microcontroller Interface Timing Requirements

    MCD t inv Data MCD invalid after rising edge of strobe MCDS Disable time, read data. TCM4300 releases MCD data bus t dis(RD) after rising edge of strobe MCDS Hold time, chip select MCCSH and MCCSL stable before...

  • Page 26: Tcm4300 To Microcontroller Interface Timing Requirements

    TCM4300 to Microcontroller Interface Timing Requirements (Mitsubishi Write Cycle) (see Figure 3–3 and Note 2) PARAMETER Setup time, read/write MCRW stable before falling edge of t su(R/W) strobe MCDS Hold time, read/write MCRW stable after rising edge of t h(R/W)
  • Page 27 MCD t inv Data MCD invalid after rising edge of strobe MCDS Disable time, read data. TCM4300 releases MCD data bus t dis(RD) after rising edge of strobe MCDS Setup time, chip select MCCSH and MCCSL stable before...

  • Page 28: Tcm4300 To Microcontroller Interface Timing Requirements (Intel Write Cycle))

    TCM4300 to Microcontroller Interface Timing Requirements (Intel Write Cycle) (see Figure 3–5 and Note 3) PARAMETER Setup time, write address MCA stable before falling edge t su(WA) of strobe MCRW Hold time, write address MCA stable after rising edge of...
  • Page 29 MCD t inv Data (MCD) invalid after rising edge of strobe MCDS Disable time, read data. TCM4300 releases MCD data bus t dis(RD) after rising edge of strobe MCDS Hold time, chip select MCCSH and MCCSL stable before...

  • Page 30: Tcm4300 To Microcontroller Interface Timing Requirements (Motorola 16-Bit Read Cycle)

    TCM4300 to Microcontroller Interface Timing Requirements (Motorola 16-Bit Write Cycle) (see Figure 3–7 and Note 4) PARAMETER Setup time, read/write MCRW stable before falling edge of t su(R/W) strobe MCDS Hold time, read/write MCRW stable after rising edge of t h(R/W)
  • Page 31 MCD t inv Data MCD invalid after falling edge of strobe MCDS Disable time, read data. TCM4300 releases MDS data bus t dis(RD) after falling edge of strobe MCDS Hold time, chip select MCCSH and MCCSL stable before...

  • Page 32: Tcm4300 To Microcontroller Interface Timing Requirements (Motorola 8-Bit Read Cycle)

    TCM4300 to Microcontroller Interface Timing Requirements (Motorola 8-Bit Write Cycle) (see Figure 3–9 and Note 5) PARAMETER Setup time, read/write MCRW stable before rising edge of t su(R/W) strobe MCDS Hold time, read/write MCRW stable after falling edge of t h(R/W)

  • Page 33: Tcm4300 To Dsp Interface (Read Cycle)

    3.10 Switching Characteristics, TCM4300 to DSP Interface (Read Cycle) (see Figure 3–10) PARAMETER Setup time, read/write DSPRW stable before falling edge of t su(R/W) strobe DSPSTRBL Hold time, read/write DSPRW stable after rising edge of t h(R/W) strobe DSPSTRBL Setup time, chip select stable DSPCSL before falling edge...

  • Page 34: Tcm4300 To Dsp Interface (Write Cycle)

    3.11 Switching Characteristics, TCM4300 to DSP Interface (Write Cycle) (see Figure 3–11) PARAMETER Setup time, read/write DSPRW stable before falling edge of t su(R/W) strobe DSPSTRBL Hold time, read/write DSPRW stable after rising edge of t h(R/W) strobe DSPSTRBL Setup time, chip select stable DSPCSL before falling edge...
  • Page 35 3–12...

  • Page 36: Principles Of Operation

    4 Principles of Operation This section describes the operation of the TCM4300 in detail. Timing diagrams and associated tables are contained in Section 3 of this data manual. Data Transfer The interface to both the system digital signal processor and microcontroller is in the form of 2s complement.
  • Page 37 Table 4–2. RXIP, RXIN, RXQP, and RXQN Inputs (AV PARAMETER Input voltage range Differential Input voltage for full- scale Input voltage for full scale digital output Single ended Differential Nominal operating level Nominal operating level Single ended Input CMRR (RXI, RXQ) Sampling frequency, SINT (digital mode) Sampling frequency, SINT (analog mode) Receive error vector magnitude (EVM)

  • Page 38: Receive (Rx) Channel Frequency Response (Rxi, Rxq Input In Digital Mode)

    In the digital mode (MODE = 1), the data is written to the TXI register using the SINT interrupt to synchronize the data transfer. The TCM4300 performs parallel-to-serial conversion of the bits in the TXI register and encodes the resulting bit stream as /4 DQPSK data samples. These samples are then filtered by a digital...

  • Page 39: Transmit (Tx) I And Q Channel Outputs

    (RC) filter. The TCM4300 generates a power amplifier (PA) control signal, PAEN, to enable the power supply for the PA. The start and stop times of the TDM burst are controlled by writing to a single bit, TXGO, in the DSP DStatCtrl register.

  • Page 40: Transmit (Tx) Channel Frequency Response (Analog Mode)

    Transmit Burst Operation (Digital Mode) In the digital mode, the TCM4300 performs all encoding, signal processing, and power ramping for the burst. Start and stop timing of the variable length bursts are set by means of the TXGO bit in the DStatCtrl register.

  • Page 41: Power Ramp-Up/Ramp-Down Timing Diagram

    delay after the last symbol occurs (2 SINT periods before TXGO goes low); then the transmit outputs decay to zero differential voltage (each output at the voltage supplied to the VCM input terminal). The shape of the decay is the transient resulting from the internal SQRC filtering. The transmit outputs are held at zero differential voltage 6 SINT periods (3 symbol periods) after the start of the decay.

  • Page 42: Transmit I And Q Output Level

    Figure 4–2. Transmit Power Ramp-Up/Ramp-Down Functional Diagram Transmit I And Q Output Level In the digital mode, the output level at TXI and TXQ is controlled by the TCM4300. During the burst, but not including ramp-up or ramp-down periods, the average output level (I specified value.

  • Page 43: Wide-Band Data Interrupts

    Table 4–8. Typical Bit-Error-Rate Performance (WBD_BW = 000) TEST CONDITIONS PARAMETER PARAMETER Bit error rate The WBDD is controlled by the bits in the control register WBDCtrl (see Table 4–9). Table 4–9. Bits in Control Register WBDCtrl NAME BIT CODE WBD_LCKD —...

  • Page 44: Wide-Band Data Demodulator General Information

    At the same time, the interrupts DWBDINT and MWBDFINT are asserted. The interrupt rate is 800 s (8 bits/10 kHz). These interrupts are individually cleared when the WBD register is read by the corresponding processor. They can also be cleared by their respective processor by writing a 1 to the corresponding clear WBD bit.

  • Page 45: Auxiliary D /A Converters Slope (Agc, Afc, Pwrcont)

    The AFC, AGC, and PWRCONT DACs are disabled after powerup or after a reset of the TCM4300. After power up or reset, the default AUXFS[1:0] is 00. When the DACs are powered down, their output terminals go to a high-impedance state and can tolerate any voltage present on the terminal that falls within the supply range.

  • Page 46: Rssi/Battery A/D Converter

    Auxiliary DACs, LCD Contrast Converter (continued) Table 4–12. Auxiliary D /A Converters Slope (LCDCONTR) NOMINAL LSB AUXFS[1:0] SLOPE VALUE SETTING 2.5/16 0.1563 Do not use Do not use 4/16 0.2500 4.5/16 0.2813 † The maximum input code is 15. The value shown for 16 is extrapolated. 4.10 RSSI, Battery Monitor The received signal strength indicator (RSSI) and battery (BAT) strength monitor share a common register.

  • Page 47: Clock Generation

    CSCLK is exactly CMCLK divided by 256 (see Figure 4–4). To save power, the codec clocks are only generated by TCM4300 when the SCEN bit of the DStatCtrl register is set high. When SCEN is low, both outputs, CSCLK and CMCLK, are held low. SCEN is also available as an output.

  • Page 48: Phase-Adjustment Strategy

    The number of cycles altered is controlled by internal counters. In the TCM4300 there are two clocks which must be adjusted: CMCLK and an internal 9.72-MHz clock from which SINT is derived. Each of these clocks has an associated counter that counts the number of cycles that have been lengthened or shortened by one MCLKIN period each and thus detects when the total adjustment is complete.

  • Page 49: Timing And Clock Generation For 38.88-Mhz Clock

    17, 18, 19, 20 Adjust Counter B From DSP Adjust Counter A 38.88 MHz MCLKIN 3, 4, 5 Analog/Digital Mode (MODE bit) Clock Divider Chain From Micro- controller N = (2, 3, . . . 32) MCLKEN Figure 4–5. Timing and Clock Generation for 38.88-MHz Clock 4–14 2.048-MHz Codec Master Clock CMCLK Bits 0 –...

  • Page 50: Frequency Synthesizer Interface

    4.12 Frequency Synthesizer Interface The synthesizer interface provides a means of programming three synthesizers. The synthesizer-side outputs are a data line, a clock line, and three latch enable lines that separately strobe data into each synthesizer. The control inputs are registers mapped into the microcontroller address space. The status of the interface can be monitored to determine when the programming operation has been completed.

  • Page 51: Synthesizer Interface Circuit Block Diagram

    Ready Timing Logic SYNDTA SYNLE0 SEL 0 SYNLE1 SEL 1 SYNLE2 SEL 2 CLKPOL Clock SYNCLK Circuit Figure 4–6. Synthesizer Interface Circuit Block Diagram 4–16 CLKPOL NUMCLKS Control LOWVAL Registers HIGHVAL SEL[2:0] MSB/LSB FIRST SYNRDY To MStatCtrl Register 32-Bit Data Register DMUX HIGHVAL...

  • Page 52: Contents Of Syndata Registers

    The SynData0 register contains the least significant bits of the 32-bit data register. SynData3 contains the most significant bits. The bits in the SynCtrl0, SynCtrl1, and SynCtrl2 registers are allocated as shown in Figure 4–7. 7 – 5 SynCtrl0 SynCtrl0 SEL[2:0] 7 –...

  • Page 53: Power Control Port

    For systems requiring minimum system current consumption, power can be provided to each functional part of the TCM4300 only when that function is required for proper system operation. To accomplish this, the TCM4300 provides six external power control signals accessible through the DStatCtrl and MStatCtrl registers.

  • Page 54: Internal And External Power Control Logic

    In addition to allowing control of power to external functional modules, these power control bits combined with other control bits are used to control internal TCM4300 functions. This control system is shown in Figure 4–9. WBD_ON Ctrl FMRXEN MIntCtrl SCEN...

  • Page 55: Microcontroller-Dsp Communications

    In the analog mode, (MODE bit set low), PAEN is high whenever TXEN is active and SYNOL is low. The SYNOL input can be used as an indication to the TCM4300 that the external synthesizers are out of lock. The PAEN signal is gated by SYNOL to prevent off-channel transmissions.
  • Page 56 4.15 Microcontroller Register Map The microcontroller can access 17 locations within the TCM4300. The register locations are 8 bits wide as shown in Table 4–16 and Table 4–17. Table 4–16. Microcontroller Register Map ADDR NAME WBDCtrl WBD_LCKD WBD_ON FIFO FIFO A(B) Microcontroller to DSP (DSP to microcontroller)

  • Page 57: Wide-Band Data/Control Register

    Table 4–17. Microcontroller Register Definitions ADDR NAME WBDCtrl Wide-band data Wide-band data FIFO FIFO A(B) microcontroller to DSP (DSP to microcontroller) MIntCtrl Interrupt/control status SynData0 SynData1 SynData2 SynData3 Synthesizer interface SynCtrl0 SynCtrl1 SynCtrl2 MCClock Microcontroller clock speed RSSI A/D RSSI level BAT A/D Battery level monitor LCD D/A...

  • Page 58: Microcontroller Status And Control Registers

    Table 4–18. WBDCtrl Register R / W NAME Wide-band data lock data. WBD_LCKD determines whether edge R / W WBD_LCKD detector is locked (1) or unlocked (0). R / W WBD_ON Wide-band data on. WBD_ON turns the WBDD module on/off (1/0). 7 –...

  • Page 59: Mstatctrl Register Bits

    Table 4–19. MStatCtrl Register Bits R / W NAME Synthesizer out of lock. SYNOL is equal to the level applied to SYNOL input pin. SYNOL can be used as an input for an externally generated SYNOL status signal to prevent transmission when external synthesizers are out of lock.

  • Page 60: Dsp Register Map

    The register map accessible to the DSP port is shown in Table 4–20 and Table 4–21. There are 14 system addressable locations. Note that the write address of FIFO B is the same as the read address of FIFO A. Figure 4-11 details the connection of TCM4300 to an example DSP. Table 4–20. DSP Register Map...

  • Page 61: Wide-Band Data Registers

    BST OFFSET values are 00, 01, 10, and 11, which correspond to an offset value d of 0, 1, 2, and 3 respectively as shown below. BST OFFSET BST OFFSET The delay in the TCM4300 TX channels is increased by the amount: SINT BST OFFSET 4–26...

  • Page 62: Dsp Status And Control Registers

    4.22 DSP Status and Control Registers DIntCtrl, Clear and Send Bits: The bit names in the DIntCtrl register indicate the action to be taken when a 1 is written to the respective bit. When these bits are being read, a 1 indicates that the corresponding interrupt is pending.

  • Page 63: Power-On Reset Register Initialization

    4.23 Reset A low on RSINL causes the TCM4300 internal registers to assume their reset values. The power-on reset circuit also causes internal reset. However, the logic level at RSINL has no effect on reset outputs RSOUTH and RSOUTL. The effects of resetting the TCM4300 are described in the following paragraphs.

  • Page 64: Microcontroller Interface Connections For Intel Mode

    4.24 Microcontroller Interface The microcontroller interface of the TCM4300 is a general purpose bus interface (see Table 4–24) which ensures compatibility with a wide range of microcontrollers, including the Mitsubshi M37700 series and most Intel and Motorola series. The interface consists of a pair of microcontroller type select inputs MTS1 and MTS0, address and data buses, as well as several input and output control signals that are designed to operate in a manner compatible with the microcontroller selected by the user.

  • Page 65: Mitsubishi Microcontroller Mode Of Operation

    (R/ W) signal and active-low interrupt request signals. The processor E (8-bit) or DS (16-bit) and (R/ W) control signals should be connected to the TCM4300 MCDS signal and the MCRW signal, respectively. Table 4–27 illustrates the connections between the TCM4300 and an 8-bit Motorola processor.

  • Page 66: Microcontroller Interface Connections For Motorola Mode (16 Bits)

    Table 4–28. Microcontroller Interface Connections for Motorola Mode (16 bits) TCM4300 TERMINAL MTS1, MTS0 Tie to logic levels: high and low, respectively MCCSH Not on microcontroller; can be used for address decoding MCCSL Not on microcontroller (68000, 68008) CS1, CS2, or CS3 (68302) MCD7–MCD0...
  • Page 67 4–32...

  • Page 68: Mechanical Data

    5 Mechanical Data PZ (S-PQFP-G100) 0,50 12,00 TYP 14,20 13,80 16,20 15,80 1,45 1,35 1,60 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136 PLASTIC QUAD FLATPACK 0,27 0,08 0,17...
  • Page 69 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current.

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