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DISP:
1500
0µS
100
nDISP:
600
0µS
DISP: 40 KHz
nDISP: 100 KHz
Ø
Øp lags Ø by
approx. 1µS
Øp
DISP: 10 KHz
nDISP: 25 KHz
ØB1
ØB8
ØB1p
DISP: 625 Hz
nDISP: 1563 Hz
ØD0
ØD1
ØD15
ØnD0•Ø
ØD0•B2
OP•ØD0•B1p
n(OP•ØD0•B2p)
OP•ØD0•B4p
nOP•ØD14p
with
00000987654321.
X
in the display.
ØD n
15
0
Digit held in display latch
after ØB1p
14
–
registers
idle
Facit 1123 Calculator
Section: Timing Diagram
Page: 13
Rendition: 2014 Mar 6
200
300
400
500
40
80
120
160
200
1
2
3
4
–
1
2
3
Clock Rates (as measured)
DISP=1 (displaying): 43KHz, 23µS
DISP=0 (calculating): 111KHz, 9µS
600
700
800
900
240
280
320
360
5
6
7
8
9
4
5
6
7
8
one full number cycle
in registers
1000
1100
1200
1300
1400
400
440
480
520
560
10
11
12
13
9
10
11
12
1500
1600
600
640 / 0µS
14
15
0
13
14
–
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