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Arithmetic Display Latch & Display Power Supply Timing Diagram IC Pinouts & Physical Layout Connectors Facit 1123 Calculator This schematic has been derived through reverse engineering. Section: Title and Contents This is not the manufacter’s schematic, nor Page: 1 Rendition: 2020 Oct 9...
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F is used to indicate where arithmetic will begin during the number cycle. ♦ During multiply and divide, the uppermost digit of the Y register is used as a digit counter to limit the multiply/divide Facit 1123 Calculator loop.
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Digit held in display latch after ØB1p – – – registers idle one full number cycle in registers Facit 1123 Calculator Clock Rates (as measured) DISP=1 (displaying): 43KHz, 23µS Section: Timing Diagram DISP=0 (calculating): 111KHz, 9µS Page: 13 Rendition: 2020 Oct 9...
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M5340 ♦ M5962s are reversed in their orientation on the board b 6 c relative to all other ICs. b 7 c Facit 1123 Calculator b 8 c N b 71 N b 72 Section: IC Pinouts & Physical Layout...
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GND 71 72 DP>6 16 — 45 nØD0 • Italicised expressions are connections with no signal name in the schematic. Facit 1123 Calculator • Bold-faced expressions are signal sources. • See preceding page for connector orientation. Section: Connectors Page: 15...