Philips 32PFL5604H/12 Service Manual page 45
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Also See for 32PFL5604H/12:
- User manual (54 pages) ,
- Quick start manual (12 pages) ,
- Brochure (3 pages)
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7.6.3
Connectivity and Compute Subsystem
Refer to
Figure 7-12
for the connectivity and compute
subsystem.
I2C-1
I2C-2
I2C-3
UART-1
UART-2
USB
EJTAG
The Connectivity Subsystem consists of:
•
PCI/XIO interface
•
USB2.0 interface
•
Three 2-wire UARTs
•
Four Master/Slave I
•
Common Interface/Conditional Access Interface.
The Computing Subsystem consists of:
•
32-bit MIPS RISC core
•
Enhanced JTAG (EJTAG) block inside the MIPS
•
JTAG_MMIO blocks
•
TV controller
•
Audio/Video DSP (AV_DSP)
•
Memory Control Unit (MCU).
PNX8543x
IIC4_DMA
IIC2_DMA
IIC3_DMA
UART1
UART2
USB2.0
JTAG_MMIO
Figure 7-12 PNX8543 connectivity and compute subsystem
2
C interfaces
Circuit Descriptions
DDR2-SDRAM
MCU_DDR
MIPS
4KEc
EJTAG
PCI_XIO
CAI
SYSTEM
CONTROLLER
80C51
7.6.4
Service Notice - FLASH RAM / PNX8543 exchange
The FLASH RAM (item 7M00) and/or PNX8543 (item 7600)
can only be exchanged by an authorised central workshop with
dedicated programming tools. Due to the presence of (CI+)
keys in the components, unauthorised exchange of these
components will always result in a defective board.
Q543.3E LA
7.
AVDSP
PCI/XIO
CI/CA
I2C-MC
UART-3
PWMs
GPIOs
18440_205_090226.eps
EN 45
090819
2010-Jun-29
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