Sram Ddr2 Core (Sram_Ddr2_Core) - Annapolis Micro Systems Wildstar-II Series Hardware Reference Manual

Table 7-3: SRAM Basic I/O Signal Mapping
Signal Name Width
User_Out.Addr
User_Out.Data_Out
User_Out.Data_OE_n
User_Out.BW_n
User_Out.Load_n
User_Out.WE_n
User_Out.Clk
User_Out.Clk_n
User_In.Data_In
User_In.Clk_In
User_In.Addr_In
User_In.WE_In_n
User_In.Load_In_n
*
Note: SA[0] is always grounded.

7.2.4 SRAM DDR2 Core (SRAM_DDR2_Core)

The SRAM DDR2 core is designed to provide a high-level interface to the SRAM
memories. The SRAM_Basic_IO is included inside the core, so it is not
necessary to include this elsewhere. The SRAM DDR2 core supports the
following SRAM memories:
• Micron® 18 Mb DDRII CIO 2 word burst (MT57W512H36B)
• NEC® 18 Mb DDRII CIO 2 word burst (UPD44164362)
• Samsung® 18 Mb DDRII CIO 2 word burst (K7I163682B-FC20)
WILDSTAR ™ -II Hardware Reference Manual
Annapolis Micro Systems, Inc.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
Dir Description
20 Input Address Bus
36 Input Data Bus Output
36 Input Data Bus Output Enable
4 Input Byte Write Enable
2 Input
1 Input Write Enable
1 Input
1 Input
36 Output Data Bus Input
1 Output Clock Input
(Input Buffer on
User_out.Clk pad)
20 Output Addr Input
(Input Buffer on
User_Out.Addr pad)
1 Output Write Enable Input
(Input Buffer on
User_Out.WE_n pad)
2 Output Load Input
(Input Buffer on
User_Out.Load_n pad)
Doc No. 12921-0000 Rev. 6.0
Datasheet Name
SA[1:14]
Load 0=LD#, chip 1
1=LD#,chip 2 (if present)
Clock
Clock
*
DQ_
NA
BW_#
R/W#
K
K#
DQ_
NA
NA
NA
NA
Page 7-17