Panasonic SA-AK22 Service Manual page 26

SA-AK22
Pin No. Mark
52 EFM -
53 PCK -
54 VCOF2 I/O
55 SUBC O
56 SBCK I
57 VSS I
58 X1 IN I
59 X2 OUT O
60 VDD I
61 BYTCK -
62 /CLDCK -
63 FCLK -
64 IPFLAG -
65 FLAG -
14.3. IC703 (AN8739SBE2) Focus coil/ Tracking coil/ Traverse motor/
Spindle motor driver
Pin No. Mark I/O
1 /RST -
2 NC -
3 IN2 I
4 PC2 I
5 NC -
6 IN1 I
7 NC I
8 PVCC1 I
9 PGND1 -
10 NC -
11 D1- O
12 D1+ O
13 D2- O
14 D2+ O
14.4. IC600 (M38B79MFA053) System Microprocessor
Pin No. Mark
1 DECK2
2 KEY3
3 KEY2
4 KEY1
5 V_JOG_AD
6 J_JOG_AD
7 CHG_AD1
8 CHG_AD2
I/O Function
EFM signal output
PLL extraction clock output
(fPCK = 4.321 MHz during
normal playback)
VCO Loop filter for 33.8688
MHz conversation terminal for
16.9344 MHz crystal mode,
must use other circuit
Sub-code serial data output
Clock input for sub-code
serial data
GND
Crystal oscillating circuit input
(f = 16.9344MHz)
Crystal oscillating circuit input
(f = 16.9344 MHz)
Power supply input (for
oscillating circuit)
Byte clock output
Sub-code frame clock signal
output (fCLDCK = 7.35 kHz
during normal playback)
Crystal frame clock signal
output (fCLK = 7.35 kHz,
double = 14.7 kHz)
Interpolation flag output ("H" :
Interpolation)
Flag output
Function
RESET output terminal
N.C.
Motor Drive (2) input
Turntable motor drive signal ("L
:ON)
N.C.
Motor driver (1) input
N.C.
Power supply (1) for driver
Ground connection (1) for driver
N.C.
Motor driver (1) reverse-action
output
Motor driver (1) forward-action
output
Motor driver (2) reverse-action
output
Motor driver (2) forward-action
output
I/O Function
I Tape mecha condition input
(Half2/Reci_F/Mode/Reci_R)
I Key 3 input
I Key 2 input
I Key 1 input
I Volume jog A-D detection
input
I EQ Joy jog A-D detection
input
I (Open Clamp) Chngr sw A-D
detection input 1
I (Position/ bottom) Chngr sw
A-D detection input 2
Pin No. Mark I/O
66 CLVS -
67 CRC -
68 DEMPH -
69 RESY -
70 IOSEL I
71 /TEST I
72 AVDD1 I
73 OUTL O
74 AVSS1 I
75 OUTR O
76 RSEL I
77 IOVDD I
78 PSEL I
79 MSEL I
80 SSEL I
Pin No. Mark I/O
15 D3- O Motor
output
16 D3+ O Motor
output
17 D4- O Motor
output
18 D4+ O Motor
output
19 NC - N.C.
20 PGND2 - Ground connection (2) for driver
21 PVCC2 I Power supply (2) for driver
22 NC - N.C.
23 VCC I Power supply terminal
24 VREF I Reference voltage input
25 IN4 I Motor driver (4) input
26 IN3 I Motor driver (3) input
27 RSTIN I Reset terminal
28 NC - N.C.
Pin No. Mark
9 CDRST O
10 STATUS I
11 SPE I
12 ST/DO/SQC I/O
K
13 SD I/O
14 SUBQ I
15 RDS_CL I
16 RDS_DA I
17 CNVSS -
18 /RESET -
26
Function
Spindle servo phase
synchronizing signal output
("H" : CLV, "L" : rough servo)
Sub-code CRC checked
output ("H' :OK, "L" :NG)
De-emphassis ON signal
output ("H" :ON)
Frame re-synchronizing signal
output
Mode Switching Terminal
Test input
Power supply input (for
analog circuit)
Left channel audio signal
output
GND
Right channel audio signal
output
RF signal polarity assignment
input (at "H" level, RSEL="H",
at "L" level, RESL="L")
5V supply input
Test terminal (connected to
Gnd)
SMCK oscillating frequency
designation input ("L":4.2336
MHz, "H":8.4672 MHz)
SUBQ output mode select
("H":Q-code buffer mode)
Function
driver (3) reverse-action
driver (3) forward-action
driver (4) reverse-action
driver (4) forward-action
I/O Function
CD reset output
CD signal processor status
input (INV)
Speana input
Tuner if data/stereo input and
CD subcode clock output
Tuner signal detect input
CD subcode data input (INV)
RDS clock input
RDS data input
Flash mode terminal
(connect to ground)
RESET input