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Viov; Vio + 0.3 - ON Semiconductor NCV7341 Manual

High speed low power can transceiver

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Definitions
All voltages are referenced to GND (Pin 2). Positive
currents flow into the IC. Sinking current means the current
is flowing into the pin; sourcing current means the current
is flowing out of the pin.
Table 5. ABSOLUTE MAXIMUM RATINGS
Symbol
V
Supply voltage
BAT
V
Supply voltage
CC
V
Supply voltage
IO
V
DC voltage at pin CANH
CANH
V
DC voltage at pin CANL
CANL
V
−V
DC voltage between bus pins CANH and CANL
CANL
CANH
V
DC voltage at pin VSPLIT
SPLIT
V
DC voltage at pin INH
INH
V
DC voltage at pin WAKE
WAKE
V
DC voltage at pin TxD
TxD
V
DC voltage at pin RxD
RxD
V
DC voltage at pin STB
STB
V
DC voltage at pin EN
EN
V
DC voltage at pin ERR
ERR
V
Transient voltage at pin CANH
tran(CANH)
V
Transient voltage at pin CANL
tran(CANL)
V
Transient voltage at pin VSPLIT
tran(VSPLIT)
V
Electrostatic discharge voltage at pins intended to be
esd(CANL/CANH/
wired outside of the module
VSPLIT, VBAT, WAKE)
(CANH, CANL, V
V
Electrostatic discharge voltage at all other pins
esd
Latch−up
Static latch−up at all pins
T
Storage temperature
stg
T
Ambient temperature
amb
T
Maximum junction temperature
junc
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Applied transient waveforms in accordance with ISO 7637 part 3, test pulses 1, 2, 3a, and 3b (see Figure 9).
2. Standardized human body model electrostatic discharge (ESD) pulses in accordance to MIL883 method 3015.7.
3. Static latch-up immunity: Static latch-up protection level when tested according to EIA/JESD78.
4. Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3-1993.
NCV7341
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
cause permanent device failure. Exposure to absolute
maximum ratings for extended periods may affect device
reliability.
Parameter
, VBAT, WAKE)
SPLIT
http://onsemi.com
10
Stresses above those listed in the following table may
Conditions
0 < V
< 5.25 V;
CC
no time limit
0 < V
< 5.25 V;
CC
no time limit
0 < V
< 5.25 V;
CC
no time limit
0 < V
< 5.25 V;
CC
no time limit
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 4)
(Note 2)
(Note 4)
(Note 3)
Min.
Max.
Unit
−0.3
58
V
−0.3
+7
V
−0.3
+7
V
−58
+58
V
−58
+58
V
−58
+58
V
−58
+58
V
−0.3
VBAT+0.3
V
−0.3
58
V
−0.3
7
V
−0.3
V
+ 0.3
V
IO
−0.3
7
V
−0.3
7
V
−0.3
V
+ 0.3
V
IO
−300
+300
V
−300
+300
V
−300
+300
V
−4
4
kV
−500
500
V
−3
3
kV
−500
500
V
120
mA
−50
+150
°C
−50
+125
°C
−50
+180
°C

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