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Quectel L50 Hardware Design

Quectel L50 Hardware Design

Gps engine
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L50 Hardware Design
L50
Quectel GPS Engine
Hardware Design
L50_HD_V1.0

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Summary of Contents for Quectel L50

  • Page 1 L50 Hardware Design Quectel GPS Engine Hardware Design L50_HD_V1.0...
  • Page 2 Furthermore, system validation of this product designed by Quectel within a larger electronic system remains the responsibility of the customer or the customer’s system integrator. All specifications supplied herein are subject to change.

  • Page 3: Table Of Contents

    L50 Hardware Design Contents Contents ............................2 Table Index ............................4 Figure Index ............................5 0. Revision History ........................... 6 1. Introduction ........................... 7 1.1 Related Documents ......................... 7 1.2 Terms and Abbreviations ......................7 2. Product Concept ..........................9 2.1 Key Features ..........................
  • Page 4 L50 Hardware Design 7. Manufacturing ..........................36 7.1 Assembly and Soldering ......................36 7.2 Moisture Sensitivity ......................36 7.3 ESD Safe ..........................37 7.4 Tape and Reel ........................37 L50_HD_V1.0 -3 -...
  • Page 5 TABLE 10: RECOMMENDED EEPROMS ..................25 TABLE 11: PIN DEFINITION OF THE DR_I2C INTERFACES ............25 TABLE 12: ANTENNA SPECIFICATION FOR L50 MODULE ............27 TABLE 14: RECOMMENDED OPERATING CONDITIONS ............. 30 TABLE 15: THE MODULE CURRENT CONSUMPTION ..............31 TABLE 16: THE ESD ENDURANCE TABLE (TEMPERATURE: 25°...
  • Page 6 FIGURE 2: ATP TIMING SEQUENCE ....................17 FIGURE 3: PTF TIMING SEQUENCE ....................18 FIGURE 4: POWER DESIGN REFERENCE FOR L50 MODULE ............. 19 FIGURE 5: REFERENCE CHARGING CIRCUIT FOR CHARGEABLE BATTERY ....... 19 FIGURE 6: SEIKO XH414 CHARGING AND DISCHARGING CHARACTERISTICS ....20 FIGURE 7: TURN ON TIMING SEQUENCE OF MODULE ..............

  • Page 7: Revision History

    L50 Hardware Design 0. Revision History Revision Date Author Description of change 2011-07-25 Baly BAO/Harry LIU Initial L50_HD_V1.0 -6 -...

  • Page 8: Introduction

    L50 Hardware Design 1. Introduction This document defines and specifies L50 GPS module. It describes L50 hardware interface and its external application reference circuits, mechanical size and air interface. This document can help customer quickly understand module interface specifications, electrical and mechanical characteristics.
  • Page 9 L50 Hardware Design One Socket Protocol PDOP Position Dilution of Precision Recommended Minimum Specific GNSS Data SBAS Satellite-based Augmentation System SUPL Secure User Plane Location Surface Acoustic Wave To Be Determined TTFF Time-To-First-Fix UART Universal Asynchronous Receiver & Transmitter VDOP...

  • Page 10: Product Concept

    This will reduce customers’ design complexity greatly.  L50, in SMD type, can be embedded in customer applications via the 24-pin pads with the slim 16 x 28 x 3mm package. It provides all hardware interfaces between the module and host board.
  • Page 11 L50 Hardware Design  Accuracy of 1PPS Signal Typical accuracy 61 ns  Time pulse 200ms  Velocity Accuracy Without aid 0.01 m/s  Acceleration Accuracy Without aid 0.1 m/s²  Dynamic Performance Maximum altitude 18288m  Maximum velocity 514m/s ...

  • Page 12: Functional Diagram

    Figure 1: Functional diagram for L50 2.3 Evaluation Board In order to help customers to develop applications with L50, Quectel offers an Evaluation Board (EVB) with appropriate power supply, RS-232 serial port and EEPROM. Note: For more details, please refer to the document [1].

  • Page 13: Application

    L50 Hardware Design 3. Application L50 is a 24-pin surface mounted device (SMD) which could be embedded into customers’ application conveniently. Sub-interfaces included in these pins are described in detail in the following chapters:  Power management (refer to Chapter 3.4) ...

  • Page 14: Pin Description

    L50 Hardware Design 3.2 Pin Description Table 5: Pin description Power Supply DESCRIPTIO COMMENT NAME CHARACTERISTICS Supply voltage Vmax= 1.89V Supply current should be Vmin=1.71V no less than 100mA. Vnom=1.8V VIO/RTC RTC and CMOS Vmax=1.89V Power supply for RTC I/O voltage Vmin=1.71V...
  • Page 15 L50 Hardware Design ON_OFF Power control VILmin=-0.4V A pulse generated on the VILmax=0.45V ON_OFF pin which lasts VIHmin=0.7* for at least 1ms and VIO/RTC consists of a rising edge VIHmax=3.6V and low level, can switch operating mode between hibernate and full-on.
  • Page 16 L50 Hardware Design RXD/ Function VOLmax=0.4V MOSI/ overlay: VOHmin=0.75*VCC  SSPI_DI VILmin=-0.4V slave SPI VILmax=0.45V data input VIHmin=0.7*VCC (MOSI) VIHmax=3.6V  UART_RX UART data receive (RXD)  I2C_DIO I2C data (SDA) TXD/ Function VOLmax=0.4V MISO/ overlay: VOHmin=0.75*VCC  SSPI_DO VILmin=-0.4V slave SPI VILmax=0.45V...

  • Page 17: Operating Modes

    1ms on the ON_OFF pin. 3.4 Power Management There are two power supply pins in L50, VCC and VIO/RTC. 3.4.1 VCC Power VCC pin supplies power for GPS BB domain and GPS RF domain. The power supply VCC’s current varies according to the processor load and satellite acquisition.

  • Page 18: Energy Saving Mode

    Figure 2: ATP timing sequence 3.4.3.2 PTF Mode Push to fix (PTF): In this mode, L50 is configured to be waked up periodically, typically every 1800 sec (configurable range 10~7200 sec) for updating position and collecting new ephemeris data from valid satellites.

  • Page 19: Power Supply

    3.5.1 Power Reference Design The following diagram is one solution of power supply for L50 module. Customers can follow this reference design to get a short TTFF in either warm start or cold start. One concern of this design is that the battery will take the place of VCC_3.3 to supply power for RTC and CMOS I/O of the module...

  • Page 20: Battery

    L50 Hardware Design Figure 4: Power design reference for L50 module 3.5.2 Battery In this part, the charging circuit of battery is introduced and XH414 is chosen as an example, the following circuit is the reference design. Figure 5 : Reference charging circuit for chargeable battery Coin-type Rechargeable Capacitor such as XH414H-IV01E from Seiko can be used and Schottky diode such as RB520S30T1G from ON Semiconductor is recommended for its low voltage drop.

  • Page 21: Timing Sequence

    The ON_OFF pin is used to switch the module between full-on mode and hibernate mode. L50 integrates power on reset circuit internally and external RESET signal which belongs to VIO/RTC domain. When VCC and VIO/RTC are supplied simultaneously, the internal power on reset circuit executes.

  • Page 22: Figure 7: Turn On Timing Sequence Of Module

    L50 Hardware Design VIO/RTC >1s >1ms >1ms ON/OFF T>0 400us 35ms (FULL ON) 400us 400ms WAKEUP (Hibernate) (Hibernate) UART Invalid Invalid Valid Figure 7: Turn on timing sequence of module NOTE: If the “ON_OFF” pin is controlled by host controller, a 1KΩ resistor should be inserted between the GPIO of the controller and “ON_OFF”...

  • Page 23: Communication Interface

    I2C clock (SCL) 3.7.1 UART Interface L50 offers multiplexed pins which can be configured as one UART interface and CFG0/SCK should be pulled up to VCC via a 10K resistor. The module is designed as a DCE (Data Communication Equipment). Serial port TXD/MISO/SCL is connected to UART RX of customer’s device, while serial port RXD/MOSI/SDA is connected to UART TX of customer’s device.

  • Page 24: I2C Interface

    Figure 10: RS-232 level shift circuit 3.7.2 I2C Interface L50 provides multiplex function via TXD/MISO/SCL, RXD/MOSI/SDA and CFG1/SCS to construct I2C interface. Communication interface is configured as I2C by pulling CFG1/SCS down via the resistor R1. The default mode is master mode. It is important that the customer must pull up these two pins via 2K resistor for the OC/OD interface.

  • Page 25: Figure 11: I2C Timing Sequence

    L50 Hardware Design This I2C interface has the following features:  Operate up to 400kbps.  Support Multi-master I2C mode by default.  The default I2C master address: 0x60.  The default I2C slave address: 0x62. The following figure is the I2C timing sequence.

  • Page 26: Spi Interface

    The DR_I2C_DIO and DR_I2C_CLK pins are open-drain output and should be pulled up to VDD which depends on the EEPROM’s operation voltage externally by 2K resistors to meet requirement of maximum data rate up to 400Kbs. The following circuit is the reference design for L50 and EEPROM. L50_HD_V1.0...

  • Page 27: Figure 13: Reference Design For Cgee Function

    L50 Hardware Design Figure 13: Reference design for CGEE function L50_HD_V1.0 -26-...

  • Page 28: Radio Frequency

    L50 Hardware Design 4. Radio Frequency L50 receives L1 band signal from GPS satellites at a nominal frequency of 1575.42MHz. It is an ultra slim module with embedded 15 × 15 × 2.0mm patch antenna. Alongside highest reliability and quality of patch antenna, L50 also offers 48 PRN channels, which allows the module to acquire and track satellites in the shortest time, even at a very low signal level.

  • Page 29: Design Notice

    4.2 Design notice Theoretically the best position for L50 module is not only in the center of PCB not also is on the top of the PCB, so the radiation plots won’t be skewed due to the effects of placing it close to the edge of the PCB.

  • Page 30: Figure 15: Evb Of L50

    L50 Hardware Design Figure 15: EVB of L50 L50_HD_V1.0 -29-...

  • Page 31: Electrical, Reliability And Radio Characteristics

    L50 Hardware Design 5. Electrical, Reliability and Radio Characteristics 5.1 Absolute Maximum Ratings Absolute maximum rating for power supply and voltage on digital pins of the module are listed in the following table. Table 13: Absolute maximum ratings Parameter Unit Power supply voltage （VCC）...

  • Page 32: Current Consumption

    Note: Itotal=Ivcc+Ivio/rtc 5.4 Electro-Static Discharge L50 module has better ESD performance, because every pin is protected by a transient voltage suppressor (TVS). However, ESD protection precautions should still be emphasized. Proper ESD handing and packaging procedures must be applied throughout the processing, handing and operation of any application.

  • Page 33: Reliability Test

    L50 Hardware Design 5.5 Reliability Test Table 17: Reliability test Test term Condition Standard Thermal shock -30° C...+80° C, 144 cycles GB/T 2423.22-2002 Test Na IEC 68-2-14 Na Damp heat, cyclic +55° C; >90% Rh 6 cycles for 144 hours...

  • Page 34: Mechanical Dimensions

    L50 Hardware Design 6. Mechanical Dimensions This chapter describes the mechanical dimensions of the module. 6.1 Mechanical Dimensions of the Module Figure 16: L50 Top view and Side view（Unit:mm） Figure 17: L50 Bottom view（Unit:mm） L50_HD_V1.0 -33-...

  • Page 35: Recommended Footprint

    L50 Hardware Design 6.2 Recommended Footprint Figure 18: Recommended Footprint （Unit:mm） L50_HD_V1.0 -34-...

  • Page 36: Top View Of The Module

    L50 Hardware Design 6.3 Top View of the Module Figure 19: Top view of module 6.4 Bottom View of the Module Figure 20: Bottom view of module L50_HD_V1.0 -35-...

  • Page 37: Manufacturing

    7.1 Assembly and Soldering L50 is intended for SMT assembly and soldering in a Pb-free reflow process on the top side of the PCB. It is suggested that the minimum height of solder paste stencil is 130um to ensure sufficient solder volume.

  • Page 38: Esd Safe

    L50 Hardware Design taken that plastic tray is not heat resistant. L50 should be taken out before preheating, otherwise, the tray may be damaged by high-temperature heating. 7.3 ESD Safe L50 module is an ESD sensitive device and should be handled carefully.
  • Page 39 L50 Hardware Design Shanghai Quectel Wireless Solutions Co., Ltd. Room 501, Building 13, No.99 TianZhou Road, Shanghai, China 200233 Tel: +86 21 5108 6236 Mail: info@quectel.com...

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