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Holtek HT66FM5440 Manual

Brushless dc motor a/d flash mcu
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Brushless DC Motor A/D Flash MCU
HT66FM5440
Revision: V1.00
Date: ��ne ��� �01�
��ne ��� �01�

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Summary of Contents for Holtek HT66FM5440

  • Page 1 Brushless DC Motor A/D Flash MCU HT66FM5440 Revision: V1.00 Date: ��ne ��� �01� ��ne ��� �01�...

  • Page 2: Table Of Contents

    HT66FM5440 Brushless DC Motor A/D Flash MCU Table of Contents Features ......................7 CPU Feat�res ......................... � Peripheral Feat�res ......................... � General Description ..................8 Block Diagram ....................9 Pin Assignment ....................9 Pin Description ....................10 Absolute Maximum Ratings ................13 D.C.
  • Page 3 HT66FM5440 Brushless DC Motor A/D Flash MCU Acc�m�lator – ACC ....................... �9 Program Co�nter Low Register – PCL .................. 30 Look-�p Table Registers – TBLP� TBHP� TBLH ..............30 Stat�s Register – STATUS ....................30 Oscillators ...................... 32 Oscillator Overview ....................... 3�...

  • Page 4: Capt�Re Timer Register Description

    HT66FM5440 Brushless DC Motor A/D Flash MCU Capture Timer Module – CAPTM ..............84 Capt�re Timer Overview ....................... �4 Capt�re Timer Register Description ..................�4 Capt�re Timer Operation ....................... �� Noise Filter ..................... 89 Analog to Digital Converter ................. 91 A/D Converter Overview .......................

  • Page 5: Str�Ct

    HT66FM5440 Brushless DC Motor A/D Flash MCU UART Stat�s and Control Registers..................150 Ba�d Rate Generator ......................156 UART Set�p and Control..................... 156 UART Transmitter........................ 15� UART Receiver ........................159 Managing Receiver Errors ....................160 UART Interr�pt Str�ct�re..................... 161 UART Power Down and Wake-�p ..................16�...
  • Page 6 HT66FM5440 Brushless DC Motor A/D Flash MCU Logical and Rotate Operation ..................... 195 Branches and Control Transfer ................... 195 Bit Operations ........................195 Table Read Operations ....................... 195 Other Operations ......................... 195 Instruction Set Summary ................196 Table Conventions ....................... 196 Extended Instr�ction Set .....................

  • Page 7: Features

    HT66FM5440 Brushless DC Motor A/D Flash MCU Features CPU Features • Operating voltage =16MHz: 4.5V~5.5V ♦ • 0.0625μs instruction cycle with 16MHz system clock at V • Power down and wake-up functions to reduce power consumption • Oscillator types Internal High Speed 16MHz RC – HIRC ♦ Internal Low Speed 32kHz RC – LIRC ♦ • Multi-mode operation: NORMAL, IDLE and SLEEP • All instructions executed in 1~3 instruction cycles • Table read instructions • 115 powerful instructions • 8-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 4K×16 • RAM Data Memory: 384×8...

  • Page 8: General Description

    HT66FM5440 Brushless DC Motor A/D Flash MCU General Description The BLDC Motor Flash MCU HT66FM5440 provides PWM configuration flexibility and complete protection mechanism which are necessary for brushless DC motor applications. The device uses the HT8-1T architecture to achieve one oscillation cycle for one instruction. With the integrated 16MHz oscillator, executing a single instruction only needs 0.0625μs. Compared with its predecessor, the HT66FM5440 adds the interrupt priority configuration function and two interrupt preempt functions, which can be flexibly configured according to different interrupt priority requirements for different systems. Two unsigned Multiplication and Division Units (MDU), one 8-bit type and one 16-bit type, are provided for complicated operational requirements. The 16-bit MDU additionally integrates a 32-bit/16-bit unsigned divider.

  • Page 9: Block Diagram

    HT66FM5440 Brushless DC Motor A/D Flash MCU Block Diagram Port A PA0~PA7 Reset Driver UART Circuit 4K×16 384×8 Port B Pin-Shared PB0~PB7 Driver & Interrupt Stack Pin-Remapping Port C INT1 LVD/LVR PC0~PC5 Function Controller 8-Level Driver Port D Pin-Shared PD0~PD3...

  • Page 10: Pin Description

    HT66FM5440 Brushless DC Motor A/D Flash MCU Pin Description The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. Pin Name Function Description PAPU General p�rpose I/O. Register enabled p�ll-�p PAWU CMOS and wake-�p PAPS0 PAPS0 NMOS C data/address line � PA0/SDA/RX/ ICPDA/OCDSDA PAPS0 — External UART RX serial data inp�t pin ICPDA —...
  • Page 11 HT66FM5440 Brushless DC Motor A/D Flash MCU Pin Name Function Description PAPU General p�rpose I/O. Register enabled p�ll-�p PA� PAWU CMOS and wake-�p PAPS1 PA�/OPA�O/ OPA�O PAPS1 — Operational Amplifier 2 output NFIN/AN6 PAPS1 NFIN — Noise Filter External inp�t PAPS1 —...
  • Page 12 HT66FM5440 Brushless DC Motor A/D Flash MCU Pin Name Function Description PBPU PB� CMOS General p�rpose I/O. Register enabled p�ll-�p PBPS1 TP�_1 PBPS1 — CMOS PTM� o�p�t PB�/TP�_1/TX/ AN� PBPS1 — CMOS External UART TX serial data o�tp�t pin AN�...

  • Page 13: Absolute Maximum Ratings

    HT66FM5440 Brushless DC Motor A/D Flash MCU Pin Name Function Description — — Digital negative power s�pply� gro�nd VSS&AVSS AVSS — — Analog negative power s�pply� gro�nd Legend: I/T: Input type; O/T: Output type; OPT: Optional by register option; PWR: Power; ST: Schmitt Trigger input; CMOS: CMOS output; NMOS: NMOS output; AN: Analog signal Absolute Maximum Ratings Supply Voltage ....................V −0.3V to V +6.0V...

  • Page 14: Characteristics

    HT66FM5440 Brushless DC Motor A/D Flash MCU A.C. Characteristics Ta=�5°C, unless otherwise specified Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions 4.5V~ System Clock (HIRC) =16MHz — — HIRC 5.5V Ta=�5°C -1.0% +1.0% Ta= -40°C~�5°C -�.0% +�.0% High Speed Internal RC Oscillator HIRC Freq�ency (HIRC)

  • Page 15: A/D Converter Electrical Characteristics

    HT66FM5440 Brushless DC Motor A/D Flash MCU Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Minim�m Low Voltage Width to — — 1�0 �40 4�0 μs Reset Minim�m Low Voltage Width to — — 1�0 �40 μs Interr�pt A/D Converter Electrical Characteristics Ta=�5°C...

  • Page 16: D/A Converter Electrical Characteristics

    HT66FM5440 Brushless DC Motor A/D Flash MCU D/A Converter Electrical Characteristics Ta=�5°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions D/A Converter Operating Voltage — — — D/A Converter O�tp�t Voltage — 00h~FFh� no load 0.01 — 0.99 D/A Conversion Time —...

  • Page 17: Operational Amplifier 1 & 2 Electrical Characteristics

    HT66FM5440 Brushless DC Motor A/D Flash MCU Operational Amplifier 1 & 2 Electrical Characteristics Ta=�5°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Operating Voltage — — Power Down C�rrent — — — μA Inp�t Offset Voltage Witho�t calibration —...

  • Page 18: Comparators Electrical Characteristics

    HT66FM5440 Brushless DC Motor A/D Flash MCU Comparators Electrical Characteristics Ta=�5°C Test Condition Symbol Parameter Min. Typ. Max. Unit Conditions Comparator Operating Voltage — — Comparator Operating C�rrent — — μA Comparator Power Down C�rrent 5V Comparator disabled — —...

  • Page 19: System Architecture

    HT66FM5440 Brushless DC Motor A/D Flash MCU System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of the device take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching, instruction execution and data write-back operation are overlapped, hence instructions are effectively executed in one or two cycles for most of the standard or extended instructions respectively, with the exception of branch or call instructions which needs one more cycle. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these...

  • Page 20: Stack

    HT66FM5440 Brushless DC Motor A/D Flash MCU Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a non- consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low...

  • Page 21: Arithmetic And Logic Unit - Alu

    HT66FM5440 Brushless DC Motor A/D Flash MCU If the stack is overflow, the first Program Counter save in the stack will be lost. Program Co�nter Top of Stack Stack Level 1 Stack Level � Stack Stack Level 3 Pointer Program Memory Bottom of Stack Stack Level � Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may...

  • Page 22: Flash Program Memory

    HT66FM5440 Brushless DC Motor A/D Flash MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For the device the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, the Flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 4K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. 000H Initialisation Vector 004H Interr�pt Vectors...
  • Page 23 HT66FM5440 Brushless DC Motor A/D Flash MCU The accompanying diagram illustrates the addressing data flow of the look-up table. Program Memory Last Page or TBHP Register Data 16 bits TBLP Register User Selected Register TBLH Register High Byte Low Byte Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is "0F00H" which refers to the start address of the last page within the 4K words Program Memory of the device. The table pointer low byte register is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "0F06H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the specific address pointed by the TBLP and TBHP registers if the "TABRD [m]" or "LTABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m]" or "LTABRD [m]" instruction is executed.

  • Page 24: In Circ�It Programming - Icp

    In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in- circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re- insertion of the device. Holtek Writer Pins MCU Programming Pins Pin Description ICPDA Programming Serial Data/Address ICPCK PA� Programming Clock Power S�pply Gro�nd...

  • Page 25: On-Chip Deb�G S�Pport - Ocds

    On-Chip Debug Support – OCDS There is an EV chip named HT66VM5440 which is used to emulate the HT66FM5440 device. The EV chip device also provides an "On-Chip Debug" function to debug the real MCU device during the development process. The EV chip and the real MCU device are almost functionally compatible except for "On-Chip Debug" function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide". Holtek e-Link Pins EV Chip Pins Pin Description OCDSDA OCDSDA On-Chip Deb�g S�pport Data/Address inp�t/o�tp�t OCDSCK OCDSCK On-Chip Deb�g S�pport Clock inp�t Power S�pply Gro�nd Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored.

  • Page 26: Data Memory Addressing

    HT66FM5440 Brushless DC Motor A/D Flash MCU Special P�rpose Data Memory (Sector 0 ~ Sector �) �FH �0H General P�rpose Data Memory (Sector 0 ~ Sector �) Sector 0 Sector 1 Sector � Data Memory Structure Data Memory Addressing For the device that supports the extended instructions, there is no Bank Pointer for Data Memory.
  • Page 27 HT66FM5440 Brushless DC Motor A/D Flash MCU Sector 0, 2 Sector 1 Sector 0, 2 Sector 1 IAR0 IAR0 ADHVDL ADHVDH ADBYPS IAR1 IAR1 PBPS0 PBPS0 MP1L MP1L PBPS1 PBPS1 MP1H MP1H OCPS ADCR3 INTEG0 INTEG0 CTRL CTRL TBLP TBLP...

  • Page 28: Special Function Register Description

    HT66FM5440 Brushless DC Motor A/D Flash MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section; however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only from Sector 0 while the IAR1 register together with the MP1L/MP1H register pair and IAR2 register together with the MP2L/MP2H register pair can access data from any Data Memory Sector. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers will return a result of "00H" and writing to the registers will result in no operation.

  • Page 29: Acc�M�Lator - Acc

    HT66FM5440 Brushless DC Motor A/D Flash MCU Indirect Addressing Program Example 2 data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h start: mov a, 04h ;...

  • Page 30: Program Co�Nter Low Register - Pcl

    HT66FM5440 Brushless DC Motor A/D Flash MCU Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the SC flag, CZ flag, zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/ logical operation and system management flags are used to record the status and operation of the microcontroller.
  • Page 31 HT66FM5440 Brushless DC Motor A/D Flash MCU In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. STATUS Register Name "x": �nknown Bit 7 SC: The result of the "XOR" operation which is performed by the OV flag and the MSB of the instruction operation result. Bit 6 CZ: The operational result of different flags for different instructions. For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag. For SBC/SBCM/LSBC/LSBCM instructions, the CZ flag is the "AND" operation result which is performed by the previous operation CZ flag and current operation zero flag. For other instructions, the CZ flag will not be affected. Bit 5 TO: Watchdog Time-out flag 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred. Bit 4 PDF: Power down flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3 OV: Overflow flag...

  • Page 32: Oscillators

    HT66FM5440 Brushless DC Motor A/D Flash MCU Oscillators Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through relevant control registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. Fully integrated internal oscillators, requiring no...

  • Page 33: Internal High Speed Rc Oscillator - Hirc

    HT66FM5440 Brushless DC Motor A/D Flash MCU Internal High Speed RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 16MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Note that if this internal system clock option is selected, as it requires no external pins for its operation. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal...

  • Page 34: System Operation Modes

    HT66FM5440 Brushless DC Motor A/D Flash MCU High Speed Oscillator 6-stage HIRC Prescaler /� /� /3� HLCLK� CKS�~CKS0 bits Low Speed Oscillator LIRC LIRC Time Base TBCK Watchdog Timer Device Clock Configurations System Operation Modes There are four different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. The NORMAL Mode allows normal operation of the...

  • Page 35: Control Registers

    HT66FM5440 Brushless DC Motor A/D Flash MCU NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator. This mode operates allowing the microcontroller to operate normally with a clock source coming from the HIRC oscillator. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the HLCLK bit and CKS2~CKS0 bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLEEP Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP mode the CPU will be stopped. However the f and f clocks will continue to operate. IDLE0 Mode The IDLE0 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer, TMs and Time Base. In the IDLE0 Mode, the system oscillator will be stopped, the f and f clocks will be on. IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as TMs and Time Base. In the IDLE1 Mode, the system oscillator will continue to run, and the f and f clocks will be on.
  • Page 36 HT66FM5440 Brushless DC Motor A/D Flash MCU LTO: Low speed oscillator ready flag Bit 3 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed oscillator is stable after power on reset or a wake-up has occurred. HTO: High speed system oscillator ready flag Bit 2 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as "1" by the application program after device power-on. Bit 1 IDLEN: IDLE Mode Control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Bit 0 HLCLK: System Clock Selection 0: f /2 ~ f /64 1: f...

  • Page 37: Operating Mode Switching

    HT66FM5440 Brushless DC Motor A/D Flash MCU Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching from the NORMAL Mode to the SLEEP/IDLE Modes is executed via the HALT instruction. When an HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the condition of the IDLEN bit in the SMOD register and the FSYSON bit in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, f , to the clock source, f /2~f /64. The accompanying flowchart shows what happens when the device moves between the various operating modes. IDLE1 NORMAL HALT instr�ction exec�ted CPU stop IDLEN=1 CPU r�n FSYSON=1 IDLE0 SLEEP HALT instr�ction exec�ted HALT instr�ction exec�ted...

  • Page 38: Standby C�Rrent Considerations

    HT66FM5440 Brushless DC Motor A/D Flash MCU Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in the SMOD register equal to "1" and the FSYSON bit in the CTRL register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction, but the Time Base clock f , and the low frequency clock f and the Watchdog Timer clock f will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with both the IDLEN bit in the SMOD register equal to "1" and the FSYSON bit in the CTRL register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The system clock, Time Base clock f...

  • Page 39: Wake-�P

    HT66FM5440 Brushless DC Motor A/D Flash MCU Wake-up To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the CPU will be switched off. However, when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow If the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. The actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake- up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.00 ��ne ��� �01�...

  • Page 40: Watchdog Timer

    HT66FM5440 Brushless DC Motor A/D Flash MCU Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, f , which can be supplied by the LIRC oscillator. The LIRC internal oscillator has an approximate frequency of 32kHz and this specified internal clock period can vary with V , temperature and process variations. The Watchdog Timer source clock is then subdivided by a ratio of 2 to 2 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Note that the Watchdog Timer function is always enabled, which can be controlled by the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable operation. The WDTC register is initiated to 01010011B at any reset and keeps unchanged at the WDT time-out occurrence in a power down state. WDTC Register Name WE� WS� WE4~WE0: WDT function software control Bit 7~3...

  • Page 41: Watchdog Timer Operation

    HT66FM5440 Brushless DC Motor A/D Flash MCU LVRF: LVR function reset flag Bit 2 Described elsewhere LRF: LVR control register software reset flag Bit 1 Described elsewhere Bit 0 WRF: WDT control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps...

  • Page 42: Reset And Initialisation

    HT66FM5440 Brushless DC Motor A/D Flash MCU Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring internally.
  • Page 43 HT66FM5440 Brushless DC Motor A/D Flash MCU RSTD Internal Reset Low Voltage Reset Timing Chart • LVRC Register Name LVS� LVS6 LVS5 LVS4 LVS3 LVS� LVS1 LVS0 Bit 7~0 LVS7~LVS0: LVR Voltage Select control 01010101: 3.8V 00110011: 3.8V 10011001: 3.8V 10101010: 3.8V Any other value: Generates MCU reset – register is reset to POR value When an actual low voltage condition occurs, as specified by the defined LVR voltage value above, an MCU reset will be generated. The reset operation will be activated after 2~3 f clock cycles. In this situation the register contents will remain the same LIRC after such a reset occurs.

  • Page 44: Reset Initial Conditions

    HT66FM5440 Brushless DC Motor A/D Flash MCU Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as a LVR reset except that the Watchdog time-out flag TO will be set to "1". WDT Time-o�t RSTD Internal Reset WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for details.
  • Page 45 HT66FM5440 Brushless DC Motor A/D Flash MCU WDT Time-out WDT Time-out Register Power On Reset (Normal Operation) (IDLE/SLEEP) IAR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �...
  • Page 46 HT66FM5440 Brushless DC Motor A/D Flash MCU WDT Time-out WDT Time-out Register Power On Reset (Normal Operation) (IDLE/SLEEP) CAPTMDH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �...
  • Page 47 HT66FM5440 Brushless DC Motor A/D Flash MCU WDT Time-out WDT Time-out Register Power On Reset (Normal Operation) (IDLE/SLEEP) � � � � � � � � (ADRFS=0� ADCRL_SEL=0) - - - - � � � � (ADRFS=1� ADCRL_SEL=0) ADHVDH x x x x x x x x x x x x x x x x �...
  • Page 48 HT66FM5440 Brushless DC Motor A/D Flash MCU WDT Time-out WDT Time-out Register Power On Reset (Normal Operation) (IDLE/SLEEP) IICTOC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �...
  • Page 49 HT66FM5440 Brushless DC Motor A/D Flash MCU WDT Time-out WDT Time-out Register Power On Reset (Normal Operation) (IDLE/SLEEP) � � � � � � � � (ADRFS=0� ADCRL_SEL=0) - - - - � � � � (ADRFS=1� ADCRL_SEL=0) ISRH0 x x x x x x x x x x x x x x x x �...
  • Page 50 HT66FM5440 Brushless DC Motor A/D Flash MCU WDT Time-out WDT Time-out Register Power On Reset (Normal Operation) (IDLE/SLEEP) � � � � � � � � (ADRFS=0� ADCRL_SEL=0) - - - - � � � � (ADRFS=1� ADCRL_SEL=0) ISRH3 x x x x x x x x x x x x x x x x �...

  • Page 51: Input/Output Ports

    HT66FM5440 Brushless DC Motor A/D Flash MCU WDT Time-out WDT Time-out Register Power On Reset (Normal Operation) (IDLE/SLEEP) PTM3DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �...

  • Page 52: P�Ll-High Resistors

    HT66FM5440 Brushless DC Motor A/D Flash MCU Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers, namely PAPU~PDPU, and are implemented using weak PMOS transistors. Note that the pull-high resistor can be controlled by the relevant pull-high control register only when the pin-shared functional pin is selected as an input or NMOS output. Otherwise, the pull-high resistors cannot be enabled. PxPU Register Name PxPU� PxPU6 PxPU5 PxPU4 PxPU3 PxPU� PxPU1 PxPU0 PxPUn: I/O Port x Pin pull-high function control 0: Disable 1: Enable The PxPUn bit is used to control the pin pull-high function. Here the "x"can be A, B, C and D. However, the actual available bits for each I/O Port may be different. Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature...

  • Page 53: I/O Port Control Registers

    HT66FM5440 Brushless DC Motor A/D Flash MCU I/O Port Control Registers Each I/O port has its own control register known as PAC~PDC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the...
  • Page 54 HT66FM5440 Brushless DC Motor A/D Flash MCU input pins, such as INTn, TCKn, etc, which share the same pin-shared control configuration with their corresponding general purpose I/O functions when setting the relevant pin-shared control bit fields. To select these pin functions, in addition to the necessary pin-shared control and peripheral functional setup aforementioned, they must also be setup as an input by setting the corresponding bit in the I/O port control register. To correctly deselect the pin-shared function, the peripheral function should first be disabled and then the corresponding pin-shared function control register can be modified to select other pin-shared functions. Register Name PAPS0 PA3S1 PA3S0 PA�S1 PA�S0 PA1S1 PA1S0 PA0S1 PA0S0 PAPS1 PA�S1 PA�S0 PA6S1 PA6S0 PA5S1 PA5S0 PA4S1 PA4S0 PBPS0 PB3S1 PB3S0 PB�S1 PB�S0 PB1S1...
  • Page 55 HT66FM5440 Brushless DC Motor A/D Flash MCU • PAPS1 Register Name PA�S1 PA�S0 PA6S1 PA6S0 PA5S1 PA5S0 PA4S1 PA4S0 Bit 7~6 PA7S1~PA7S0: PA7 Pin-Shared function selection 00: PA7/NFIN 01: AN6 10: PA7/NFIN 11: OPA2O Bit 5~4 PA6S1~PA6S0: PA6 Pin-Shared function selection 00: PA6 01: C1N 10: AN7 11: OPA1O Bit 3~2 PA5S1~PA5S0: PA5 Pin-Shared function selection 00: PA5/H3 01: PA5/H3 10: C3P 11: PA5/H3 Bit 1~0 PA4S1~PA4S0: PA4 Pin-Shared function selection 00: PA4/H2...
  • Page 56 HT66FM5440 Brushless DC Motor A/D Flash MCU 11: TP3_0 Rev. 1.00 ��ne ��� �01�...
  • Page 57 HT66FM5440 Brushless DC Motor A/D Flash MCU • PBPS1 Register Name PB�S1 PB�S0 PB6S1 PB6S0 PB5S1 PB5S0 PB4S1 PB4S0 Bit 7~6 PB7S1~PB7S0: PB7 Pin-Shared function selection 00: PB7 01: TX 10: TP2_1 11: AN2 Note that to select this TX pin function, the corresponding output source selection bit in the PRM register should be cleared to 0. Bit 5~4 PB6S1~PB6S0: PB6 Pin-Shared function selection 00: PB6 01: RX 10: TP2_0 11: OPA0O Bit 3~2 PB5S1~PB5S0: PB5 Pin-Shared function selection 00: PB5 01: TP2_1 10: C2N 11: PB5 Bit 1~0...
  • Page 58 HT66FM5440 Brushless DC Motor A/D Flash MCU • PCPS1 Register Name — — — — PC5S1 PC5S0 PC4S1 PC4S0 — — — — — — — — Bit 7~4 Unimplemented, read as "0" Bit 3~2 PC5S1~PC5S0: PC5 Pin-Shared function selection 00: PC5 01: PC5 10: GCB 11: PC5 Bit 1~0 PC4S1~PC4S0: PC4 Pin-Shared function selection 00: PC4 01: PC4 10: GCT 11: PC4 •...
  • Page 59 HT66FM5440 Brushless DC Motor A/D Flash MCU • PRM Register Name NFINPS INT1PS RXPS TXPS C1NPS1 C1NPS0 SDAPS SCLPS Bit 7 NFINPS: NFIN input source pin selection 0: PA7 1: PB0 Bit 6 INT1PS: INT1 input source pin selection 0: PB0 1: PD2 Bit 5 RXPS: RX input source pin selection 0: PB6 1: PA0 Bit 4 TXPS: TX output source pin selection 0: PB7 1: PA2 Bit 3~2 C1NPS1~C1NPS0: C1N input source pin selection 00: PB3 01: PA4 10: PA6...

  • Page 60: I/O Pin Str�Ct�Res

    HT66FM5440 Brushless DC Motor A/D Flash MCU I/O Pin Structures The accompanying diagram illustrates the internal structure of the I/O logic function. As the exact logical construction of the I/O pin will differ from this drawing, it is supplied as a guide only to assist with the functional understanding of the I/O logic function. The wide range of pin-shared structures does not permit all types to be shown. P�ll-high Register Weak Control Bit Select P�ll-�p Data B�s Write Control Register Chip Reset I/O pin Read Control Register Data Bit Write Data Register Read Data Register System Wake-�p...

  • Page 61: Timer Modules - Tm

    HT66FM5440 Brushless DC Motor A/D Flash MCU Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. Introduction The device contains four TMs with each TM having a reference name of PTMn. The PTM0 and PTM1 are 16-bit Periodic Type TMs while the PTM2 and PTM3 are 10-bit Periodic Type TMs. The common features to the 16-bit and 10-bit Periodic TMs will be described in this section and the detailed operation will be described in the Periodic Type TMs section. The main features of TMs are...

  • Page 62: Tm External Pins

    HT66FM5440 Brushless DC Motor A/D Flash MCU TM Interrupts The Periodic type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs has one TM input pin, with the label TCKn. The PTMn input pin, TCKn, is essentially a clock source for the PTMn and is selected using the PTnCK2~PTnCK0 bits in the PTMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. The TCKn input pin can be chosen to have either a rising or falling active edge. The TCKn pin is also used as the external trigger input pin in single pulse output mode. The TMs each have two output pin with the label TPn_0 and TPn_1. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn_0 and TPn_1 output...

  • Page 63: Programming Considerations

    HT66FM5440 Brushless DC Motor A/D Flash MCU Programming Considerations The TM Counter Registers and the Capture/Compare CCRA, CCRB and CCRP registers, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA, CCRB and CCRP registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the "MOV" instruction to access the CCRA, CCRB and CCRP low byte registers, named PTMnAL, PTMnBL and PTMnRPL, using the following access procedures. Accessing the CCRA, CCRB or CCRP low byte registers without following these access procedures will result in unpredictable values. PTMn Co�nter Register (Read only) PTMnDL PTMnDH �-bit B�ffer...

  • Page 64: Periodic Type Tm - Ptm

    HT66FM5440 Brushless DC Motor A/D Flash MCU Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can be controlled with one or two external input pins and can drive one or two external output pins. Note that the TM input and output pin functions should be selected by proper configuration which is described in the Pin-shared Functions section. Name TM No. TM Input Pin TM Output Pin 16-bit PTM 0� 1 TCK0� TP0_0; TCK1� TP1_0 TP0_0� TP0_1; TP1_0� TP1_1 10-bit PTM ��...

  • Page 65: Periodic Tm Operation

    HT66FM5440 Brushless DC Motor A/D Flash MCU CCRP Comparator P Match 10-bit Comparator P TMnPF Interr�pt PTOC b0~b9 TPn_0 O�tp�t Polarity 10-bit Co�nter Clear Control Control TPn_1 Co�nt-�p Co�nter PTnON PTnCCLR b0~b9 PTnPAU PTM1� PTM0 PTPOL PTIO1� PTIO0 TCKn Comparator A Match 10-bit Comparator A TMnAF Interr�pt...

  • Page 66: Periodic Type Tm Register Description

    HT66FM5440 Brushless DC Motor A/D Flash MCU Periodic Type TM Register Description Overall operation of the Periodic Type TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit or 16-bit value, while three read/write register pairs exist to store the internal 10-bit or 16-bit CCRA value, CCRP value and CCRB value. The remaining three registers are control registers which setup the different operating and control modes. Register Name PTMnC0 PTnPAU PTnCK� PTnCK1 PTnCK0 PTnON — — — PTMnC1 PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnCAPTS PTnCCLR PTMnC� — — —...
  • Page 67 HT66FM5440 Brushless DC Motor A/D Flash MCU PTnCK2~PTnCK0: Select PTMn Counter clock Bit 6~4 000: f 001: f 010: f 011: f 100: f 101: f 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the PTMn. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source is the system clock, while f and f are other internal clocks, the details of which can be found in the oscillator section. Bit 3 PTnON: PTMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the PTMn. Setting the bit high enables the counter to run, clearing the bit disables the PTMn. Clearing this bit to zero will stop the counter from counting and turn off the PTMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the PTMn is in the Compare Match Output Mode, PWM output Mode or Single Pulse Output Mode then the PTMn output pin will be reset to its initial condition, as specified by the PTnOC bit, when the PTnON bit changes from low to high. Bit 2~0 Unimplemented, read as "0" PTMnC1 Register (n=0~3)
  • Page 68 HT66FM5440 Brushless DC Motor A/D Flash MCU 00: Input capture at rising edge of TPn_0 or TCKn and the counter value will be latched into CCRA 01: Input capture at falling edge of TPn_0 or TCKn and the counter value will be latched into CCRA 10: Input capture at falling/rising edge of TPn_0 or TCKn and the counter value will be latched into CCRA 11: Input capture disabled PTnTCLR[1:0]=01B or 10B or 11B: 00: Input capture at rising edge of TPn_0 or TCKn and the counter value will be latched into CCRB 01: Input capture at falling edge of TPn_0 or TCKn and the counter value will be latched into CCRA 10: Input capture at falling/rising edge of TPn_0 or TCKn and the counter value will be latched into CCRA at falling edge and into CCRB at rising edge 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the PTMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTMn is running. In the Compare Match Output Mode, the PTnIO1 and PTnIO0 bits determine how the PTMn output pin changes state when a compare match occurs from the Comparator A. The PTMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the PTMn output pin should be setup using the PTnOC bit in the PTMnC1 register. Note that the output level requested by the PTnIO1 and PTnIO0 bits must be different from the initial value setup using the PTnOC bit otherwise no change will occur on the PTMn output pin when a compare match occurs. After the PTMn output pin changes state, it can be reset to its initial level by changing the level of the PTnON bit from low to high. In the PWM Mode, the PTnIO1 and PTnIO0 bits determine how the PTMn output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the...
  • Page 69 HT66FM5440 Brushless DC Motor A/D Flash MCU PTnPOL: PTMn Output polarity Control Bit 2 0: Non-invert 1: Invert This bit controls the polarity of the output pins. When the bit is set high the PTMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the PTMn is in the Timer/Counter Mode. Bit 1 PTnCAPTS: PTMn Capture Trigger Source Selection 0: From TPn_0 pin 1: From TCKn pin This bit is used to select the PTMn capture input trigger source. However for PTM0, the capture trigger source is also determined by the CINS bit in the NF_VIH register. When the PT0CAPTS bit is set to 1, the capture input trigger source can be TCK0 or noise filtered Dat_Out signal determined using the CINS bit. Bit 0 PTnCCLR: Select PTMn Counter clear condition 0: PTMn Comparator P match 1: PTMn Comparator A match This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PTnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PTnCCLR bit is not used in the PWM Mode, Single Pulse or Capture Input Mode. PTMnC2 Register (n=0~3) Name — —...
  • Page 70 HT66FM5440 Brushless DC Motor A/D Flash MCU PTMnDH Register (n=0~1) Name D1� D� Bit 7~0 D15~D8: PTMn Counter High Byte Register bit 7 ~ bit 0 PTMn 16-bit Counter bit 15 ~ bit 8 PTMnDH Register (n=2~3) Name — — — — — — D� — — — — — — — — — — — — Bit 7~2 Unimplemented, read as "0"...
  • Page 71 HT66FM5440 Brushless DC Motor A/D Flash MCU PTMnBH Register (n=0~1) Name D1� D� D15~D8: PTMn CCRB High Byte Register bit 7 ~ bit 0 Bit 7~0 PTMn 16-bit CCRB bit 15 ~ bit 8 PTMnBH Register (n=2~3) Name — — — — — — D� — — — — — — — — — — — — Bit 7~2 Unimplemented, read as "0"...

  • Page 72: Periodic Type Tm Operating Modes

    HT66FM5440 Brushless DC Motor A/D Flash MCU Periodic Type TM Operating Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PTnM1 and PTnM0 bits in the PTMnC1 register. Compare Match Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match...
  • Page 73 HT66FM5440 Brushless DC Motor A/D Flash MCU Counter Value Co�nter overflow PTnCCLR = 0; PTnM[1:0] = 00 CCRP > 0 CCRP=0 Co�nter cleared by CCRP val�e 0xFFFF or 0x3FF CCRP > 0 Co�nter Res�me Restart CCRP Pa�se Stop CCRA Time...
  • Page 74 HT66FM5440 Brushless DC Motor A/D Flash MCU Counter Value PTnCCLR = 1; PTnM[1:0] = 00 CCRA = 0 CCRA > 0 Co�nter cleared by CCRA val�e Co�nter overflow 0xFFFF or 0x3FF CCRA=0 Res�me CCRA Pa�se Stop Co�nter Restart CCRP Time...
  • Page 75 HT66FM5440 Brushless DC Motor A/D Flash MCU Timer/Counter Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the PTMn output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively. The PWM function within the PTMn is useful for applications which require functions...
  • Page 76 HT66FM5440 Brushless DC Motor A/D Flash MCU Counter Value PTnM[1:0] = 10 Co�nter cleared by CCRP Co�nter Reset when PTnON ret�rns high CCRP Co�nter Stop if Pa�se Res�me PTnON bit low CCRA Time PTnON PTnPAU PTnPOL CCRA Int. Flag TMnAF CCRP Int.
  • Page 77 HT66FM5440 Brushless DC Motor A/D Flash MCU Single Pulse Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively and also the PTnIO1 and PTnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTMn output pin. The trigger for the pulse output leading edge is a low to high transition of the PTnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PTnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the PTnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PTnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTMn interrupt. The counter...
  • Page 78 HT66FM5440 Brushless DC Motor A/D Flash MCU Counter Value PTnM[1:0] = 10 ; PTnIO[1:0] = 11 Co�nter stopped by CCRA Co�nter Reset when PTnON ret�rns high CCRA Co�nter Stops by Res�me Pa�se software CCRP Time PTnON A�to. set by Software...
  • Page 79 HT66FM5440 Brushless DC Motor A/D Flash MCU Capture Input Mode To select this mode bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPn_0 or TCKn pin which is selected using the PTnCAPTS bit in the PTMnC1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The counter is started when the PTnON bit changes from low to high which is initiated using the application program. The PTnIO1 and PTnIO0 bits decide which active edge transition type to be latched and to generate an interrupt. The PTnTCLR1 and PTnTCLR0 bits decide the condition that the counter reset back to zero. The present counter value latched into CCRA or CCRB is decided by both PTnIO1~PTnIO0 and PTnTCLR1~PTnTCLR0 setting. The PTnIO1~PTnIO0 and PTnTCLR1~PTnTCLR0 bits are setup independently on each other. When the required edge transition appears on the TPn_0 or TCKn pin the present value in the counter will be latched into the CCRA or CCRB registers and a PTMn interrupt generated.
  • Page 80 HT66FM5440 Brushless DC Motor A/D Flash MCU Co�nter Val�e PTnM[1:0] = 01; PTnTCLR[1:0] = 00 Co�nter cleared by CCRP Co�nter Co�nter Stop Reset CCRP Res�me Pa�se Time PTnON PTnPAU Active Active Active edge edge edge PTMn Capt�re Pin TPn_0 or TCKn CCRA Int.
  • Page 81 HT66FM5440 Brushless DC Motor A/D Flash MCU PTnM [1:0] = 01; PTnTCLR[1:0] = 01 Co�nter Val�e Co�nter cleared by CCRP Co�nter Co�nter Stop Reset CCRP Res�me Pa�se Time PTnON PTnPAU Active Active Active Active edge edge edge edge PTMn Capt�re Pin TPn_0 or TCKn CCRA Int.
  • Page 82 HT66FM5440 Brushless DC Motor A/D Flash MCU Co�nter cleared by Co�nter Val�e PTnM [1:0] = 01; PTnTCLR[1:0] = 10 CCRP Co�nter Co�nter Stop Reset CCRP Res�me Pa�se Time PTnON PTnPAU Active Active Active edge edge edge PTMn Capt�re Pin TPn_0 or TCKn CCRA Int.
  • Page 83 HT66FM5440 Brushless DC Motor A/D Flash MCU PTnM [1:0] = 01; PTnTCLR[1:0] = 11 Co�nter Val�e Co�nter cleared by CCRP Co�nter Co�nter Stop Reset CCRP Res�me Pa�se Time PTnON PTnPAU Active Active Active Active edge edge edge edge PTMn Capt�re Pin TPn_0 or TCKn CCRA Int.

  • Page 84: Capture Timer Module - Captm

    HT66FM5440 Brushless DC Motor A/D Flash MCU Capture Timer Module – CAPTM The Capture Timer Module is a timing unit specifically used for Motor Control purposes. The CAPTM is controlled by a program selectable clock source. Capture Timer Overview At the core of the Capture Timer is a 16-bit count-up counter which is driven by a user selectable internal clock source which is some multiple of the system clock or by the PWM. There is also an internal comparator which compares the value of this 16-bit counter with a pre-programmed 16- bit value stored in two registers. There are two basic modes of operation, a Compare Mode and a Capture Mode, each of which can be used to reset the internal counter. When a compare match situation is reached a signal will be generated to reset the internal counter. The counter can also be cleared when a capture trigger is generated by one of four sources, FHA, FHB, FHC and CTIN. INTA INTB INTC Rising/Falling CAPNFT/...
  • Page 85 HT66FM5440 Brushless DC Motor A/D Flash MCU CAPTC0 Register Name CAPTPAU CAPTCK� CAPTCK1 CAPTCK0 CAPTON — CAPS1 CAPS0 — — Bit 7 CAPTPAU: CAPTM Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the CAPTM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4...
  • Page 86 HT66FM5440 Brushless DC Motor A/D Flash MCU CAPEN: CAPTM capture input control Bit 5 0: Disable 1: Enable CAPNFT: CAPTM Noise Filter sample times definition Bit 4 0: Twice 1: 4 times The CAPTM Noise Filter circuit requires sampling the signal twice or 4 times continuously, when the sampled signals are all the same, the signal will be acknowledged. The sample clock is decided by the CAPNFS bit.
  • Page 87 HT66FM5440 Brushless DC Motor A/D Flash MCU CAPTMAH Register Name D1� D� Bit 7~0 D15~D8: CAPTM Compare High Byte Register bit 7 ~ bit 0 CAPTM 16-bit Compare Register bit 15 ~ bit 8 CAPTMCL Register Name D� D� "x": �nknown D7~D0: CAPTM Capture Low Byte Register bit 7 ~ bit 0 Bit 7~0 CAPTM 16-bit Capture Register bit 7 ~ bit 0 CAPTMCH Register Name D1� D� "x": �nknown D15~D8: CAPTM Capture High Byte Register bit 7 ~ bit 0 Bit 7~0 CAPTM 16-bit Capture Register bit 15 ~ bit 8 Capture Timer Operation The Capture Timer is used to detect and measure input signal pulse widths and periods. It can be used in Capture or Compare Mode. There are four timer capture inputs, FHA, FHB, FHC and CTIN.
  • Page 88 HT66FM5440 Brushless DC Motor A/D Flash MCU Noise Filter Sampling Noise Filter with CAPNFT=0 and CAPNFS=0 Capture Mode Operation The capture timer module contains two capture registers, CAPTMCL and CAPTMCH, which are used to store the present value in the counter. When the Capture Module is enabled, then each capture input source receives a valid trigger signal, the content of the free running counter-up 16- bit counter, which is contained in the CAPTMDL and CAPTMDH registers, will be captured into the capture registers, CAPTMCL and CAPTMCH. When this occurs, the relevant interrupt priority flag bit in the interrupt control register will be set. If this interrupt is enabled by setting the relevant interrupt priority enable bit high, an interrupt will be generated. If the CAPCLR bit is set high, then the 16-bit counter will be automatically reset after a capture event occurs. Compare Mode Operation When the timer is used in the compare mode, the CAPTMAL and CAPTMAH registers are used to store the 16-bit compare value. When the free running value of the count-up 16-bit counter reaches a value equal to the programmed values in these compare registers, the relevant interrupt priority flag will be set which will generate an interrupt if its related interrupt priority enable bit is set. If the CAMCLR bit is set high, then the counter will be reset to zero automatically when a compare match condition occurs. The rotor speed or a stalled motor condition can be detected by setting the compare registers to compare the captured signal edge transition time. If a rotor stall condition occurs, then a compare interrupt will be generated, after which the PWM motor drive circuit can be shut down to prevent a motor burn out situation.

  • Page 89: Noise Filter

    HT66FM5440 Brushless DC Motor A/D Flash MCU Noise Filter The external NFIN pin is connected to an internal filter to reduce the possibility of unwanted event counting events or inaccurate pulse width measurements due to adverse noise or spikes on the NFIN input signal, and then outputs to the 16-bit PTM0 capture circuit in order to ensure that the motor control circuit works normally. The noise filter circuit is an I/O surge filtering analog circuit which can filter micro-second grade sharp-noise. Antinoise pulse width maximum: (NF_VIH[4:0]-NF_VIL[4:0])×5μs, (NF_VIH[4:0]-NF_VIL[4:0])>1 Data_In Data_O�t NFIN Noise Filter PT0IO1~PT0IO0 TCK0 NF_BYPS Edge Detector TP0_0 CINS 150ns noise filter PT0CAPTS Dat_In Noise Filter PTM0 Dat_Out NF_VIH[4:0] NF_VIL[4:0]...
  • Page 90 HT66FM5440 Brushless DC Motor A/D Flash MCU NF_VIH Register Name NF_BYPS CINS — D� — — Bit 7 NF_BYPS: Bypass Noise Filter enable 0: Disable 1: Enable, Dat_Out=Dat_In Bit 6 CINS: PTM0 capture source selection 0: Noise Filter Dat_Out not selected (remains original PTM0 capture path with 150ns filter) 1: Noise Filter Dat_Out selected Bit 5 Unimplemented, read as "0" Bit 4~0 D4~D0: NF_VIH register bit 4 ~ bit 0 NF_VIL Register Name NFIS1 NFIS0 — D� — — NFIS1~NFIS0: NFIN interrupt edge control Bit 7~6...

  • Page 91: Analog To Digital Converter

    HT66FM5440 Brushless DC Motor A/D Flash MCU Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Converter Overview This device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals, or internal signals, and convert these signals directly into a 12-bit or 10-bit digital value. The six external channels can be individually configured to be isolated using the unity-gain buffer when connected to the internal A/D converter. This function can avoid transient voltages caused by channel switching from affecting the channel voltage to be measured. However, in this case the input voltage is limited in the range of V +0.1V to V...

  • Page 92: A/D Converter Register Description

    HT66FM5440 Brushless DC Motor A/D Flash MCU ADDL ADSTR DLSTR Start ADLVD/ADHVD DELAY PWM Int ADR/ISR AD HL/LV Int_AHL_ Lim AN� Trigger ADBYPS Int_AD_EOC or int_AD_ISEOC EOCB or ISEOCB AN� Bypass Av=1/5/10/�0 OPA0O OPA1O OPA�O ACS3~ACS0 ADISn3~ADISn0 OPA1P OPA1N Bypass channel selector OPA�P...
  • Page 93 HT66FM5440 Brushless DC Motor A/D Flash MCU Register Name ADBYPS UGB_ON — BYPSAN� BYPSAN6 BYPSAN3 BYPSAN� BYPSAN1 BYPSAN0 ADLVDL (ADRFS=0� D� — — — — ADCRL_SEL=0) ADLVDL (ADRFS=1� D� D� ADCRL_SEL=0) ADLVDL (ADRFS=0� — — — — — — ADCRL_SEL=1) ADLVDL (ADRFS=1�...
  • Page 94 HT66FM5440 Brushless DC Motor A/D Flash MCU A/D Converter Data Registers – ADRL, ADRH, ISRLn, ISRHn As this device contains an internal up to 12-bit A/D converter, it requires two data registers to store each converted value. These are a high byte register, known as ADRH, and a low byte register, known as ADRL, to store the converted value which is triggered by the ADSTR bit. The device also contains four register pairs to strore the converted value which is triggered by the DLSTR bit. Each register pair is composed of a high byte register, known as ISRHn, and a low byte register, known as ISRLn. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits or 10 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0 register together with the ADCRL_SEL bit in the ADCR2 register as shown in the accompanying tables. D0~D11 or D0~D9 are the A/D conversion result data bits. Any unused bits will be read as zero. • ADCRL_SEL=0 → 12-bit Format ADRH (Read only) ADRL (Read only) ADRFS D11 D10 D9 D�...
  • Page 95 HT66FM5440 Brushless DC Motor A/D Flash MCU • ADCRL_SEL=0 → 12-bit Format ADLVDH (R/W) ADLVDL (R/W) ADRFS D11 D10 D9 D� D� D� D11 D10 D9 D� D� D� ADHVDH (R/W) ADHVDL (R/W) ADRFS D11 D10 D9 D� D� D�...
  • Page 96 HT66FM5440 Brushless DC Motor A/D Flash MCU • ADCR0 Register Name ADSTR EOCB ADOFF ADRFS ACS3 ACS� ACS1 ACS0 Bit 7 ADSTR: Start the A/D conversion 0→1→0: Start 0→1: Reset the A/D converter and set EOCB to "1" This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6 EOCB: End of A/D conversion flag 0: A/D conversion is ended 1: A/D conversion is in progress This read only flag is used to indicate when an A/D conversion process has completed. When a conversion process is running the bit will be high. Bit 5 ADOFF: A/D converter power on/off control 0: A/D converter power on 1: A/D converter power off This bit controls the power to the A/D internal function. This bit should be cleared to zero to enable the A/D converter. If the bit is set high, then the A/D converter will be switched off reducing the device power consumption. As the A/D converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. It is...
  • Page 97 HT66FM5440 Brushless DC Motor A/D Flash MCU • ADCR1 Register Name ADRE DLSTR PWIS ADCHVE ADCLVE ADCK� ADCK1 ADCK0 Bit 7 ADRE: ADSTR triggered A/D conversion interrupted by A/D auto-scan flag 0: ADSTR triggered A/D conversion interrupted by A/D auto-scan has not occurred 1: ADSTR triggered A/D conversion interrupted by A/D auto-scan has occurred As the A/D auto-scan triggered conversion has a higher priority than the ADSTR triggered A/D conversion, it can interrupt an ongoing ADSTR triggered A/D conversion. The ADRE bit can be used to monitor whether such condition has...
  • Page 98 HT66FM5440 Brushless DC Motor A/D Flash MCU • ADCR2 Register Name IOEOCB ADCRL_SEL ADCH_SEL1 ADCH_SEL0 ISEOCB — PWDIS1 PWDIS0 — — Bit 7 IOEOCB: A/D auto-scan circuit status flag 0: A/D auto-scan circuit is idle 1: A/D auto-scan circuit is busy This bit will be set high by hardware when the A/D auto-scan circuit is in a busy status, in which case ADSTR triggered A/D conversions are not allowed. Bit 6 ADCRL_SEL: A/D resolution selection 0: 12-bit, one conversion needs 18×t ADCK 1: 10-bit, one conversion needs 16×t ADCK Bit 5~4 ADCH_SEL1~ADCH_SEL0: Number of channels to be scanned selection 00: 1 channel 01: 2 channels 10: 3 channels 01: 4 channels This setup is only available for A/D auto-scan triggered conversion. After setting these bits, the actual channel to be converted is configured using the ADISn3~ADISn0 bits.
  • Page 99 HT66FM5440 Brushless DC Motor A/D Flash MCU • ADISG1 Register Name ADIS13 ADIS1� ADIS11 ADIS10 ADIS03 ADIS0� ADIS01 ADIS00 Bit 7~4 ADIS13~ADIS10: Auto-scan triggered A/D conversion second analog channel input selection 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: OPA2 output 0101: OPA1 output 0110: OPA0 output 0111: AN6 1000: AN7 1001~1111: Undefined When using the auto-scan mechnism to trigger the A/D conversion and multiple channels are selected, the A/D converter will orderly switch to the channel selected by the ADIS1 bit field. After this conversion the result is stored in the ISRH1 and ISRL1...
  • Page 100 HT66FM5440 Brushless DC Motor A/D Flash MCU • ADISG2 Register Name ADIS33 ADIS3� ADIS31 ADIS30 ADIS�3 ADIS�� ADIS�1 ADIS�0 Bit 7~4 ADIS33~ADIS30: Auto-scan triggered A/D conversion fourth analog channel input selection 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: OPA2 output 0101: OPA1 output 0110: OPA0 output 0111: AN6 1000: AN7 1001~1111: Undefined When using the auto-scan mechnism to trigger the A/D conversion and multiple channels are selected, the A/D converter will orderly switch to the channel selected by the ADIS3 bit field. After this conversion the result is stored in the ISRH3 and ISRL3...

  • Page 101: A/D Converter Operation

    HT66FM5440 Brushless DC Motor A/D Flash MCU • ADDL Register Name D� D� Bit 7~0 D7~D0: A/D delay time register bit 7 ~ bit 0 (count by f A/D delay time value=(1/f ) × ADDL[7:0] • ADBYPS Register Name UGB_ON — BYPSAN� BYPSAN6 BYPSAN3 BYPSAN� BYPSAN1 BYPSAN0 — — Bit 7 UGB_ON: Unity-gain buffer on/off control 0: Disable 1: Enable Bit 6 Unimplemented, read as "0" Bit 5 BYPSAN7: AN7 bypass unity-gain buffer control 0: Disable, AN7 go through unity-gain buffer...
  • Page 102 HT66FM5440 Brushless DC Motor A/D Flash MCU The EOCB bit in the ADCR0 register is used to indicate whether the ADSTR triggered analog to digital conversion process is completed. This bit will be automatically cleared to zero by the microcontroller after an A/D conversion cycle has ended. Similarly, the ISEOCB bit in the ADCR2 register is used to indicate whether the A/D auto-scan triggered analog to digital conversion process is completed. This bit will be automatically set high by the microcontroller after all the selected channels for the A/D auto-scan conversion have been converted. In addition, the corresponding A/D interrupt request flag AEOCF or ISAEOCF will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal...

  • Page 103: S�Mmary Of A/D Conversion Steps

    HT66FM5440 Brushless DC Motor A/D Flash MCU Controlling the power on/off function of the A/D converter circuitry is implemented using the ADOFF bit in the ADCR0 register. This bit must be cleared to power on the A/D converter. When the ADOFF bit is cleared to power on the A/D converter internal circuitry, a certain delay as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs, if the ADOFF bit is low, then some power will still be consumed. In power conscious applications it is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D converter function is not being used. The boundary register pairs, ADHVDH/ADHVDL and ADLVDH/ADLVDL contain preset values which can be compared with the converted values of OPA0O, OPA1O and OPA2O that are stored in ADRH/ADRL registers or ISRHn/ISRLn registers. Various types of comparisons can be made as defined by the ADCLVE and ADCHVE bits and an interrupt will be generated to inform the system that either the lower or higher boundary has been execeeded. This function can be used to ensure...
  • Page 104 HT66FM5440 Brushless DC Motor A/D Flash MCU ADCLK ADSTR ADCK START EOCB DEOC D[11:0] 000H DOUT ADOFF 12-bit A/D Conversion Timing ADCLK ADSTR ADCK START EOCB DEOC D[9:0] 000H DOUT ADOFF 10-bit A/D Conversion Timing DLSTR Triggered A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement a DLSTR triggered A/D conversion process.

  • Page 105: Considerations For Sim�Tanio�Sly �Sing Both Trigger Methods

    HT66FM5440 Brushless DC Motor A/D Flash MCU • Step 5 Select A/D converter resolution and data format by setting the ADCRL_SEL bit in the ADCR2 register and the ADRFS bit in the ADCR0 register. • Step 6 If A/D conversion interrupt is used, the interrupt control registers must be correctly configured to ensure the A/D interrupt function is active. The master interrupt control bit, EMI, the A/D conversion interrupt control bit, ISAEOCE, and the associated interrupt priority control bit, Int_ prinE, must all be set high in advance. • Step 7 After the A/D conversion process is complete, the ISEOCB flag will go high and then the output data can be read from ISRHn and ISRLn registers. After reading the converted results, the ISEOCB bit should be cleared to zero by application program. Note: When checking for the end of the conversion process, if the method of polling the ISEOCB bit in the ADCR2 register is used, the interrupt enable step above can be omitted. Considerations for simutaniously using both trigger methods...

  • Page 106: Programming Considerations

    HT66FM5440 Brushless DC Motor A/D Flash MCU The following are some important notes for simutaniously using both trigger methods: • The analog channel to be converted by the ADSTR triggered A/D conversion is determined by the ACS bit field. • The analog channels to be converted by the DLSTR triggered A/D conversion is determined by the ADCH_SEL and ADISn bit fields. Up to four channels can be converted in one DLSTR triggered A/D conversion. • The DLSTR triggered A/D conversion has a higher priority than the ADSTR triggered A/D conversion thus the former can interrupt the later. If this happens the ongoing ADSTR triggered A/D conversion will be abandoned and the ADRE bit will be set high by hardware to inform the system that the current result in the ADRH and ADRL registers is invalid. • When entering the DLSTR trigger mode, the A/D converter will automatically switch to the first channel defined by the ADIS0 bie field. The system will wait for a delay time defined by ADDL and start to convert the first channel. Note that only before the first channel conversion the ADDL delay time is required. • During each channel conversion the system will simutaniously check whether the current channel is the last one. If no the converter will switch to the next channel. If yes the converter will switch back to the channel defined by the ACS bit field. • The converted result of channel defined by ADISn bit field is strored in the ISRHn and ISRLn registers. • When the last channel conversion has been finished, the ISEOCB bit will be set high and the ISAEOCF interrupt will be generated. • When switching back to the ACS defined channel, the converter will not re-sample the interrupted A/D conversion channel. If users need to re-sample the input channel, set the ADSTR bit from low to high and low again. Programming Considerations...

  • Page 107: A/D Conversion Programming Examples

    HT66FM5440 Brushless DC Motor A/D Flash MCU 1.5 LSB FFFH FFEH FFDH A/D Conversion Result 0.5 LSB 0�H 4096 � 4093 4094 4095 4096 Analog Input Voltage Ideal A/D Conversion Function A/D Conversion Programming Examples The following two programming examples illustrate how to setup and implement an ADSTR triggered A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR0...
  • Page 108 HT66FM5440 Brushless DC Motor A/D Flash MCU Example: using the interrupt method to detect the end of conversion clr AEOCE ; disable A/D interrupt mov a,03H mov ADCR1,a ; select f /8 as A/D clock clr ADOFF mov a,01h ; setup PDPS0 to configure pin AN0 mov PDPS0,a...

  • Page 109: Comparators

    HT66FM5440 Brushless DC Motor A/D Flash MCU Comparators Four independent analog comparators are contained within the device. These functions offer flexibility via their register controlled features such as power-down, hysteresis etc. In sharing their pins with normal I/O pins the comparators do not waste precious I/O pins if there functions are otherwise unused. OPA0 output Comparator 0 DAC output Comparator 1 Comparator 2 Comparator 3 Note: When the PB3S1~PB3S0 bits in the PBPS0 register are configured to 10B, the switches circled in the block diagram will be turned on, in which case C1N, C2N and C3N is shorted internally and connected to the CPN pin.

  • Page 110: Comparator Register

    HT66FM5440 Brushless DC Motor A/D Flash MCU Comparator Register The CMPC control register controls othe hysteresis functions and on/off control of the four comparators. As the comparator 0 is used in the over current detector, there will be more description about it in the associated chapter. CMPC Register Name C3HYEN C�HYEN C1HYEN C0HYEN C3EN C�EN C1EN C0EN Bit 7 C3HYEN: Comparator 3 hysteresis control 0: Disable 1: Enable...

  • Page 111: Over Current Detection

    HT66FM5440 Brushless DC Motor A/D Flash MCU C1EN: Comparator 1 on/off control Bit 1 0: Off 1: On This is the Comparator 1 on/off control bit. If the bit is zero the comparator 1 will be switched off and no power consumed even if analog voltages are applied to its inputs. For power sensitive applications this bit should be cleared to zero if the comparator 1 is not used or before the device enters the SLEEP or IDLE mode. C0EN: Comparator 0 on/off control Bit 0 0: Off 1: On This is the Comparator 0 on/off control bit. If the bit is zero the comparator 0 will be switched off and no power consumed even if analog voltages are applied to its inputs. For power sensitive applications this bit should be cleared to zero if the comparator 0 is not used or before the device enters the SLEEP or IDLE mode. Over Current Detection The device contains a fully integrated over current detect circuit which is used for motor protection. PB6/OPA0O Int_AHL_ Lim OP & Compare Int_Is ADLVD/ADHVD ADR/ISR PB6S[1:0] AD HL/LV Int_AHL_ Lim...
  • Page 112 HT66FM5440 Brushless DC Motor A/D Flash MCU Over Current Detect Register There are three registers to control the function and operation of the over current detection circuits, known as OPOMS, OPCM and OPA0CAL. These 8-bit registers define functions such as comparator 0 interrupt edge control, OPA0 operation mode selection and OPA0 calibration. The OPCM register is an 8-bit DAC register used for OPA0 comparison. OPOMS Register Name CMP0_EG1 CMP0_EG0 — — — OPA0VS� OPA0VS1 OPA0VS0 — — — — — — Bit 7~6 CMP0_EG1~CMP0_EG0: Interrupt edge control for Comparator 0 00: Comparator 0 and D/A converter disabled 01: Rising edge trigger 10: Falling edge trigger 11: Dual edge trigger Bit 5~4 Unimplemented, read as "0"...

  • Page 113: Phase Current Detection

    HT66FM5440 Brushless DC Motor A/D Flash MCU Phase Current Detection The device contains a fully integrated phase current detect circuit which is used for motor protection. PA6S[1:0] PD1/OPA1P OPA1O OPA1 PA6/OPA1O PD0/OPA1N To A/D converter PA�S[�:0] PD3/OPA�P OPA�O OPA� PA�/OPA�O PD�/OPA�N To A/D converter Phase Current Detector Block Diagram Phase Current Detect Functional Description The phase current detect function can be implemented using OPA1 and OPA2. The OPA1 and OPA2 outputs can be measured by connecting to the A/D converter. These two signals can also be output...

  • Page 114: Bldc Motor Control Circuit

    HT66FM5440 Brushless DC Motor A/D Flash MCU BLDC Motor Control Circuit This section describes how the device can be used to control Brushless DC Motors, otherwise known as BLDC Motors. Its high level of functional integration and flexibility offer a full range of driving features for motor driving. Functional Description The PWM counter circuit output PWMO has an adjustable PWM Duty to control the output motor power thus controlling the motor speed. Changing the PWM frequency can be used to enhance the motor drive efficiency or to reduce noise and resonance generated during physical motor operation. The internal Mask circuit is used to determine which PWM modulation signals are enabled or disabled for the motor speed control. The PWM modulation signal can be output using both the...

  • Page 115: Pwm Co�Nter Control Circ�It

    HT66FM5440 Brushless DC Motor A/D Flash MCU PWM Counter Control Circuit The device includes a 10-bit PWM generator. The PWM signal has both adjustable duty cycle and frequency that can be setup by programming 10-bit values into the corresponding PWM registers. PWMR DUTR0~� PRDR PWMC PWM0~� 10-bit PWMD0~�_Int PWM �p/down co�nter PWMP_Int PWM Block Diagram New PWM Period PWMP(New) PWMP(Old) New PWM D�ty PWMD_CH0(New) PWMD_CH0(Old) PWMO PWMD_CH0(New) PWMP(New)
  • Page 116 HT66FM5440 Brushless DC Motor A/D Flash MCU PWM Duty Synchronous Update Modes In high speed BLDC applications, using PWM interrupt to update the duty may result in asynchronous update for the three PWM duty values. This will generate undesired PWM duty outputs and lead to control errors. To improve this problem, two methods are provided for...
  • Page 117 HT66FM5440 Brushless DC Motor A/D Flash MCU • PWMC Register Name PWMMS1 PWMMS0 PCKS1 PCKS0 PWMON ITCMS1 ITCMS0 PWMLD Bit 7~6 PWMMS1~PWMMS0: PWM mode selection 0x: Edge-aligned mode 10: Center-aligned mode 1 11: Center-aligned mode 2 Bit 5~4 PCKS1~PCKS0: PWM counter clock source selection (f based on f 00: f 01: f 10: f 11: f PWM frequency=1/{PWMR×[1/(f /n)]} Bit 3 PWMON: PWM circuit on/off control 0: Off 1: On This bit controls the overall on/off function of the PWM. Setting the bit high enables the counter to run, clearing the bit disables the PWM. Clearing this bit to zero will stop the counter from counting and turn off the PWM which will reduce its power consumption.
  • Page 118 HT66FM5440 Brushless DC Motor A/D Flash MCU • DUTRnL Register (n=0~3) Name D� D� Bit 7~0 D7~D0: 10-bit PWMn Duty Low Byte Register bit 7 ~ bit 0 10-bit DUTRn Register bit 7 ~ bit 0 • DUTRnH Register (n=0~3) — Name — — — — — D� — — — — — — — — — — —...

  • Page 119: Mask F�Nction

    HT66FM5440 Brushless DC Motor A/D Flash MCU • PWMRH Register — Name — — — — — D� — — — — — — — — — — — — Bit 7~2 Unimplemented, read as "0" Bit 1~0 D9~D8: 10-bit PWM Counter High Byte Register bit 1 ~ bit 0 10-bit PWM Counter bit 9 ~ bit 8 Mask Function The device includes a Motor Control Mask Function for increased control flexibility. PWMME PWMMD...
  • Page 120 HT66FM5440 Brushless DC Motor A/D Flash MCU Normal Mode In the Normal Mode, the motor speed control method is determined by the PWMS/MPWE bits in the MCF register. • When PWMS =0, the bottom port PWM output selects transistor pair bottom arm GAB/ GBB/ GCB. • When PWMS =1, the top port PWM output selects transistor pair top arm, GAT/ GBT/ GCT. • When MPWE =0, the PWM output is disabled and AT0/BT0/CT0/AB0/BB0/CB0 are all on. • When MPWE =1, the PWM output is enabled and AT0/BT0/CT0/AB0/BB0/CB0 can output a variable PWM signal for speed control. • When MPWMS=0, the PWM has a Complementary output. • When MPWMS=1, the PWM has a Non-complementary output. • When MSKMS=0, Hardware Mask Mode is selected. • When MSKMS=1, Software Mask Mode is selected. • MCF Register Name MSKMS — — — MPWMS MPWE FMOS PWMS —...
  • Page 121 HT66FM5440 Brushless DC Motor A/D Flash MCU Hardware Mask Mode • Complementary control, MPWMS=0 PWMS=0 PWMB PWMO PWMS=1 PWMO PWMB PWMS=0 PWMB PWMO PWMS=1 PWMO PWMB PWMS=0 PWMB PWMO PWMS=1 PWMO PWMB • Non-complementary control, MPWMS=1 PWMS=0 PWMO PWMS=1 PWMO...
  • Page 122 HT66FM5440 Brushless DC Motor A/D Flash MCU Software Mask Mode To control the software Mask circuit, two registers known as PWMME and PWMMD are provided. PWMME register is used to control PWM signal and PWMMD is used to determine the MOS Gate Driver Circuit is on or off. 3-phase inverter Symbol Mask Complement Mode Example PWMB PWMB PWMB PWMB PWMO PWMO PWMO PWMO Current Path (3,0) Current Path (5,0) Current Path (5,2) Current Path (1,2)
  • Page 123 HT66FM5440 Brushless DC Motor A/D Flash MCU • PWMME Register Name — — PME5 PME4 PME3 PME� PME1 PME0 — — — — Bit 7~6 Unimplemented, read as "0" Bit 5~0 PMEn: PWM mask enable bit (n=0~5) 0: PWM generator signal is output to the next stage 1: PWM generator signal is masked and PMDn is output to the next stage • PWMMD Register Name — — PMD5 PMD4 PMD3 PMD� PMD1 PMD0 —...
  • Page 124 HT66FM5440 Brushless DC Motor A/D Flash MCU Other Functions Several other functions exist for additional motor control drive signal flexibility. These are the Dead Time Function, Staggered Function and Polarity Control Function. Dead Time Function During transistor pair switching, the Dead Time function is used to prevent both upper and lower transistor pairs from conducting at the same time thus preventing a virtual short circuit condition from occurring. The actual dead time value can be setup to be within a value from 0.3μs to 5μs which is selected by the application program. The Dead Time Insertion circuit requires six independent output circuits: When the AT0/AB0/BT0/BB0/CT0/CB0 outputs experience a rising edge, then a Dead Time is inserted. When the AT0/AB0/BT0/BB0/CT0/CB0 outputs experience a falling edge, then the outputs remain unchanged. The Dead-Time Insertion Circuit is only used during motor control. The Dead Time function is controlled by the DTE bit in the DTS register. Dead-Time Insertion 1. Rising Add Dead-Time Insertion 2. Falling Unchange AT0,AB0 BT0,BB0...
  • Page 125 HT66FM5440 Brushless DC Motor A/D Flash MCU Staggered Function The Staggered Function is used to force all output drive transistors to an off condition when a software error occurs or due to external factors such as ESD. Note: The default condition for the BLDC motor control circuit is designed for default N-type transistor pairs. This means a "1" value will switch the transistor on and a "0" value will switch it off. Polarity Control Function This function allows setup of the external gate drive transistor On/Off polarity status. A single register, PLC, is used for overall control. • PLC Register Name —...
  • Page 126 HT66FM5440 Brushless DC Motor A/D Flash MCU Hall Sensor Decoder This device contains a fully integrated Hall Sensor decoder function which interfaces to the Hall Sensors in the BLDC motor for directional and speed control. HCHK_NUM HNF_MSEL HDLY_MSEL CTM_SEL[1:0] PWMO PWMB Hall Noise Filter Hall Delay Mask Hall Sensor PTMn-Int Decoder HDCD 12×6 Registers HDCEN HDMS HDCR BRKE BRKE PROTECT Hall Sensor Decoder Block Diagram The Hall Sensor input signals are selected by setting the HDMS bit high. If the HDMS bit is zero...
  • Page 127 HT66FM5440 Brushless DC Motor A/D Flash MCU Several registers are used to control the noise filter. The HNF_EN bit in the HNF_MSEL register is used as the overall enable/disable bit for the noise filter. It is necessary to enable CMP1, CMP2 and CMP3 hysteries function before the camparators are used during motor control sensorless applications. HNF_EN bit Status Noise filter off – HA/HB/HC bypass the noise filter Noise filter on Hall Sensor Noise Filter Enable The sampling frequency of the Hall noise filter is setup using the HFR_SEL [2:0] bits.
  • Page 128 HT66FM5440 Brushless DC Motor A/D Flash MCU Hall Delay Circuit Hall Noise Filter Hall Sensor Decoder HDCD 12×6 Register BUF1[2:0] BUF2[2:0] HDMS HDCEN HDLY_MSEL CTM_SEL[1:0] PTM0 PTM1 PTM3 (16-bit (16-bit (10-bit PTM) PTM) PTM) Delay Function Block Diagram Delay Time Delay Function Timing Rev.
  • Page 129 HT66FM5440 Brushless DC Motor A/D Flash MCU Motor Control Drive Signals The direction of the BLDC motor is controlled using the HDCR and HDCD registers as well as a series of HDCT registers, HDCT0~HDCT11. When using the Hall Sensor Decoder function, the direction can be determined using the FRS bit and the brake operation can be controlled using the BRKE bit. Both bits are in the HDCR register. Six bits in the HDCT0~HDCT5 registers are used for the Motor Forward table, and six bits in the HDCT6~HDCT11 registers are used for the Motor Backward table. The accompanying tables show the truth tables for each of the registers. 60 Degree 120 Degree Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HDCT0[5:0] Forward HDCT1[5:0] (HDCEN=1� FRS=0� HDCT�[5:0] BRKE=0) HDCT3[5:0] HDCT4[5:0] HDCT5[5:0] 60 Degree...
  • Page 130 Brushless DC Motor A/D Flash MCU Hall sensor: 1�0 degree Motor Forward �-pole Motor S� S� Power MOS HT66FM5440 IR�101×3 Moto HV Motor Motor Drive Signal Timing Diagram – Forward Direction Hall sensor: 1�0 degree Motor Backward �-pole Motor S1 S� S3 S4 S5 S6 S1 S�...
  • Page 131 HT66FM5440 Brushless DC Motor A/D Flash MCU Hall Sensor Decoder Register Description The HDCR register is the Hall Sensor Decoder control register, HDCD is the Hall Sensor Decoder input data register, and HDCT0~HDCT11 are the Hall Sensor Decoder tables. The HCHK_NUM register is the Hall Noise Filter check number register and HNF_MSEL is the Hall Noise Filter Mode select register. The INTEG0 register is Hall Noise Filter input source selection and output interrupt edge control register. • INTEG0 Register Name — HSEL INTCS1 INTCS0 INTBS1 INTBS0 INTAS1 INTAS0 — — Bit 7 Unimplemented, read as "0" Bit 6 HSEL: HA/HB/HC source selection 0: H1/H2/H3 1: CMP1/CMP2/CMP3 output Bit 5~4 INTCS1~INTCS0: FHC Interrupt edge control for INTC 00: Disable...
  • Page 132 HT66FM5440 Brushless DC Motor A/D Flash MCU BRKE: Motor brake control Bit 2 0: AT/BT/CT/AB/BB/CB=V 1: AT/BT/CT=0, AB/BB/CB=1 FRS: Motor Forward/Backward selection Bit 1 0: Forward 1: Backward Bit 0 HDCEN: Hall Sensor Decoder control 0: Disable 1: Enable • HDCD Register Name — — — — — — — — — — — — — — — Bit 7~3 Unimplemented, read as "0"...

  • Page 133: Hall Sensor Decoder

    HT66FM5440 Brushless DC Motor A/D Flash MCU • HCHK_NUM Register Name — — — HCK_N4 HCK_N3 HCK_N� HCK_N1 HCK_N0 — — — — — — Bit 7~5 Unimplemented, read as "0" Bit 4~0 HCK_N4~HCK_N0: Hall Noise Filter check times • HNF_MSEL Register Name — — — — HNF_EN HFR_SEL� HFR_SEL1 HFR_SEL0 —...
  • Page 134 HT66FM5440 Brushless DC Motor A/D Flash MCU PSWE PSWPS=0 PSWD PSWPS=1 Reset PROTECT AHLHE AHLPS=1 Int_AHL_Lim Delay AHLPS=0 ISPS=1 & Compare ISHE ISPS=0 Int_Is CapCHE PROTECTOC CapTM_Cmp Latch OCPSE Enable CAPTM Reset CapOHE CapTM_Over Protection Function Control Motor Protection Function Description...
  • Page 135 HT66FM5440 Brushless DC Motor A/D Flash MCU Current Protection Function The device contains an internal OPA0, a high speed (2µs) 12-bit A/D Converter, an 8-bit D/A Converter and a comparator to measure the motor current and to detect excessive current values If an over current situation should occur, then the external drive circuit can be shut down immediately to prevent motor damage. More details are provided in the Over Current Detection chapter. As the motor driver PCB will have rather large amounts of noise, and as this noise will be amplified by the OPA0, this can easily lead to false triggering. For this reason the Fault Mode must be used. The PROTECTOC mechanism provides a more immediate current protection. Ensure that the ISHE bit has been set to select the hardware over current protection before setting the OCPSE bit high. After this the over current compare interrupt int_Is can be used to directly switch off the drive signals. Since Int_Is is a pulse signal, a latch component must be used to latch the over current trigger source. When the PROTECTOC signal is logic high, the drive signals at the polarity stage will be ignored and the over current protection logics in the OCPS register are used to immediately switch off drive signals to protect the power MOS. To remove the PROTECTOC over current...
  • Page 136 HT66FM5440 Brushless DC Motor A/D Flash MCU HAT~HCB ×6 HAT~HCB ×6 S� S� 15KHz 15KHz ~64 �s ~64 �s PWM co�nter PWM co�nter GAT~GCB (×6) GAT~GCB (×6) (PWMO) (PWMO) Time Time Int_ADC Int_ADC Int_CMP Int_CMP MOS C�rrent Limiting Protection: (AHLHE=1; AHLPS=1) MOS Over C�rrent Protection: (ISHE=1;...
  • Page 137 HT66FM5440 Brushless DC Motor A/D Flash MCU Motor Protection Register Description There are three registers, MPTC1, MPTC2 and OCPS, which are used for the motor protection control function. • MPTC1 Register Name PSWD PSWE CapOHE CapCHE ISHE AHLHE — OCPSE — — PSWD: Motor Protection Software Mode data Bit 7 0: PSWD=0 1: PSWD=1 PSWE: Motor Protection Software Mode control Bit 6 0: Disable 1: Enable When the motor protection software mode has been enabled and triggered, is should be removed by setting this bit from high to low and then high again. CapOHE: CapTM_Over Hardware Mode control Bit 5 0: Disable...
  • Page 138 HT66FM5440 Brushless DC Motor A/D Flash MCU • MPTC2 Register Name — — — PSWPS AHLPS ISPS CAPCPS CAPOPS — — — — — — Bit 7~5 Unimplemented, read as "0" Bit 4 PSWPS: Pause/Fault Mode selection in Software Mode 0: Fault Mode 1: Pause Mode Bit 3 AHLPS: Int_AHL_Lim Pause/Fault Mode selection 0: Protection circuit allows immediate restart of PWM output when the Int_AHL_ Lim interrupt has been reset. 1: Protection circuit allows restart of PWM output on the next PWM period when the Int_AHL_Lim interrupt has been reset. Bit 2 ISPS: Int_Is Pause/Fault Mode selection 0: Fault Mode...
  • Page 139 HT66FM5440 Brushless DC Motor A/D Flash MCU • OCPS Register Name — — OCPCB OCPCT OCPBB OCPBT OCPAB OCPAT — — — — Bit 7~6 Unimplemented, read as "0" Bit 5 OCPCB: C pair Bottom port gate output selection 0: Output 0 1: Output 1 Bit 4 OCPCT: C pair Top port gate output selection 0: Output 0 1: Output 1 Bit 3 OCPBB: B pair Bottom port gate output selection 0: Output 0 1: Output 1 Bit 2 OCPBT: B pair Top port gate output selection 0: Output 0...

  • Page 140: I 2 C Interface

    HT66FM5440 Brushless DC Motor A/D Flash MCU C Interface The I C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. Device Device Device Slave Master Slave C Master/Slave Bus Connection C Interface Operation The I C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As...

  • Page 141: I C Registers

    HT66FM5440 Brushless DC Motor A/D Flash MCU Data B�s � � C Data Register C Address Register (IICD) (IICA) Address Address Match –HAAS Comparator � C Interr�pt Direction Control SCL Pin Debo�nce Data in MSB Shift Register Circ�itry SDA Pin Read/Write Slave Data o�t MSB...
  • Page 142 HT66FM5440 Brushless DC Motor A/D Flash MCU IICD Register Name D� D� "x": �nknown Bit 7~0 D7~D0: I C Data Buffer bit 7~bit 0 The IICA register is the location where the 7-bit slave address of the slave device is stored. When a master device, which is connected to the I C bus, sends out an address, which matches the slave address in the IICA register, the slave device will be selected. IICA Register Name A� ─ ─ ─ A6~A0: I Bit 7~1 C slave address A6~A0 is the I C slave address bit 6 ~ bit 0. Bits 7~ 1 of the IICA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I C bus, sends out an address, which matches the slave address in the IICA register, the slave device will be selected. Bit 0 Unimplemented, read as "0" There are two control registers for the I C interface, IICC0 and IICC1. The register IICC0 is used...
  • Page 143 HT66FM5440 Brushless DC Motor A/D Flash MCU IICC1 Register Name HAAS TXAK IAMWU RXAK Bit 7 HCF: I C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Below is an example of the flow of a two-byte I C data transfer. First, I...

  • Page 144: I � C B�S Comm�Nication

    HT66FM5440 Brushless DC Motor A/D Flash MCU IAMWU: I Bit 1 C Address Match Wake Up Control 0: Disable 1: Enable This bit should be set to 1 to enable the I C address match wake up from the SLEEP or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable the I C address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. RXAK: I Bit 0 C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave do not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is "1". When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I C Bus. C Bus Communication Communication on the I C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the IICC1 register will be set and an I C interrupt will be generated. After entering the interrupt service routine,...

  • Page 145: I � C B�S Start Signal

    HT66FM5440 Brushless DC Motor A/D Flash MCU Start Config�re the pin-shared I/O ports � to I C f�nction SET IICEN Write Slave Address to IICA � C B�s Interr�pt=? CLR IICE SET IICE and Int_prinE Poll IICF to decide Wait for Interr�pt �...

  • Page 146: I � C B�S Slave Address Acknowledge Signal

    HT66FM5440 Brushless DC Motor A/D Flash MCU C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no...

  • Page 147: I � C Time-O�T Control

    HT66FM5440 Brushless DC Motor A/D Flash MCU Start IICTOF=1? SET IICTOEN HAAS=1? CLR IICTOF HTX=1? SRW=1? RETI Read from IICD to CLR HTX SET HTX release SCL Line CLR TXAK RETI Write data to IICD to D�mmy read from IICD...
  • Page 148 HT66FM5440 Brushless DC Motor A/D Flash MCU Start Slave Address � C time-o�t co�nter start Stop � C time-o�t co�nter reset on SCL negative transition C Time-out When an I C time-out counter overflow occurs, the counter will stop and the IICTOEN bit will be cleared to zero and the IICTOF bit will be set high to indicate that a time-out condition has occurred. The time-out condition will also generate an interrupt which uses the I C interrupt vector. When an C time-out occurs, the I C internal circuitry will be reset and the registers will be reset into the following condition: Registers After I C Time-out IICD�...

  • Page 149: Uart Interface

    HT66FM5440 Brushless DC Motor A/D Flash MCU UART Interface The device contains an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features: • Full-duplex, asynchronous communication • 8 or 9 bits character length • Even, odd or no parity options • One or two stop bits...

  • Page 150: Uart External Pins

    HT66FM5440 Brushless DC Motor A/D Flash MCU UART External Pins To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX and RX pins are the UART transmitter and receiver pins respectively. The TX and RX pin function should first be selected by the corresponding pin-shared function selection register before the UART function is used. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will setup these pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the TX and RX pins. When the TX or RX pin function is disabled by clearing the UARTEN, TXEN or RXEN bit, the TX or RX pin will be set to a floating state. At this time whether the internal pull-high resistor is connected to the TX or RX pin or not is determined by the corresponding I/O pull-high function control bit. UART Data Transfer Scheme The above block diagram shows the overall data transfer structure arrangement for the UART. The actual data to be transmitted from the MCU is first transferred to the TXR_RXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR_RXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal TXR_RXR register, where it is buffered and can be manipulated by the application program. Only the TXR_ RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception only exists as a single shared register in the Data Memory. This shared register known as the TXR_RXR register is used for both data transmission and data reception. UART Status and Control Registers There are five control registers associated with the UART function. The USR, UCR1 and UCR2...
  • Page 151 HT66FM5440 Brushless DC Motor A/D Flash MCU USR Register The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only. Further explanation on each of the flags is given below: Name PERR FERR OERR RIDLE RXIF TIDLE TXIF Bit 7 PERR: Parity error flag 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is "0", it indicates a parity error has not been detected. When the flag is "1", it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the TXR_RXR data register. Bit 6 NF: Noise flag 0: No noise is detected 1: Noise is detected The NF flag is the noise flag. When this read only flag is "0", it indicates no noise condition. When the flag is "1", it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The NF flag can be cleared by a software sequence which will involve a read to the status register USR followed by an access to the TXR_RXR data register.
  • Page 152 HT66FM5440 Brushless DC Motor A/D Flash MCU RXIF: Receive TXR_RXR data register status Bit 2 0: TXR_RXR data register is empty 1: TXR_RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is "0", it indicates that the TXR_RXR read data register is empty. When the flag is "1", it indicates that the TXR_RXR read data register contains new data. When the contents of the shift register are transferred to the TXR_RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag will eventually be cleared when the USR register is read with RXIF set, followed by a read from the TXR_RXR register, and if the TXR_RXR register has no more new data available. Bit 1 TIDLE: Transmission idle 0: Data transmission is in progress (Data being transmitted) 1: No data transmission is in progress (Transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is "0", it indicates that a transmission is in progress. This flag will be set high when the TXIF flag is "1" and when there is no transmit data or break character being transmitted. When TIDLE is equal to "1", the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR_RXR register. The flag is not generated when a data character or a break is queued and ready to be sent. Bit 0 TXIF: Transmit TXR_RXR data register status 0: Character is not transferred to the transmit shift register 1: Character has transferred to the transmit shift register (TXR_RXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is "0", it indicates that the character is not transferred to the transmitter shift register. When the flag is "1", it indicates that the transmitter shift register has received a character from the TXR_RXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR_RXR data register.
  • Page 153 HT66FM5440 Brushless DC Motor A/D Flash MCU When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. Bit 6 BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to "1", a 9-bit data length format will be selected. If the bit is equal to "0", then an 8-bit data length format will be selected. If 9-bit data length format is selected, then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. Bit 5 PREN: Parity function enable control 0: Parity function is disabled 1: Parity function is enabled This is the parity enable bit. When this bit is equal to "1", the parity function will be enabled. If the bit is equal to "0", then the parity function will be disabled. Replace the most significant bit position with a parity bit. PRT: Parity type selection bit Bit 4 0: Even parity for parity generator 1: Odd parity for parity generator This bit is the parity type selection bit. When this bit is equal to "1", odd parity type will be selected. If the bit is equal to "0", then even parity type will be selected. STOPS: Number of Stop bits selection Bit 3...
  • Page 154 HT66FM5440 Brushless DC Motor A/D Flash MCU UCR2 Register The UCR2 register is the second of the two UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on each of the bits is given below: Name TXEN RXEN BRGH ADDEN WAKE TIIE TEIE Bit 7 TXEN: UART Transmitter enabled control 0: UART transmitter is disabled 1: UART transmitter is enabled The bit named TXEN is the Transmitter Enable Bit. When this bit is equal to "0", the transmitter will be disabled with any pending data transmissions being aborted. In addition the buffers will be reset. In this situation the TX pin will be set in a floating state. If the TXEN bit is equal to "1" and the UARTEN bit is also equal to "1", the transmitter will be enabled and the TX pin will be controlled by the UART. Clearing...
  • Page 155 HT66FM5440 Brushless DC Motor A/D Flash MCU WAKE: RX pin wake-up UART function enable control Bit 3 0: RX pin wake-up UART function is disabled 1: RX pin wake-up UART function is enabled This bit is used to control the wake-up UART function when a falling edge on the RX pin occurs. Note that this bit is only available when the UART clock (f ) is switched off. There will be no RX pin wake-up UART function if the UART clock (f ) exists. If the WAKE bit is set to 1 as the UART clock (f ) is switched off, a UART wake-up request will be initiated when a falling edge on the RX pin occurs. When this request happens and the corresponding interrupt is enabled, an RX pin wake-up UART interrupt will be generated to inform the MCU to wake up the UART function by switching on the UART clock (f ) via the application program. Otherwise, the UART function can not resume even if there is a falling edge on the RX pin when the WAKE bit is cleared to 0. Bit 2 RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled This bit enables or disables the receiver interrupt. If this bit is equal to "1" and when the receiver overrun flag OERR or receive data available flag RXIF is set, the UART interrupt request flag will be set. If this bit is equal to "0", the UART interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. TIIE: Transmitter Idle interrupt enable control Bit 1 0: Transmitter idle interrupt is disabled 1: Transmitter idle interrupt is enabled This bit enables or disables the transmitter idle interrupt. If this bit is equal to "1" and when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the UART interrupt request flag will be set. If this bit is equal to "0", the UART interrupt request flag will not be influenced by the condition of the TIDLE flag.

  • Page 156: Ba�D Rate Generator

    HT66FM5440 Brushless DC Motor A/D Flash MCU Baud Rate Generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the baud rate register BRG and the second is the value of the BRGH bit with the control register UCR2. The BRGH bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value N in the BRG register which is used in the following baud rate calculation formula determines the division factor. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit Ba�d Rate (BR) / [64 (N+1)] / [16 (N+1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. Calculating the Baud Rate and Error Values For a clock frequency of 4MHz, and with BRGH cleared to zero determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800.
  • Page 157 HT66FM5440 Brushless DC Motor A/D Flash MCU Enabling/Disabling the UART Interface The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX pin, then it will default to a logic high value. Clearing the UARTEN bit will disable the TX and RX pins and allow these two pins to be used as normal I/O or other pin-shared functional pins by configuring the corresponding pin-shared control bits. When the UART function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration. Data, Parity and Stop Bit Selection The format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9, the PRT bit controls the choice of odd or even parity, the PREN bit controls the parity on/off function and the STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit, which is the MSB of the data byte, identifies the frame as an address character or data if the address detect function is enabled. The number of stop bits, which can be either one or two, is independent of the data length and is only used for the transmitter. There is only one stop bit for the receiver.

  • Page 158: Uart Transmitter

    HT66FM5440 Brushless DC Motor A/D Flash MCU UART Transmitter Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR_RXR register. The data to be transmitted is loaded into this TXR_RXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR_RXR register, if it is available. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR_RXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initiated by first loading data into the TXR_RXR register, after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to the TXR_RXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin can then be configured as the I/O or other pin-shared functions by configuring the corresponding pin-shared control bits. Transmitting Data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit first. In the transmit mode, the TXR_RXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the TXEN bit to ensure that the TX pin is used as a UART transmitter pin.

  • Page 159: Uart Receiver

    HT66FM5440 Brushless DC Motor A/D Flash MCU Transmit Break If the TXBRK bit is set then break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13×N ‘0’ bits and stop bits, where N=1, 2, etc. If a break character is to be transmitted then the TXBRK bit must be first set by the application program, and then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognised. UART Receiver The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the receiver core lies the Receive Serial Shift Register, commonly known as the RSR. The data which is received on the RX external input pin is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Receiving Data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin, LSB first. In the read mode, the TXR_RXR register forms a buffer between the internal bus and the receiver shift register. The TXR_RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while a third byte can continue to be received. Note that the application program must ensure that the data is read from TXR_RXR before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of BNO, PRT and PREN bits to define the word length, parity type.

  • Page 160: Managing Receiver Errors

    HT66FM5440 Brushless DC Motor A/D Flash MCU Receive Break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO bit plus one stop bit. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO plus one stop bit. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. A break is regarded as a character that contains only zeros with the FERR flag set. If a long break signal has been detected, the receiver will regard it as a data frame including a start bit, data bits and the invalid stop bit and the FERR flag will be set. The receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: • The framing error flag, FERR, will be set. • The receive data register, TXR_RXR, will be cleared. • The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Idle Status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver Interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, TXR_RXR. An overrun error can also generate an interrupt if RIE=1.

  • Page 161: Uart Interr�Pt Str�Ct�Re

    HT66FM5440 Brushless DC Motor A/D Flash MCU Noise Error – NF Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame the following will occur: • The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. • Data will be transferred from the Shift register to the TXR_RXR register. • No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by a TXR_RXR register read operation. Framing Error – FERR The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high; otherwise the FERR flag will...

  • Page 162: Uart Power Down And Wake-�P

    HT66FM5440 Brushless DC Motor A/D Flash MCU USR Register UCR� Register TEIE Transmitter Empty Flag TXIF UART Interr�pt TIIE Transmitter Idle UARTE Int_prinE Interr�pt signal Req�est Flag Flag TIDLE to MCU UARTF Receiver Overr�n Flag OERR ADDEN Receiver Data Available RXIF...

  • Page 163: Low Voltage Detector - Lvd

    HT66FM5440 Brushless DC Motor A/D Flash MCU The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set when the MCU enters the power down mode with the UART clock f being switched off, then a falling edge on the RX pin will initiate an RX pin wake-up UART interrupt. Note that as it takes certain system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, the Interrupt priority enable bit, Int_prinE, and the UART interrupt enable bit, UARTE, must be set. If the EMI, Int_prinE and UARTE bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed. Low Voltage Detector – LVD The device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, V , and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select the fixed voltage below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the V voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low...

  • Page 164: Lvd Operation

    HT66FM5440 Brushless DC Motor A/D Flash MCU VBGEN: Bandgap Voltage Output Enable control Bit 3 0: Disable 1: Enable Note that the Bandgap circuit is enabled when the LVD or LVR function is enabled or when the VBGEN bit is set to 1. VLVD2~VLVD0: LVD Voltage selection Bit 2~0 000: 4.0V 001: 4.0V 010: 4.0V 011: 4.0V 100: 4.0V 101: 4.0V 110: 4.0V 111: 4.0V LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, V , with a pre-specified voltage level stored in the LVDC register. This pre-sepcified voltage level has a fixed value of 4.0V. When the power supply voltage, V , falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is in the SLEEP mode, the low voltage detector will be disabled even if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay t should be allowed for the circuitry LVDS to stabilise before reading the LVDO bit. Note also that as the V voltage may rise and fall rather slowly, at the voltage nears that of V , there may be multiple bit LVDO transitions.

  • Page 165: Multiplication Division Unit - Mdu

    HT66FM5440 Brushless DC Motor A/D Flash MCU Multiplication Division Unit – MDU The device has an 8-bit and a 16-bit Multiplication Division Units, named MDU0 and MDU1 respectively. The MDU0 integrates an 8-bit unsigned multiplier and divider. The MDU1 integrates a 16-bit unsigned multiplier and a 32-bit/16-bit divider. They can be used to calculate the motor electric rotation angle. The MDUs, in replacing the software multiplication and division operations, can therefore save large amounts of computing time as well as the Program and Data Memory space. They also reduce the overall microcontroller loading and results in the overall system performance improvements. �-bit Dividend MDU0R0 �-bit M�ltiplicand MD0DONE MD0OV...

  • Page 166: Mdu Registers

    HT66FM5440 Brushless DC Motor A/D Flash MCU MDU Registers For the 8-bit MDU0 the multiplication and division operations are determined by the MD0S bit and implemented by writing the required operand to the corresponding MDU0 data register. For the 16- bit MDU1 the multiplication and division operations are implemented in a specific way, a specific write access sequence of a series of MDU1 data registers. The status register, MDUnCTRL, provides the indications for the MDU operation. The data register each is used to store the data regarded as the different operand corresponding to different MDU operations. Register Name MDU0R0 D� D� MDU0R1 D� D� MDU0CTRL — — — — — MD0DONE MD0OV MD0S 8-Bit MDU0 Registers List Register Name MDU1R0 D�...

  • Page 167: Mdu Operation

    HT66FM5440 Brushless DC Motor A/D Flash MCU MDU1Rn Register – n=0~5 Name D� D� "x": �nknown Bit 7~0 D7~D0: 16-bit MDU1 data register n MDU1CTRL Register Name MD1EF MD1OV — — — — — — — — — — — — — — — — —...
  • Page 168 HT66FM5440 Brushless DC Motor A/D Flash MCU 16-bit MDU1 Operation For this MDU the multiplication or division operation is carried out in a specific way and is determined by the write access sequence of the six MDU1 data registers, MDU1R0~MDU1R5. The low byte data, regardless of the dividend, multiplicand, divisor or multiplier, must first be written into the corresponding MDU1 data register followed by the high byte data. All MDU1 operations will be executed after the MDU1R5 register is write-accessed together with the correct specific write access sequence of the MDU1Rn. Note that it is not necessary to consecutively write data into the MDU1 data registers but must be in a correct write access sequence. Therefore, a non-write MDU1Rn instruction or an interrupt, etc., can be inserted into the correct write access sequence without destroying the write operation. The relationship between the write access sequence and the MDU1 operation is shown in the following. • 32-bit/16-bit division operation: Write data sequentially into the six MDU1 data registers from MDU1R0 to MDU1R5. • 16-bit/16-bit division operation: Write data sequentially into the specific four MDU1 data registers in a sequence of MDU1R0, MDU1R1, MDU1R4 and MDU1R5 with no write access to MDU1R2 and MDU1R3.

  • Page 169: Interrupts

    HT66FM5440 Brushless DC Motor A/D Flash MCU Operations 32-bit / 16-bit Division 16-bit / 16-bit Division 16-bit × 16-bit Multiplication Items Write Seq�ence Dividend Byte 0 written to MDU1R0 First write Dividend Byte 1 written to MDU1R1 Dividend Byte 0 written to MDU1R0 M�ltiplicand Byte 0 written to MDU1R0...
  • Page 170 HT66FM5440 Brushless DC Motor A/D Flash MCU Interrupt Name Enable Bit Request Flag Interrupt Number HALAE HALAF M�lti-f�nction 0 HALBE HALBF (Hall Sensor A/B/C interr�pts) HALCE HALCF Comparator 0: Int_Is — — � PWMPE PWMPF PWMD0E PWMD0F M�lti-f�nction 1 (PWM Period and D�ty 0~�)
  • Page 171 HT66FM5440 Brushless DC Motor A/D Flash MCU INTEG0 Register Name — HSEL INTCS1 INTCS0 INTBS1 INTBS0 INTAS1 INTAS0 — — Bit 7 Unimplemented, read as "0" Bit 6 HSEL: HA/HB/HC source selection Described elsewhere INTCS1~INTCS0: FHC Interrupt edge control for INTC Bit 5~4 00: Disable 01: Rising edge trigger 10: Falling edge trigger 11: Dual edge trigger INTBS1~INTBS0: FHB Interrupt edge control for INTB Bit 3~2 00: Disable 01: Rising edge trigger 10: Falling edge trigger 11: Dual edge trigger Bit 1~0 INTAS1~INTAS0: FHA Interrupt edge control for INTA 00: Disable...
  • Page 172 HT66FM5440 Brushless DC Motor A/D Flash MCU Int_pri1F: Interrupt priority 1 request flag Bit 4 0: No request 1: Interrupt request Int_pri3E: Interrupt priority 3 control Bit 3 0: Disable 1: Enable Bit 2 Int_pri2E: Interrupt priority 2 control 0: Disable 1: Enable Bit 1 Int_pri1E: Interrupt priority 1 control 0: Disable 1: Enable Bit 0 EMI: Global interrupt control 0: Disable 1: Enable INTC1 Register Name Int_pri�F Int_pri6F Int_pri5F Int_pri4F Int_pri�E Int_pri6E Int_pri5E Int_pri4E Bit 7 Int_pri7F: Interrupt priority 7 request flag...
  • Page 173 HT66FM5440 Brushless DC Motor A/D Flash MCU INTC2 Register Name Int_pri11F Int_pri10F Int_pri9F Int_pri�F Int_pri11E Int_pri10E Int_pri9E Int_pri�E Bit 7 Int_pri11F: Interrupt priority 11 request flag 0: No request 1: Interrupt request Bit 6 Int_pri10F: Interrupt priority 10 request flag 0: No request 1: Interrupt request Int_pri9F: Interrupt priority 9 request flag Bit 5 0: No request 1: Interrupt request Int_pri8F: Interrupt priority 8 request flag Bit 4 0: No request 1: Interrupt request Int_pri11E: Interrupt priority 11 control Bit 3 0: No request 1: Interrupt request Int_pri10E: Interrupt priority 10 control Bit 2...
  • Page 174 HT66FM5440 Brushless DC Motor A/D Flash MCU Int_pri14E: Interrupt priority 14 control Bit 2 0: Disable 1: Enable Int_pri13E: Interrupt priority 13 control Bit 1 0: Disable 1: Enable Bit 0 Int_pri12E: Interrupt priority 12 control 0: Disable 1: Enable MFI0 Register Name — HALCF HALBF HALAF — HALCE HALBE HALAE — — — — Bit 7 Unimplemented, read as "0" Bit 6 HALCF: Hall sensor C interrupt request flag 0: No request 1: Interrupt request...
  • Page 175 HT66FM5440 Brushless DC Motor A/D Flash MCU PWMPE: PWM Period match interrupt control Bit 3 0: Disable 1: Enable PWMD2E: PWM2 Duty match interrupt control Bit 2 0: Disable 1: Enable Bit 1 PWMD1E: PWM1 Duty match interrupt control 0: Disable 1: Enable Bit 0 PWMD0E: PWM0 Duty match interrupt control 0: Disable 1: Enable MFI2 Register Name — — AEOCF ISAEOCF — — AEOCE ISAEOCE — — — — — —...
  • Page 176 HT66FM5440 Brushless DC Motor A/D Flash MCU MFI4 Register Name — — TM0AF TM0PF — — TM0AE TM0PE — — — — — — — — Bit 7~6 Unimplemented, read as "0" Bit 5 TM0AF: PTM0 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 TM0PF: PTM0 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 TM0AE: PTM0 Comparator A match interrupt control...
  • Page 177 HT66FM5440 Brushless DC Motor A/D Flash MCU MFI6 Register Name — — TM3AF TM3PF — — TM3AE TM3PE — — — — — — — — Bit 7~6 Unimplemented, read as "0" Bit 5 TM3AF: PTM3 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 TM3PF: PTM3 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 TM3AE: PTM3 Comparator A match interrupt control...

  • Page 178: Interrupt Priority Configuration

    HT66FM5440 Brushless DC Motor A/D Flash MCU Interrupt Priority Configuration Some interrupt sources have their own individual interrupt number while others share the same interrupt number, as shown in the Interrupt Registers section. All interrupts are categorised into fifteen priority levels, from the higheset interrupt priority 1 (04H) to the lowest interrupt priority 15 (3CH). Each interrupt priority level has its own interrupt enable bit and request flag. The actual priority for each interrupt source is configured by writing its corresponding interrupt number into the target bit field in the Pri_name0 ~ Pri_name7 registers. If an interrupt number is not configured into any interrupt priority level, when the interrupt source within this interrupt number occurs, only its interrupt request flag will be set high without further interrupt response. If an interrupt number has been configured into multiple interrupt priority levels, when the interrupt source within this interrupt number occurs, a subroutine call to each preset interrupt vector will take place according to the priority order. Note that after the interrupt priority initialisation, all the interrupt priority flags must be cleared once. Vector Interrupt Priority Enable Bit...
  • Page 179 HT66FM5440 Brushless DC Motor A/D Flash MCU Pri_name0 Register Name IP�R3 IP�R� IP�R1 IP�R0 IP1R3 IP1R� IP1R1 IP1R0 Bit 7~4 IP2R3~IP2R0: Setup the required interrupt number in interrupt priority 2 Bit 3~0 IP1R3~IP1R0: Setup the required interrupt number in interrupt priority 1 Pri_name1 Register Name IP4R3 IP4R� IP4R1 IP4R0 IP3R3 IP3R� IP3R1 IP3R0 Bit 7~4 IP4R3~IP4R0: Setup the required interrupt number in interrupt priority 4 Bit 3~0 IP3R3~IP3R0: Setup the required interrupt number in interrupt priority 3 Pri_name2 Register Name IP6R3 IP6R�...
  • Page 180 HT66FM5440 Brushless DC Motor A/D Flash MCU Pri_name6 Register Name IP14R3 IP14R� IP14R1 IP14R0 IP13R3 IP13R� IP13R1 IP13R0 Bit 7~4 IP14R3~IP14R0: Setup the required interrupt number in interrupt priority 14 Bit 3~0 IP13R3~IP13R0: Setup the required interrupt number in interrupt priority 13 Pri_name7 Register Name — — — — IP15R3 IP15R� IP15R1 IP15R0 — — — — — — —...

  • Page 181: Interr�Pt Operation

    HT66FM5440 Brushless DC Motor A/D Flash MCU The following example explains how the program runs when both preempt functions are enabled by setting the INTPRI1~INTPRI0 bits to 11B. Interrupt Vector High Priority Main loop System clock 1 Vector 10H preempts the main loop. 2 Exits vector 10H subroutine and returns to the main loop. 3 Vector 0CH preempts the main loop. 4 The second highest priority 08H preempts the 0CH subroutine. 5 The first highest priority 04H preempts the 08H subroutine. 6 Exits vector 04H subroutine by "RETI" and go no to execute the 08H subroutine. 7 Exits vector 08H subroutine by "RETI" and go no to execute the 0CH subroutine. 8 Exits vector 0CH subroutine by "RETI" and returns to the main loop. Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A match or A/D conversion completion etc., the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a "JMP" which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI", which retrieves the original Program Counter address from...
  • Page 182 HT66FM5440 Brushless DC Motor A/D Flash MCU If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt prioriy request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding prioriy request flag should be set before the device is in SLEEP or IDLE Mode. Legend Req�est Flag � no a�to reset in ISR Req�est Flag � a�to reset in ISR EMI a�to disabled in ISR Enable Bits Interr�pt...
  • Page 183 HT66FM5440 Brushless DC Motor A/D Flash MCU Legend Request Flag, no auto reset in ISR Request Flag, auto reset in ISR Enable Bits Interrupt Number Name Interrupt Multi-Function 0 Sub-name HALAF HALAE CMP0 HALBF HALBE Multi-Function 1 HALCF HALCE PWMD2...

  • Page 184: Hall Sensor Interr�Pts

    HT66FM5440 Brushless DC Motor A/D Flash MCU Hall Sensor Interrupts The Hall sensor interrupts are contained within the multi-function interrupt 0 thus sharing the same interrupt number. They are controlled by signal transistions on the Hall sensor noise filter output signals, FHA, FHB and FHC. After being configured with a desired interrupt priority level, a Hall sensor interrupt request will take place when the Hall sensor interrupt request flag, HALAF, HALBF or HALCF, and the corresponding interrupt priority request flag are set, which will occur when a transition appears on the Hall sensor noise filter outputs. To allow the program to branch to its prespective interrupt vector address, the global interrupt enable bit, EMI, the Hall sensor interrupt enable bit, HALAE, HALBE or HALCE, and the relevant interrupt priority enable bit, Int_prinE, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG0 register. If the Hall noise filter inputs are selected to come from the external input pins, H1, H2 and H3, which are pin-shared with I/O pins, they should be configured as an external Hall sensor input pins using the corresponding pin-shared control bits before the Hall sensor interrupt functions are enabled. When the interrupt is enabled, the stack is not full and either one of the Hall sensor interrupts occurs, a subroutine call to the relevant interrupt vector will take place. When the interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts and the related interrupt priority request flag, Int_prinF, will be automatically reset, but the Hall sensor interrupt request flags, HALAF, HALBF and HALCF, must be manually cleared by the application program. The INTEG0 register is used to select the type of active edge that will trigger the Hall sensor interrupt. A choice of either rising or falling or both edge types can be chosen to trigger a Hall...

  • Page 185: Comparator Interr

    HT66FM5440 Brushless DC Motor A/D Flash MCU Noise Filter Input Interrupt The external noise filter intput interrupt has its own independent interrupt number and is controlled by signal transitions on the NFIN pin. After being configured with a desired interrupt priority level, an external noise filtered intput interrupt request will take place when the relevant interrupt priority request flag, Int_prinF, is set, which will occur when a transition, whose type is chosen by the edge select bits NFIS1 and NFIS0 in the NF_VIL register, appears on the NFIN pin. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the relevant interrupt priority enable bit, Int_prinE, must first be set. As the external noise filter interrupt pin is pin-shared with I/O pin, it can only be configured as the noise filter interrupt pin if its interrupt priority enable bit has been set and the noise filter interrupt pin is selected by the corresponding pin- shared function selection bits. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the noise filter interrupt pin, a subroutine call to the noise filter interrupt vector will take place. When the interrupt is serviced, its interrupt priority request flag, Int_prinF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the NFIN pin will remain valid even if the pin is used as a noise filter interrupt input. The NF_VIL register is used to select the type of active edge that will trigger the noise filter interrupt. A choice of either rising or falling or both edge types can be chosen to trigger a noise filter...

  • Page 186: Pwm Mod�Le Interr�Pts

    HT66FM5440 Brushless DC Motor A/D Flash MCU Multi-function Interrupts Within the device there are up to seven Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the Hall sensor input interrupts, PWM period and duty interrupts, TM Interrupts, A/D Converter Interrupts, UART Interrupt, I C interrupt and LVD Interrupt. The interrupt sources within each Multi-function interrupt share the same interrupt number. After being configured with the desired interrupt priority level, a multi-function request will take place when its relevant interrupt priority request flag, Int_prinF, is set, which occurs when any of its included functions generate an interrupt request. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the relevant interrupt priority enable bit, must first be set. When the interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related interrupt priority request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the interrupt priority request flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts will not be automatically reset and must be manually reset by the application program. PWM Module Interrupts The PWM module has five interrupts, one PWM Period match interrupt known as PWMP and four PWM Duty match interrupts known as PWMDn (n=0~3). The PWMP and PWMD0~PWMD2 interrupts are contained in multi-function interrupt 1 and they share the same interrupt number. The...
  • Page 187 HT66FM5440 Brushless DC Motor A/D Flash MCU A/D Converter Interrupts The A/D Converter has three interrupts. One is the A/D converter boundary interrupt which is controlled by the comparison between the converted data registers, ADRH/ADRL or ISRHn/ ISRLn, and the boundary register pairs, ADHVDH/ADHVDL and ADLVDH/ADLVDL. It has its independent interrupt number. The other two are the A/D normal conversion interrupt, which is controlled by the end of an normal A/D conversion process, and the A/D auto-scan interrupt, which is controlled by the end of A/D auto-scan process. They are contained within the multi-function 2 and share the same interrupt number. After being configured with the desired interrupt priority level, the A/D converter boundary interrupt...
  • Page 188 HT66FM5440 Brushless DC Motor A/D Flash MCU UART Interrupt The UART interrupt is contained within the multi-function interrupt 7 sharing the same interrupt number with other interrupt sources in the same group. Several individual UART conditions can generate a UART interrupt. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. After being configured with the desired interrupt priority level, an UART interrupt request will take place when the UART interrupt request flag and the associated interrupt priority request flag are set, which happens when one of these conditions occurs. To allow the program to branch to the respective interrupt vector addresses, the global interrupt enable bit, EMI, interrupt priority enable bit, Int_ prinE and UART interrupt enable bit, UARTE, must first be set. When the interrupt is enabled, the stack is not full and any of these conditions are created, a subroutine call to the respective interrupt vector, will take place. When the UART interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the interrupt priority request flag will be also automatically cleared. As the UARTF flag will not be automatically cleared, it has to be cleared by the application program. However, the USR register flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART section. C Interrupt The I C interrupt is contained within the multi-function interrupt 7 sharing the same interrupt number with other interrupt sources in the same group. After being configured with the desired...

  • Page 189: Time Base Interr�Pt

    HT66FM5440 Brushless DC Motor A/D Flash MCU The Time Base clock source, f , originates from the internal clock source f /4 or f and then passes through a divider, the division ratio of which is selected by programming the TB1 and TB0 bits to obtain longer interrupt periods whose value ranges. TB1~TB0 1� ÷� ~� Time Base Interr�pt LIRC TBCK Time Base Interrupt TBC Register Name TBON TBCK — — — — — — — — — —...

  • Page 190: Interr�Pt Wake-�P F�Nction

    HT66FM5440 Brushless DC Motor A/D Flash MCU Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt priority request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins or a low power supply voltage may cause their respective interrupt priority request flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake- up function is to be disabled then the corresponding interrupt priority request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced. Where a certain interrupt, whether has its own request flag or not, has been configured to an interrupt priority level, then when the interrupt service routine is executed, as only the interrupt priority request flags, Int_prinF, will be automatically cleared, the individual request flag of the function needs to be cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE Mode, the wake up being generated when the relevant interrupt priority request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective interrupt priority request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine.

  • Page 191: Application Circuits

    Basing on the basic functional requirements mentioned above, this chapter will introduce how to use the HT66FM5440 to implement three-phase BLDC motor control. The BLDC motor system is mainly composed of the power circuit, MCU control circuit, motor driving circuit and voltage/current detection circuit, which will be introduced in detail in the hardware block diagram section. Functional Description All necessary and important functions required for brushless motor driving are integrated in the HT66FM5440 device and are coordinated by the BLDC motor control circuit. These functions include a 10-bit motor dedicated PWM, mask function, Hall sensor decoder and motor protection function, which combined with the OCP, capture timer, etc., provide the advantage of fast system protection. From the perspective of a control system, the main points of each function will be explained in the following. Hall Sensor/Sensorless For brushless motor operation, it is necessary to know the rotor position in order to provide correct operation phase. There are two methods to obtain the rotor position, which are determined by the...

  • Page 192: Hardware Block Diagram

    HT66FM5440 Brushless DC Motor A/D Flash MCU Detection and Protection Function Configuration Brushless motor driving requires instant detection for system voltage, current and speed. Once an abnormal situation occurs, the driving circuit must be immediately switched off to protect the peripheral hardware thus ensuring system security. The motor dedicated 16-bit capture timer contains motor stalling protection related configurations and can be used to monitor the motor speed. When the stalling situation occurs, the PWM signals will be directly switched off to prevent large motor static current from occurring.

  • Page 193: Hardware Circ�It

    HT66FM5440 Brushless DC Motor A/D Flash MCU 8. The Hall sensor decoder contains a total of 12 phase change logic registers for motor forward and backward directions. To implement the required phase change logic, these registers should be established in advance and can be controlled by the hardware decoder or by the HDCD register using the application program. And then use the HDCR register to implement motor operating, motor brake and motor direction control. 9. Motor operating current sampling is achieved using the current sampling resistor, R_Shunt. When the current flows through the register, a tiny voltage signal will be produced. This signal will first be amplified by the OPA in the OCP circuit, and then read by the ADC or checked by the DAC and CMP to detect the over current situation, which once occurred will trigger the corresponding over current protection measures. 10. Lastly, by coordinating all the relevant peripheral circuits the BLDC motor control circuit will configure the motor driving PWM signals and phase change logic according to the Hall sensor signals and protection signals to implement motor operating control. Hardware Circuit +DC Bus +DC Bus 78L05 +DC Bus DC Power +DC Bus P-N MOSFET +DC Bus Det_VDC +DC Bus...

  • Page 194: Instruction Set

    HT66FM5440 Brushless DC Motor A/D Flash MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 1 system clock cycle, therefore in the case of an 16MHz system oscillator, most instructions would be implemented within 0.0625μs and branch or call instructions would be implemented within 0.125μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required.

  • Page 195: Logical And Rotate Operation

    HT66FM5440 Brushless DC Motor A/D Flash MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such...

  • Page 196: Instruction Set Summary

    HT66FM5440 Brushless DC Motor A/D Flash MCU Instruction Set Summary The instructions related to the data memory access in the following table can be used when the desired data memory is located in Data Memory sector 0. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic Z� C� AC� OV� SC Add Data Memory to ACC ADD A�[m] Note Z� C� AC� OV� SC ADDM A�[m]...
  • Page 197 HT66FM5440 Brushless DC Motor A/D Flash MCU Mnemonic Description Cycles Flag Affected Data Move MOV A�[m] Move Data Memory to ACC None MOV [m]�A Move ACC to Data Memory Note None MOV A�x Move immediate data to ACC None Bit Operation CLR [m].i...

  • Page 198: Extended Instr�Ction Set

    HT66FM5440 Brushless DC Motor A/D Flash MCU Extended Instruction Set The extended instructions are used to support the full range address access for the data memory. When the accessed data memory is located in any data memory sections except sector 0, the extended instruction can be used to access the data memory instead of using the indirect addressing access to improve the CPU firmware performance. Mnemonic Description Cycles Flag Affected Arithmetic � Z� C� AC� OV� SC LADD A�[m]...
  • Page 199 HT66FM5440 Brushless DC Motor A/D Flash MCU Mnemonic Description Cycles Flag Affected Branch LSZ [m] Skip if Data Memory is zero � Note None LSZA [m] Skip if Data Memory is zero with data movement to ACC � Note None...

  • Page 200: Instruction Definition

    HT66FM5440 Brushless DC Motor A/D Flash MCU Instruction Definition Add Data Memory to ACC with Carry ADC A,[m] Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s) OV, Z, AC, C, SC ADD A,x...
  • Page 201 HT66FM5440 Brushless DC Motor A/D Flash MCU CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Operation Stack ← Program Counter + 1 Program Counter ← addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ← 00H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i ← 0 Affected flag(s) None CLR WDT...
  • Page 202 HT66FM5440 Brushless DC Motor A/D Flash MCU DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. Operation [m] ← [m] − 1 Affected flag(s) DECA [m] Decrement Data Memory with result in ACC Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC ← [m] − 1 Affected flag(s) Enter power down mode HALT Description This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO ← 0 PDF ← 1 Affected flag(s) TO, PDF INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1.
  • Page 203 HT66FM5440 Brushless DC Motor A/D Flash MCU NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC ″OR″ [m] Affected flag(s) Logical OR immediate data to ACC OR A,x Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC ″OR″ x Affected flag(s) ORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. Operation [m] ← ACC ″OR″ [m]...
  • Page 204 HT66FM5440 Brushless DC Motor A/D Flash MCU RLA [m] Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 Affected flag(s) None Rotate Data Memory left through Carry RLC [m] Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. Operation [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 Affected flag(s) RLCA [m] Rotate Data Memory left through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7...
  • Page 205 HT66FM5440 Brushless DC Motor A/D Flash MCU RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 Affected flag(s) SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − [m] − C Affected flag(s) OV, Z, AC, C, SC, CZ Subtract immediate data from ACC with Carry SBC A, x Description The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
  • Page 206 HT66FM5440 Brushless DC Motor A/D Flash MCU Set Data Memory SET [m] Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i ← 1 Affected flag(s) None SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ← [m] + 1 Skip if [m]=0 Affected flag(s) None SIZA [m]...
  • Page 207 HT66FM5440 Brushless DC Motor A/D Flash MCU SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − x Affected flag(s) OV, Z, AC, C, SC, CZ SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 ↔ [m].7~[m].4 Affected flag(s) None SWAPA [m]...
  • Page 208 HT66FM5440 Brushless DC Motor A/D Flash MCU TABRD [m] Read table (specific page) to TBLH and Data Memory Description The low byte of the program code (specific page) addressed by the table pointer pair (TBLP and TBHP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None ITABRD [m] Increment table pointer low byte first and read table to TBLH and Data Memory Description Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s)

  • Page 209: Extended Instruction Definition

    HT66FM5440 Brushless DC Motor A/D Flash MCU Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC LADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC LADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s)
  • Page 210 HT66FM5440 Brushless DC Motor A/D Flash MCU LCPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. Operation [m] ← [m] Affected flag(s) LCPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ← [m] Affected flag(s) LDAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] ← ACC + 00H or [m] ← ACC + 06H or...
  • Page 211 HT66FM5440 Brushless DC Motor A/D Flash MCU LMOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ← [m] Affected flag(s) None LMOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory. Operation [m] ← ACC Affected flag(s) None LOR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC ″OR″ [m] Affected flag(s) LORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
  • Page 212 HT66FM5440 Brushless DC Motor A/D Flash MCU LRR [m] Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 Affected flag(s) None LRRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 Affected flag(s) None LRRC [m] Rotate Data Memory right through Carry Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 Affected flag(s)
  • Page 213 HT66FM5440 Brushless DC Motor A/D Flash MCU LSDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ← [m] − 1 Skip if [m]=0 Affected flag(s) None LSDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC ← [m] − 1 Skip if ACC=0 Affected flag(s) None Set Data Memory LSET [m] Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH...
  • Page 214 HT66FM5440 Brushless DC Motor A/D Flash MCU LSNZ [m] Skip if Data Memory is not 0 Description If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Operation Skip if [m] ≠ 0 Affected flag(s) None LSUB A,[m] Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ LSUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ...
  • Page 215 HT66FM5440 Brushless DC Motor A/D Flash MCU LSZ [m].i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation Skip if [m].i=0 Affected flag(s) None LTABRD [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None LTABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None...

  • Page 216: Package Information

    HT66FM5440 Brushless DC Motor A/D Flash MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • The Operation Instruction of Packing Materials • Carton information Rev. 1.00 �16 ��ne ��� �01�...

  • Page 217: Pin Ssop (150Mil) O�Tline Dimensions

    HT66FM5440 Brushless DC Motor A/D Flash MCU 28-pin SSOP (150mil) Outline Dimensions &  " Dimensions in inch Symbol Min. Nom. Max. — 0.�36 BSC — — 0.154 BSC — 0.00� — 0.01� C’ — 0.390 BSC — — —...
  • Page 218 However� Holtek ass�mes no responsibility arising from the �se of the specifications described. The applications mentioned herein are used solely for the p�rpose of ill�stration and Holtek makes no warranty or representation that s�ch applications will be s�itable witho�t f�rther modification� nor recommends the �se of its prod�cts for application that may present a risk to h�man life d�e to...

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