Explore EP9134 User Manual

4 ports hdmi 1.3 splitter
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Explore reserves the right to make changes without further notice to any products herein to improve reliability, function or design.
Explore does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it
convey any license under its patent rights nor the rights of others. Explore products are not designed, intended, or authorized for use as
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4 Ports HDMI 1.3 Splitter
EP9134

User Guide

Revised: Nov. 23, 2009
Original Release Date: Aug. 27, 2007
Explore Confidential Proprietary
NON-DISCLOSURE AGREEMENT REQUIRED
V0.7
ug. 2
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27
2007
Exp
Exp
Explore
User Guide — EP9134_UG V0.7
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1

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Summary of Contents for Explore EP9134

  • Page 1: User Guide

    Explore reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Explore does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
  • Page 2: Revision History

    Fix Typo in DC Analogue Specification and Figure 2-3; on and F n and F Nov/23/2009 Ether Lai Fix typo in section 3.1, section 3.2.1, section 3.3.1.7 and table 3-1; 2.1, secti 1, secti Revise the thermal resistance; Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 3: Section 1 Introduction

    Section 1 Introduction 1.1 Overview The EP9134 is a 4-Port DVI/HDMI splitter with integrated HDCP decryption/encryption engines and is compliant with HDMI Rev 1.3a and HDCP Rev 1.2 specifications. The EP9134 receives DVI/HDMI inputs, process HDCP decryption and encryption and transmits the data to 4 DVI/HDMI ports. The chip uses an external EE to store the encrypted HDCP receiver/transmitter keys.
  • Page 4 User Guide — EP9134_UG V0.7 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 5: Section 2 Overview

    EXT_SWING Logics DVI/HDMI SDA1 IIC Slave HDCP Keys Receiver SCL1 SDA2 IIC Master SCL2 DVI/HDMI DVI/HDMI HDCP Keys HDCP Keys HDCP K HDCP K Transmitter Transmitter DVI/HDMI DVI/HDMI HDCP Keys HDCP Keys Transmitter Transmitter Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 6: Pin Diagram

    TX20+ SDA1 TX20- SCL2 AVDD SDA2 TX10+ VDDE TX10- VSSE AVSS reserved AVSS reserved 33 33 TX00+ SCL3 34 34 TX00- SDA3 AVDD M0_RDY _RDY TXC0+ HTPLG0 37 7 TXC0- HTPLG1 38 38 AVSS Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 7: Pin Description

    Differential Clock Output Pairs for transmitter port 0 TXC0+ Hot Plug Input HTPLG0 This pin is used to monitor the "HOT PLUG" signal for transmitter port 0. Note: This input is only 3.3V tolerant and has no internal debouncer circuit. Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 8 IN / NAME DESCRIPTION VDDE Digital Power, 3.3V VSSE Digital Ground VDD18 Core Power, 1.8V Core Ground AVDD Analog Power, 3.3V AVSS Analog Ground PVDD Analog Power for PLL, 3.3V PVSS Analog Ground for PLL Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 9 User Guide — EP9134_UG V0.7 Table 2-5 Power and Ground Pins IN / NAME DESCRIPTION _AVSS Analog Ground Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 10: Electrical Characteristics

    (wit rature (w 1 Guaranteed by design. design. design. DC Digital I/O Specifications (under normal operating conditions unless otherwise specified) Symbol Parameter Conditions Units High-level Input Voltage Low-level Input Voltage High-level Output Voltage Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 11 NOTES: 1. Guaranteed by design. 2. Jitter defines as per DVI 1.0 Specification, Section 4.6 Jitter Specification. 3. Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electronical Measurement Procedures Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 12 LOAD Differential Swing High-to-Low Transition Time = 50 ohm, LOAD = 300 ohm EXT_SWING Figure 2-3 Differential Output Timing Definition ng Defi g Defi AVDD = ABS{(TX+) - (TX-)} 80% V 50ohm 20% V Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 13: Section 3 Detail Functional Descriptions

    SB B AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Calling Address Read/ Repeated New Calling Address Stop Read/ Signal Start Signal Write Write Signal Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 14: Basic Protocol

    "0" means write to device. If the transmitted slave address matches the address of the device, the EP9134 the he add sends the acknowledge by asserting SDA Low on the ninth SCL pulse. Else, the EP9134 does not assert the pulse. El pulse.
  • Page 15 Slave Address Byte (R/W = HIGH) • Data Byte from Base Address • Data Byte from (Base Address + 1) • Data Byte from (Base Address + 2) • ............• Data Byte from (Base Address + N) Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 16 User Guide — EP9134_UG V0.7 • STOP Signal 3.3 Description of the Control Registers The following table shows all the control registers of the DVI/HDMI Transmitter EP9134: Table 3-1 IIC Control Registers Addr Mode Bit7 Bit6 Bit5 Bit4 Bit3 Bit2...
  • Page 17 TX_M0_4 TX_M0_5 TX_M0_6 TX_M0_7 TX_M0_8 RX_M0_RDY RX_M0_1 RX_M0_2 RX_M0_3 RX_M0_4 M0_4 RX_M0_5 RX_M0_ RX_M0 RX_M0_6 M0_6 M0_6 RX_M0_7 RX_M0 RX_M0 RX_M0_8 RX_Bcaps RX_Bstatus[7:0] RX_Bstatus[11:8] RX_SHA-1_HASH_0 RX_SHA-1_HASH_1 RX_SHA-1_HASH_2 RX_SHA-1_HASH_3 RX_SHA-1_HASH_4 RX_SHA-1_HASH_5 RX_SHA-1_HASH_6 RX_SHA-1_HASH_7 RX_SHA-1_HASH_8 RX_SHA-1_HASH_9 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 18: Register Descriptions

    This register is recommended to be programmed with the value 0x09 after the power on sequence if the mmend mmend expected supported TMDS clock frequency is up to 225MHz (1080p, 12 bits deep color). The TMDS_SAMP[0] is fixed to 1 always. Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 19 TMDS clock frequency is up to 225MHz (1080p, 12 bits deep color). Also, if long cable is supported, the recommended setting will be 0xA0. The transmitter will consume more current if the control bit TX_TERM is set to 1. Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 20 The 4 transmitter ports share the same IIC register address. This register is used to select which transmitter port is addressed for IIC access. 00 = Port 0 is selected 01 = Port 1 is selected 10 = Port 2 is selected 11 = Port 3 is selected Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 21 The TX_HTPLG bit indicates the hot plug status at the selected transmitter port. 1 = Hot Plug detected at the selected transmitter port. 0 = Hot Plug not detected at the selected transmitter port. Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 22 DVI mode (TX_HDMI = 0). TX_HDMI — Set HDMI mode for the selected transmitter port 1 = Put the selected transmitter port working in HDMI mode. This is valid only if the receiver is receiving HDMI signal. Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 23 0 = First Ri value is not available for the selected transmitter port. alue is lue is TX_ENC_EN — Transmitter ENC Enable 1 = Enable HDCP encryption for the selected transmitter port. 0 = Disable HDCP encryption the selected transmitter port. Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 24 Byte 5 should be written last to the receiver, as it will trigger authentication there. These 5 registers should not be read until TX_AKSV_RDY bit is 1. Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 25 M0 calculation. e M0 0 calcu 0 calcu ulat 3.3.1.15 RX_M0 Registers ($41 ~ $48) - RX_M0_1 ~ RX_M0_8 Table 3-16 RX_M0 Registers $41 ~ $48 RX_M0_1[7:0] ~ RX_M0_8[7:0] Reset: Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 26 FAST_REAUTHENTICATION bit. HENTIC HENTI 3.3.1.17 RX_Bstatus Registers ($51 ~ $52) Table 3-18 RX_Bstatus (LSB, [7:0]) Register DEVICE_CNT[6:0] DEV_EXCEED Reset: Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 27 0x60 RX_SHA-1_HASH_0 0x61 RX_SHA-1_HASH_1 0x62 RX_SHA-1_HASH_2 0x63 RX_SHA-1_HASH_3 0x64 RX_SHA-1_HASH_4 0x65 RX_SHA-1_HASH_5 0x66 RX_SHA-1_HASH_6 0x67 RX_SHA-1_HASH_7 0x68 RX_SHA-1_HASH_8 0x69 RX_SHA-1_HASH_9 0x6A RX_SHA-1_HASH_10 0x6B RX_SHA-1_HASH_11 0x6C RX_SHA-1_HASH_12 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 28 :8] ] 0x82 + 5 * (X-1) KSVx[23:16] KSVx KSVx [23:16] 23:16] 0x83 + 5 * (X-1) KSVx[31:24] SVx[3 Vx[31:2 31:2 0x84 + 5 * (X-1) KSVx[39:32] KSVx[3 KSVx[ NOTE: X = downstream device count Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...
  • Page 29: Appendix A Package

    User Guide — PACKAGE Appendix A Package Figure A-1 EP9134 Footprint Diagram DETAIL "A" EP9134 date code lot number 7.11 REF 0.08 Footprint Variations (mm) ons (mm SYMBOLS MIN. NOM. MAX. NOTES: 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE 0.05...
  • Page 30 User Guide — PACKAGE Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED...

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