Lattice ECP2 Series Usage Manual page 10

The estimated time for configuration can be calculated by dividing the bitstream size (in bits) from Table 15-4 by the
CCLK frequency. The CCLK frequency can be set using the global preferences tab within the ispLEVER Design
Planner or the Spreadsheet View (Global Preferences tab) in Diamond. For more information on setting the CCLK
frequency, please see the Master Clock section and the D[0]/SPIFASTN pin section of this document.
When downloading an encrypted bitstream file to the LatticeECP2/M S-Series devices, the user must adhere to the
appropriate conditions for the CCLK signal. These conditions are shown in TN1109,
Encryption Usage Guide.
Table 15-6. SPI Serial Flash Vendor List
One FPGA, One SPI Flash
The simplest SPI configuration consists of one SPI Serial Flash connected to one LatticeECP2/M, as shown in
Figure 15-1. This is also the recommended method for use when downloading an encrypted bitstream file to the
LatticeECP2/M S-Series devices.
Figure 15-1. One FPGA, One SPI Serial Flash
Multiple FPGA, One SPI Flash
With a sufficiently large SPI Flash multiple FPGAs can be configured as shown in Figure 15-2. The first FPGA is
configured in SPI mode; the following FPGAs are configured in Slave Serial mode.
Vendor
ST Microelectronics
Winbond
Silicon Storage Technology
Spansion
Atmel
NexFlash
Macronix
Note: This is not meant to be an exhaustive list and may be updated
from time to time.
SPI Serial
Flash
C
Q
D
/CS
SPIFASTN
PROGRAMN
DONE
LatticeECP2/M sysCONFIG Usage Guide
Part Number
M25Pxx
W25Pxx
SST25VFxx,
SST25LFxx
S25FLxx
AT25Fxx
NX25Pxx
MX25Lxx
Lattice FPGA
SPI Mode
CCLK
D7/SPID0 DOUT
BUSY/SISPI
DI/CSSPI0N
CFG2
CFG1
D0/SPIFASTN
CFG0
15-10
LatticeECP2/M Configuration