Philips VE8 Service Manual page 16

EN 16 5. Q529.1A LA
Important remark ; the appearance of the +12V
will start the +1V2 DCDC converter automatically
Detect2 should be polled on the standard 40ms
interval and startup should be continued when
detect2 becomes high.
No
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Service Modes, Error Codes, and Fault Finding
Off
Mains is applied
Standby Supply starts running.
All standby supply voltages become available .
st-by µP resets
Initialise I/O pins of the st-by µP:
- Switch reset-AVC LOW (reset state)
- Switch WP-NandFlash LOW (protected)
- Switch reset-system LOW (reset state)
- Switch reset-5100 LOW (reset state)
- Switch reset-Ethernet LOW (reset state)
- Switch reset-ST7100 LOW (reset state)
- keep reset-NVM high, Audio-reset and Audio-Mute-Up HIGH
start keyboard scanning, RC detection. Wake up reasons are
off.
Switch ON Platform and display supply by switching
LOW the Standby line.
+12V, +/-12Vs, AL and Bolt-on power
is switched on, followed by the +1V2 DCDC converter
Detect2 high received
within 1 second?
Yes
Supply-fault I/O
High?
Yes
Enable the DCDC converter for +3V3 and
+5V. (ENABLE-3V3)
Wait 50ms
Supply-fault I/O
High?
yes
Detect-1 I/O line
High?
Yes
Enable the supply fault detection
algorithm
Set I²C slave address
of Standby µP to (A0h)
Switch LOW the RESET-NVM line to allow access to NVM. (Add a
2ms delay before trying to address the NVM to allow correct NVM
initialization , this is not issue in this setup , the delay is automatically
covered by the architectural setup)
Switch HIGH the WP-NandFlash to
allow access to NAND Flash
Release Reset-PNX5100.
PNX5100 will start booting.
Wait 10ms (minimum) to allow the bootscript
of the PNX5100 to configure the PCI arbiter
Detect EJTAG debug probe
(pulling pin of the probe interface to
ground by inserting EJTAG probe)
EJTAG probe
connected ?
No
No Cold boot?
Yes
Release AVC system reset Release AVC system reset
Feed warm boot script Feed cold boot script
Figure 5-4 "Off" to "Semi Stand-by" flowchart (part 1)
Stand by or
Protection
If the protection state was left by short circuiting the
SDM pins, detection of a protection condition during
startup will stall the startup. Protection conditions in a
playing set will be ignored. The protection mode will
not be entered.
- Switch Audio-Reset high.
It is low in the standby mode if the standby
mode lasted longer than 10s.
Power-OK error:
No Layer1: 3
Layer2: 16
Enter protection
1V2 DCDC or class D error:
No Layer1: 2
Layer2: 19
Enter protection
This enables the +3V3 and
+5V converter. As a result,
also +5V-tuner, +2V5, +1V8-
PNX8541 and +1V8-PNX5100
become available.
Delay of 50ms needed because of the latency of the detect-1 circuit.
This delay is also needed for the PNX5100. The reset of the
PNX5100 should only be released 10ms after powering the IC.
3V3 / 5V DCDC or class D error:
No Layer1: 2
Layer2: 11
Enter protection
Detect-2 I/O line Disable 3V3, switch standby
No No
High? line high and wait 4 seconds
Yes
Added to make the system more robust to
power dips during startup. At this point the
Voltage output error: regular supply fault detection algorithm which
normally detects power dips is not up and
Layer1: 2
running yet.
Layer2: 18
Enter protection
This will allow access to NVM and
NAND FLASH and can not be done
earlier because the FLASH needs to
be in Write Protect as long as the
supplies are not available.
Before PNX8541 boots, the PNX5100 should have
set its PCI arbiter (bootscript command). To allow
this, approx. 1ms is needed. This 1ms is extended
to 10ms to also give some relaxation to the supplies .
An EJTAG probe (e.g. WindPower ICE probe) can
be connected for Linux Kernel debugging
purposes.
Yes
Release AVC system reset
Feed initializing boot script
disable alive mechanism
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The supply-fault line is a
combination of the DCDC
converters and the audio
protection line.
I_17660_125a.eps
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