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COBHAM GR716 Advanced Data Sheet And User’s Manual

Leon3ft microcontroller

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GR716

LEON3FT Microcontroller

2019 Advanced Data Sheet and User's Manual

The most important thing we build is trust

Features

• Fault-tolerant SPARC V8 processor with 31 register

windows, 192KiB EDAC protected tightly coupled

memory and support for reduced instruction set.

• Double precision IEEE-754 floating point unit

• Advanced on-chip debug support unit

• Memory protection units

• 8-bit external PROM/SRAM interface with BCH EDAC

protection

• Boot from external SRAM/PROM, SPI or I

protected by EDAC and dual memory redundancy

• SpaceWire interface with time distribution support

• SPI for Space master and slave interface

• MIL-STD-1553B interface

• CAN 2.0B controller interface

• PacketWire with CRC acceleration support

• On-chip 12-bit DAC and two 11-bit ADC

• Programmable PWM interface

2

• UARTs, SPI, I

C, GPIO, Timers with Watchdog, Inter-

rupt controller, Status registers, UART debug, etc.

• Configurable I/O switch matrix

Floating

Debug

Integer

Point

Support

Unit

Unit

Local

Local

Dual-port

AMBA

Dual-port

Instruction

Interface

RAM

Main bus

FTMCTRL

SPIMCTRL

IRQ Control

UART

I2CMST /

Timers

I2CSLV

AHBSTAT

SPICTRL

GRADCDAC

GRGPIO

On-chip DAC

GRPULSE

On-chip ADC

GRPWM

On-chip

Brownout

Oscillator

On-chip

LDO

Power-on

PLL

GR716-DS-UM, May 2019, Version 1.29

2

C memory

LEON3

UART

Statistics

Dbg Link

Unit

Unit

Debug bus

AHB2AHB

Bridge

Data

DMA bus

RAM

DMA

AHB2AHB

Controller

Bridge

APBCTRL

AHBROM

Bridges

MEMPROT

1553B

CLKGATE

SpaceWire

GPREG

I2C to AHB

LSTAT

SPI to AHB

GRPWRX

(MAP)

GRPWTX

GRCAN

Detector

AHB

reset

UART

Description

The GR716 device is a fault-tolerant LEON3

SPARC V8 processor with various communication

interfaces and on-chip ADC, DAC, Power-on-

Reset, Oscillator, Brown-out detection, LVDS

transceivers, regulators to support single 3.3V

supply, ideally suited for space and other high-rel

applications.

Specification

• System frequency up-to 50 MHz

• SpaceWire links up-to 100 Mbps

• CQFP132 hermetically sealed ceramic package

• Total Ionizing Dose (TID) up to 100 krad (Si)

• Single-Event Latch-up Immunity (SEL) to LET

> 118 MeV-cm

• Single-Event Upset (SEU) below 10

device and day in space environment (TBC)

• Support for single 3.3V supply

Applications

AHB

The GR716 microcontroller is an advanced microcontrol-

Trace

ler, targeting high reliability space and aeronautics appli-

cations.

Support for many different standard interfaces makes

the GR716 microcontroller ideal for supervision, monitor-

ing and control in a satellite, such as:

• propulsion system control

• sensor bus control

• robotics applications control

• simple motor control

• mechanism control

• power control

• particle detector instrumentation

• radiation environment monitoring

• thermal control

• antenna pointing control

• AOCS / GNC (Gyro, IMU, MTM)

• remote terminal unit control

• simple instrument control

• wireless networking

Availability

The GR716 microcontroller is currently available as engi-

neering samples. Contact Cobham Gaisler for informa-

tion on flight model schedule.

2

mg

-6

errors per

www.cobham.com/gaisler

TH

Table of Contents

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Summary of Contents for COBHAM GR716

Page 1 GRPWRX On-chip DAC GRPULSE (MAP) • wireless networking On-chip ADC GRPWM GRPWTX Availability The GR716 microcontroller is currently available as engi- On-chip Brownout GRCAN Oscillator Detector On-chip neering samples. Contact Cobham Gaisler for informa- Power-on tion on flight model schedule.
Page 2: Table Of Contents
Reset............................70 IO Reset ..............................70 Technical notes........................71 GRLIB AMBA plug&play scanning ..................... 71 Software portability..........................71 System Startup Status and General Configuration..............72 Configuration Registers......................... 72 Boot Strap information register ......................77 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 3 17.2 Functional Description ........................137 UART Serial Interface ......................140 18.1 Overview ............................. 141 18.2 Operation ............................. 141 18.3 Baud-rate generation ........................... 142 18.4 Loop back mode ..........................143 18.5 FIFO debug mode..........................143 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 4 Transmission............................214 25.6 Reception............................. 217 25.7 Global reset and enable ........................220 25.8 Registers .............................. 221 25.9 Memory mapping ..........................230 Clock gating unit (Primary) ....................232 26.1 Overview ............................. 232 26.2 Operation ............................. 232 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 5 Operation ............................. 297 33.3 Link interface ............................298 33.4 Time-code distribution ........................301 33.5 Interrupt distribution..........................302 33.6 Receiver DMA channels........................304 33.7 Transmitter DMA channels ......................... 310 33.8 RMAP..............................313 33.9 AMBA interface ..........................317 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 6 Operation ............................. 421 42.3 Registers .............................. 423 SPI to AHB bridge ....................... 428 43.1 Overview ............................. 428 43.2 Transmission protocol ......................... 429 43.3 System clock requirements and sampling ................... 430 43.4 SPI instructions............................ 430 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 7 51.5 State at handover to application software.................... 506 51.6 Boot source requirements........................507 51.7 Protection schemes ..........................507 Electrical description ......................510 52.1 Absolute maximum ratings ......................... 510 52.2 Recommended operating conditions ....................512 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 8 Pin assignment............................. 540 53.3 Mechanical package drawings......................544 Ordering information ......................546 Errata............................ 547 55.1 Overview ............................. 547 55.2 Errata description ..........................547 Features ..........................549 56.1 Overview ............................. 549 56.2 Feature description ..........................549 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 9: Introduction
GR716 Introduction Scope This document is the advanced data sheet and user’s manual for the GR716 LEON3FT microcontrol- ler. The GR716 microcontroller has been developed in an activity initiated by the European Space Agency under ESTEC contract 40001117749/14/NL/AK. Data sheet limitations Note that this document is an advanced data sheet: •...
Page 10: Document Revision History
GR716 Document revision history Change record information is provided in table 1. Table 1. Change record Version Date Note 1.29 May 2019 First public release GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 11: Acronyms
Megabyte, 10 bytes Mebibyte, 2 bytes, unit defined in IEEE 1541-2002 PROM Programmable Read Only Memory Random Access Memory Single Event Effects SEL/SEU/ Single Event Latchup/Upset/Transient SPARC Scalable Processor ARChitecture Software UART Universal Asynchronous Receiver/Transmitter GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 12: Definitions
Unless a radix is explicitly declared, the number should be considered a decimal. 1.8.3 Data types Byte (BYTE) 8 bits of data Halfword (HWORD) 16 bits of data Word (WORD) 32 bits of data GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 13: Register Descriptions
Readable and writable. Special condition for write, described in textual description of field. Write-clear. Readable, and cleared when written with a 1 Readable, and writable through compare-and-swap. Only applies to SpaceWire Plug-and-Play regis- ters. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 14: Architecture
Power-on reset UART Figure 1. GR716 block diagram The microcontroller is a single core LEON3FT SPARC V8 processor, with advanced interface proto- cols, that has been optimized for real-time systems and deterministic software execution. Features such as SPARC V8E Alternate Window Pointer, interrupt zero jitter latency, SPARC V8E multiply step instructions and the possibility to run software (including interrupt handlers) from local RAM are supported to increase the determinism and responsiveness in the system.
Page 15: Key Features
Timer units with seven 32-bit timers including watchdog. Multiple bus structures for non-intrusive debug, DMA transfers and memory scrubbers. Atomic access support for all APB registers (AND, OR, XOR, Set&Clear). GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 16 132-lead CQFP, 0.635 mm pitch, 24mm x 24mm, hermetically sealed with flat pins and insulating lead-frame for customer trim and form. • Software Supported by standard tools-chains and debug tools provided by Cobham Gaisler. Tool- chains, simulators and debug software is available at www.cobham.com/gaisler. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 17 Support for external clock source for the system, SpaceWire, SPI4S, 1553 and PWM. Automatic oscillator shutdown if oscillator not used. Individual programmable brown-out levels. Protection for erroneous I/O configuration during power-up and power-down. Programmable LDO output level for low power mode. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 18: Digital Architecture Overview
AMBA access with an AMBA ERROR response. Four areas can be protected on the system bus and four areas can be protected on the DMA bus. Exclusive write permission can be enforced for individual APB peripherals to protect interfaces from erroneous writes during normal operations. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 19 The scrub rate can be con- figured and should be set to an acceptable rate for the mission. The scrubber access will not block the AMBA bus since masters and slaves on the main system bus support split transactions. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 20 When the selected interrupt line is asserted, software will save the current value of the interrupt time- stamp counter into the Interrupt Assertion Timestamp register. When the processor acknowledges the interrupt, the Interrupt Timestamp Control register will be set and the current value of the timestamp GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 21 Custom boot options are supported via bootstrap options to bypass the internal boot ROM code. The LEON3FT microcontroller can be configured to boot directly from external ROM, external SRAM, external SPI Memory or internal NVRAM in package (GR716 with internal NVRAM is currently not available).
Page 22 2.2.8 Pin sharing A I/O switch matrix allows most of the GR716 microcontroller pins functionality to be configurable and to be shared between several peripherals. The I/O switch matrix provides a flexible solution where enabling one core changes the I/O switch matrix so that the current core gets connected to I/O pads.
Page 23 See section 41 for more information about the LEON3 statistics unit. The GR716 microcontroller have one dedicated Serial Debug interface. The Serial Debug unit is directly connected to the AMBA debug bus. The Serial Debug unit have a unique AMBA address described in chapter 2.11.
Page 24 Connection for blocking write access to pro- memory controller, tected areas. Protection unit grants or denies NVRAM controller, local the ongoing AMBA access via the memory instruction memory and protection bus. local data memory GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 25 ". Bus is only passively lis- from REQ/GNT signals tening. TRACE From AMBA infrastructure Main and DMA AMBA buses are routed to the to Trace buffer trace buffer. Trace buffer is passively listening to signals. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 26: Analog Architecture Overview
VDD_CORE goes above its reset threshold level. The Brownout detectors are intended to be used as pre-warnings to the GR716 microcontroller that some supply volt- age(s) has started to go down, so the CPU can perform a well-controlled system shutdown before any reset detectors are activated.
Page 27 PCB fulfill- ing the electrical specification of this input. The PLL reference-clock input is allowed to be asynchro- nous to any other clocks in the GR716 microcontroller. 2.3.4 Voltage reference The reference blocks are supplied by VDDA_REF.
Page 28 This should of course be checked in all application implementations with the GR716 microcontroller, but is especially important to do carefully when the LDO is in use at the same time as core current can be high.
Page 29 2.3.8 Temperature Sensor There is a temperature sensor implemented on the GR716 microcontroller chip. Its output signal is a monotonic voltage versus temperature, and is measured by the on-chip ADC in the same way as any other MUX channel. Its output is not threshold detected or used in any other on-chip block, so if a chip over-temperature protection is desired, the user needs to measure the sensor and take adequate actions in the system application at hand.
Page 30: Signal Overview
GR716 Signal Overview The GR716 microcontroller has 64 external general purpose user input and outputs, 6 LVDS trans- ceivers and dedicated SPI memory interface. Almost all 64 external inputs and outputs and LVDS transceivers have multiple functionality. Functionality is selected by the application software during startup and configuration.
Page 31 Table 7. IO configuration option table 1 GPIO0 UART_RTSN0 MEM_ADDR0 1553_RXENA PWRX_BUSYN CAN_TX0 SPIM_SLV1 ADC-DAC_A0 PWM0 GPIO1 UART_CTNS0 MEM_ADDR1 1553_TXA PWRX_CLK CAN_RX0 SPIM_SCK1 ADCDAC_A1 PWM1 GPIO2 UART_TX0 MEM_ADDR2 1553_RXA PWRX_DATA CAN_SEL0 I2CM_SDA0 SPIM_MOSI1 ADCDAC_A2 PWM2 GPIO3 UART_RX0 MEM_ADDR3 1553_RXNA PWRX_ABORT CAN_RX1 I2CM_SCL0 SPIM_MISO1...
Page 32 GPIO40 UART_CTSN4 1553_RXNA PWRX_ABORT I2CS_SCL1 SPI_SLV0_0 ADC3 ADC_RC PWM3 GPIO41 UART_CTSN5 RAM_CSN2 1553_TXNA PWRX_BYN CAN_TX0 I2CM_SDA0 SPI_SCK0 ADC4 DAC_WR PWM0 GPIO42 UART_RTSN5 RAM_CSN3 1553_TXINHA PWRX_RDY CAN_RX0 I2CM_SCL0 SPI_MISO0 ADC5 ADC_CS PWM1 GPIO43 UART_TX5 ROM_CSN0 1553_RXB PWTX_VALID CAN_SEL0 I2CS_SDA0 SPI_MOSI0 ADC6 ADC_RDY PWM2 GPIO44...
Page 33: I/O Switch Default Configurations For Bootstraps
Functional description GPIO[53] SPI Slave Clock interface GPIO[54] MISO SPI Master input Slave output interface GPIO[55] MOSI SPI Master output Slave input interface GPIO[56] SPI Slave Select interface Note 1: Interface uses CMOS type interface GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 34 ADDR[5] GPIO[6] ADDR[6] GPIO[7] ADDR[7] GPIO[8] ADDR[8] GPIO[9] ADDR[9] GPIO[10] ADDR[10] GPIO[11] ADDR[11] GPIO[12] ADDR[12] GPIO[13] ADDR[13] GPIO[14] ADDR[14] GPIO[15] ADDR[15] GPIO[16] ADDR[16] GPIO[17] ADDR[17] GPIO[18] ADDR[18] GPIO[33] Output interface GPIO[34] Writen enable interface GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 35 ADDR[4] GPIO[5] ADDR[5] GPIO[6] ADDR[6] GPIO[7] ADDR[7] GPIO[8] ADDR[8] GPIO[9] ADDR[9] GPIO[10] ADDR[10] GPIO[11] ADDR[11] GPIO[12] ADDR[12] GPIO[13] ADDR[13] GPIO[14] ADDR[14] GPIO[15] ADDR[15] GPIO[16] ADDR[16] GPIO[17] ADDR[17] GPIO[18] ADDR[18] Output interface Writen enable interface GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 36: I/O Switch Matrix Options, Considerations And Limitations
1 chip-select i.e. the system can assign 4 pins to another system interface. There is also a potential saving to make if the functionality ’bus ready’ and ’bus exception’ isn’t used. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 37: I/O Switch Matrix Pin Validation Script
I/O switch configuration registers. The intention of the script is to help the user of the GR716 microcontroller to validate a configuration according to table 2.6 and to quickly setup a system for test. The script should not be used for any other purpose than test and debug of systems using the GR716 microcontroller.
Page 38 // C constant const int iomx[8] = { 0x00001111, 0x11110000, 0x00002222, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}; grmon2> GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 39 The script is provided "as-is" and only checks for valid configurations according to pre-defined pin allocations for specific interfaces defined in the script. The script will not check pins placement or direction selected is correct according to target system or PCB board. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 40: I/O Switch Matrix Scenario Examples
GR716 I/O switch matrix scenario examples This chapter gives examples of how to configure the GR716 microcontroller and the I/O mux for fol- lowing scenarios: • Sensor / Actuator Node using external SRAM to store data • Bus bridge using external SRAM to store data •...
Page 41 SYS.CFG.GP7.GP2 1553_RXNB 1553_RXNB CAN_TX0 ADCDAC_D9 ADCDAC_D9 SYS.CFG.GP7.GP3 1553_RXENB ADCDAC_D10 CAN_RX0 ADCDAC_D10 ADCDAC_D10 SYS.CFG.GP7.GP4 1553_TXB ADCDAC_D11 CAN_SEL0 ADCDAC_D11 ADCDAC_D11 SYS.CFG.GP7.GP5 1553_CLK ADCDAC_D12 CAN_RX1 ADCDAC_D12 ADCDAC_D12 SYS.CFG.GP7.GP6 1553_TXNB 1553_TXNB CAN_TX1 CAN_TX1 SYS.CFG.GP7.GP7 1553_TXINHB 1553_TXINHB CAN_SEL1 CAN_SEL1 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 42 In table 22 two example of I/O configurations for Node bus bridge are shown. Note that SpaceWire is assumed to be connected on dedicated pins see BRIDGE.CFG1 in table 22. If SpaceWire redundancy is required configuration BRIDGE.CFG2 in table 22 should be used. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 43 1553_CLK 1553_CLK SYS.CFG.GP6.GP0 1553_TXNB 1553_TXNB SYS.CFG.GP6.GP1 1553_TXINHB 1553_TXINHB SYS.CFG.GP6.GP2 SYS.CFG.GP6.GP3 SYS.CFG.GP6.GP4 SYS.CFG.GP6.GP5 SYS.CFG.GP6.GP6 SYS.CFG.GP6.GP7 SYS.CFG.GP7.GP0 SYS.CFG.GP7.GP1 SYS.CFG.GP7.GP2 CAN_TX0 CAN_TX0 SYS.CFG.GP7.GP3 CAN_RX0 CAN_RX0 SYS.CFG.GP7.GP4 CAN_SEL0 CAN_SEL0 SYS.CFG.GP7.GP5 CAN_RX1 CAN_RX1 SYS.CFG.GP7.GP6 CAN_TX1 CAN_TX1 SYS.CFG.GP7.GP7 CAN_SEL1 CAN_SEL1 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 44 Connects to spacecraft bus either via MIL-1553B or SpaceWire, and on the other side to node bus via CAN. In table 23 two example of I/O configurations for Node bus bridge are depicted. Note that the external SPI configuration ROM and SpaceWire are connected on dedicated pins. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 45 1553_CLK 1553_CLK SYS.CFG.GP6.GP0 1553_TXNB 1553_TXNB SYS.CFG.GP6.GP1 1553_TXINHB 1553_TXINHB SYS.CFG.GP6.GP2 SYS.CFG.GP6.GP3 SYS.CFG.GP6.GP4 SYS.CFG.GP6.GP5 SYS.CFG.GP6.GP6 SYS.CFG.GP6.GP7 SYS.CFG.GP7.GP0 SYS.CFG.GP7.GP1 SYS.CFG.GP7.GP2 CAN_TX0 CAN_TX0 SYS.CFG.GP7.GP3 CAN_RX0 CAN_RX0 SYS.CFG.GP7.GP4 CAN_SEL0 CAN_SEL0 SYS.CFG.GP7.GP5 CAN_RX1 CAN_RX1 SYS.CFG.GP7.GP6 CAN_TX1 CAN_TX1 SYS.CFG.GP7.GP7 CAN_SEL1 CAN_SEL1 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 46: Cores
SPI for space slave 0x01 0x0A7 The information in the last two columns is available via plug’n’play information in the system and is used by software to detect peripherals and to initialize software drivers. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 47: Memory Map
CCSDS TDP / SpaceWire I/F 0x8000C000 - 0x8000C1FF GRGPRBANK IO Mux configuration register 0x8000D000 - 0x8000D0FF GRGPREG Test register and system control register 0x8000E000 - 0x8000E0FF AHBUART Slave UART configuration for remote access 0x8000F000 - 0x8000F0FF GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 48 GRGPIO 0x8030C000 - 0x8030CFFF General Purpose I/O port 32 to 64 GRGPIO 0x8030D000 - 0x8030DFFF I2C-master 0 I2CMST 0x8030E000 - 0x8030E0FF I2C-master 1 I2CMST 0x8030F000 - 0x8030F0FF PWM generator 0 GRPWM0 0x80310000 - 0x803100FF GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 49 On-chip DAC interface 3 0x8040B000 - 0x8040B0FF I2C-slave 0 I2CSLV 0x8040C000 - 0x8040C0FF I2C-slave 1 I2CSLV 0x8040D000 - 0x8040D0FF SPI for Space Slave GRSPI4 0x8040E000 - 0x8040E0FF PWM generator 1 GRPWM1 0x80410000 - 0x804100FF GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 50 2.12 Atomic access This chapter describes how atomic read and modify operations are performed in the GR716 micro- controller. The GR716 microcontroller supports atomic read-modify-write operations in hardware by mirroring the address space of the peripheral and internal data memory for different atomic opera- tions.
Page 51 += 0x80000; // Add atomic offset for op. b |= (((unsigned int) addr & 0x00000FFF) << 1); // Align local address to 0x8 __asm__ volatile ("std %1, [%0]"::"r"(b),"r"(a)); // Insert double store op GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 52: Interrupts
ADC interrupt 0 ADC1 on-chip ADC interrupt 1 ADC2 on-chip ADC interrupt 2 ADC3 on-chip ADC interrupt 3 ADC4 on-chip ADC interrupt 4 ADC5 on-chip ADC interrupt 5 ADC6 on-chip ADC interrupt 6 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 53 GPTIMER1 Interrupt 7 from timer block 1 GRGPIOSEQ0 GPIO sequencer 0 GRGPIOSEQ1 GPIO sequencer 1 PLL interrupt, Power On Reset and Brown Out interrupt AHBSTAT/DLRAM, AHB status, Scrubbers and I/O mux interrupt ILRAM/GRGPRBANK/ MEMSCRUB GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 54: Signals
& SPIM_SEL. GPIO[0] Determines the use of EDAC for external boot RAM when the GR716 microcontroller shall boot from external memory. Set to low for enabling EDAC and to high for disabling EDAC. Determine the use of PLL when the GR716 microcontroller shall boot via a remote source.
Page 55 "11" - UART remote access Note 1: User should use weak pull-up/pull-downs for configuration of the GR716 microcontroller. A weak resistor is defined as resistor which require low current from the drive circuitry. The resistance should be greater or equal to 10K ohm.
Page 56 MHz input clock after initialization of the pro- cessor and internal mem- ory test. high high high Enable SpaceWire remote access using the clock direct from the SpaceWire input pin after initialization of the pro- cessor GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 57 Note 5: Disable internal PLL by bootstrap signal to high. When bypassing the internal PLL the speed will be set to input frequency of the SpaceWire clock. The PLL will be in power down mode. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 58 0x02000000. Processor or internal memory is initialized after reset when this option is used. Note 7: Enable memory test. Memory test configuration can be used in combination with all other options. Memory test have no affect when internal boot ROM is bypassed. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 59 0x40000000. Processor or internal memory is initialized after reset when this option is used. Note 7: Enable memory test. Memory test configuration can be used in combination with all other options. Memory test have no affect when internal boot ROM is bypassed. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 60 0x01000000. Processor or internal memory is initialized after reset when this option is used. Note 7: Enable memory test. Memory test configuration can be used in combination with all other options. Memory test have no affect when internal boot ROM is bypassed. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 61: Configuration For Flight
Enable memory test. Memory test configuration can be used in combination with all other options. Configuration for flight To achieve the intended radiation tolerance in flight, certain bootstrap signals must be held at a fixed configuration: • DSU_EN must be held low (disabling debug interfaces) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 62: Complete Signal List
Analog LVDS Supply Analog VDDA_ADC Analog ADC supply Analog VSSA_ADC Analog ADC ground Analog VDDA_DAC Analog DAC supply Analog VSSA_DAC Analog DAC ground Analog VDDA_PLL Analog PLL supply Analog VSSA_PLL Analog PLL ground Analog GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 63 LDO voltage supply Analog Digital IO supply Analog VDDIO Core supply Analog Ground Analog Note 1: Connect to ground via decoupling capacitors when internal LDO is used Note 2: See chapter 2.5 for IO definition selection GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 64: Clocking
Up to six unique external clock sources connected on five external input pins: SYS_CLK, SPW_- CLK, PWRX_CLK, GR1553_CLK, SPI4S_CLK, PWM_CLK sources can be used for generating different clocks in the GR716 Microcontroller. Internal ADC and DAC clock generation is also sup- Note that external PacketWire ported to control asynchronous interface for the ADC and DAC.
Page 65: Pll Configuration And Status
The input clock frequency is set via PLL control and status registers, see section 10. When the GR716 Microcontroller is configured to be controlled via remote access the PLL is config- ured automatically after reset by the hardware. The setup used is determined by configuration boot- straps specified in chapter 3.1.
Page 66: System Clock
ADC clock shall match the sampling speed required by the application. Maximum sampling speed is 200 Ksps i.e. maximum ADC clock frequency is 2 MHz. The ADC clock is configured via registers, see 12. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 67: Dac Clock
All cores on the Debug AHB bus will be gated off when the DSU_EN signal is set to low. 4.12 Test mode clocking When in test mode (TESTEN signal = 1) all clocks in the design are connected to the SYS_CLK test clock. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 68: Reset
The 64 General purpose IO described in chapter 2.4 and 2.5 will set to high impedance mode during power-up/down, Brown detection or if a failure has been detected in the IO configuration registers described in chapter 7.1. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 69: Technical Notes
[GRIP] for this system. 6.2.3 Plug and play Standard GRLIB AMBA plug&play layout is used. The same software routines used for typical LEON/GRLIB systems can be used. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 70: System Startup Status And General Configuration
GPIO1 functional select (GP1) - Select functionality for GPIO pin 1. For functionality see Table 2.6. 3: 0 GPIO0 functional select (GP0) - Select functionality for GPIO pin 0. For functionality see Table 2.6. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 71 GPIO25 functional select (GP1) - Select functionality for GPIO pin 25. For functionality see Table 2.6. 3: 0 GPIO24 functional select (GP0) - Select functionality for GPIO pin 24. For functionality see Table 2.6. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 72 GPIO49 functional select (GP1) - Select functionality for GPIO pin 49. For functionality see Table 2.6. 3: 0 GPIO48 functional select (GP0) - Select functionality for GPIO pin 48. For functionality see Table 2.6. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 73 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DOWN 0xFFFFFFFF 31: 0 Select and configure inputs using internal pulldown resistor (DOWN) - Each bit in register bitfield corresponds to one input pin. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 74 Not used Disable configuration (DI) - Disable configuration at multiple configuration error. 0x1 - Enable disable IO when multiple errors has been detected 0x0 - Disable disable IO when multiple errors has been detected GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 75: Boot Strap Information Register
Enable Memory test (Set to zero for fast re-boot). Default settings is determined by GPIO[62]. For more infor- mation see table 30 in section 3.1 Disable EDAC for external memory. Default settings is determined by GPIO[0]. For more information see table 30 in section 3.1 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 76: Special Configuration Registers
30 in section 3.1 Not used Special Configuration Registers The special registers are used for getting access to special functions in the LEON3FT microcontroller. Special functions accessible via special configuration registers: GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 77 SYS.CFG.ANA1 and SYS.CFG.ANA2. Register described in this section is only available in debug mode. Please contact Cobham Gaisler support if for more information is needed. Table 57. Analog access configuration register...
Page 78 Enable VMON18PLL_COMPIN output on internal analog test bus 5 Access to specific functionality are granted on the following general purpose input and output signals only if corresponding configuration bit is set in the register SYS.CFG.ANA1 and SYS.CFG.ANA2. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 79 The disadvantage of using the March C- algorithm is that it is very time consuming due to its nature of checking bit by bit multiple times. {↑(w0);↑(r0,w1);↑(r1,w0);↓(r0,w1);↓(r1,w0);↓(r0)} March C- algorithm implemented Notation of the algorithm: GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 80 0x0 - Not used (Memory bit for memory is kept in reset state) 0x1 - Enable March C- test algorithm 11: 10 0x2 - Write 0x0 to all locations in memory 9: 8 0x3 - Not used 7: 6 5: 4 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 81 0x0 - No error detected during last test (If test has been run) 0x1 - Enable March C- test algorithm 23: 22 0x2 - Error during last scan 21: 20 0x3 - Invalid state and test result 19: 18 17: 16 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 82 Bit #18 - Bypass buffer, this bit should normally be set to 0 in order to get a full scale ADC reference output. To enable and output a reference for precision measurements using internal ADC set VREF bits to 100b. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 83 Override watchdog error generation (WE) - Disables reset request. To be used during debug of the system Override error generation (EE) - Disables reset generation when processor error is detected. To be used during debug of the system GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 84: Reset Generation And Brownout Detection
The Brownout detector on the supplies, VDD_CORE, VDD_IO, VDDA_PLL, VDDA_ADC, VDDA_DAC, VDD_LVDS, VDDA_REF, have individually programmable threshold levels. The threshold selected for each supply must, in worst case, be set below the guaranteed minimum supply GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 85: Registers
Interrupt mask register 0x10 LDO trim register 0x14 Voltage monitor delay register 0x18 Voltage monitor powerdown register 0x1C Unused 0x20 Power control, XO and LVDS driver enable register 0x24 Brown Out disable IO from local register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 86 Interrupt Flag for Brown Out Detection (IA) Interrupt Flag for Brown Out Detection (ID) Interrupt Flag for Brown Out Detection (IB) Interrupt Flag for Brown Out Detection (IL) Interrupt Flag for Brown Out Detection (IP) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 87 Brown Out Delay for 3.3 V power supply (BDI) 11: 10 Brown Out Delay for 1.8 V power supply (BDC) 9: 8 Brown Out Delay for Analog ADC supply (BDA) 7: 6 Brown Out Delay for Analog DAC supply (BDD) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 88 Table 76. 0x24 - BDI - Brown Out disable IO from local register RESERVED 0x00000000 31: 2 RESERVED Disable IO (D) - Brown Out disable IO from local register Note: Register is protected by password. Contact supportgasiler.com GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 89: Crystal (Xo) Oscillator
XO can then be left open. To minimize the XO current consumption, an detector is build-in to disable the XO if no external XTAL is connected to the external XO pins. 9.2.3 Typical crystal configurations This section specifies a number of typical crystal configurations for the GR716 device. XO_X0 XTAL XO_X1 GR716-DS-UM, May 2019, Version 1.29...
Page 90 The total crystal load capacitance should take into account the PCB stray capacitance and the input capacitance of the GR716 device on XO pins to ground. The XO input pins to ground are typically 4 pF. E.g. Assuming a crystal with load capacitance of...
Page 91: Pll
3.3V CMOS input, to which the XO-oscillator clock output can be directly con- nected, or any other clock signal generated on PCB fulfilling the electrical specification of this input. The PLL reference-clock input is allowed to be asynchronous to any other clocks in the GR716 LEON3FT microcontroller.
Page 92: Registers
Lost lock (LL) - This bit is a sticky bit that indicates if the lock bit from the SpaceWire clock PLL has gone low. This bit can be cleared by writing a 1 to the PLL clear lost lock bit. PLL clock lock (CL) - Shows the current value of the PLL lock output. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 93 DIV bitfield the generated clock shall be high. IF this register is set to 0x0 the duty cycle will be set to clock cycles defined in DIV and the clock period to 2xDIV. 15: 10 RESERVED GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 94 DIV bitfield the generated clock shall be high. IF this register is set to 0x0 the duty cycle will be set to clock cycles defined in DIV and the clock period to 2xDIV. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 95 Table 85. 0x18 - SYSSEL - Select system clock source RESERVED 31: 1 RESERVED Select new system clock source (S) - Writing to this register will force the system clock selected in register SYS- REF to be selected and used.as system clock. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 96 4. force the internal PWM0 clock to be available at GPIO 60 5. force the internal PWM1 clock to be available at GPIO 59 Table 89. 0x28 - PWM0REF - Select reference for PWM0 clock 24 23 16 15 RESERVED DUTY RESERVED GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 97 50% When bitfield DUTY period is larger then 0x1.The DIV bifield will divide the input frequency by DIV clock cycles and with the duty cycle defined in the DUTY bitfield GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 98: Voltage And Current References
DACs. Therefore, it is critical that RREF always is within 4.9-5.3 kohm over worst-case conditions. The DAC fullscale current is proportional to the current through RREF, where 5.11 Kohm gives a nominal fullscale current of 4.0m. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 99: Adc, Pre-Amplifier And Analog Mux
12.1 Overview The GR716 has 2 separate 11 bit Analog-to-Digital Converters (ADC) converters and 8 separate ADC control units. Each 11 bit resolution Analog-to-Digital Converters (ADC) converts analog single- ended or differential input signals to 11 bit digital outputs. An integrated analog multiplexer and pre- amplifier allow measuring both on- and off-chip analog signals.
Page 100: Operation
For simplicity the hardware do not perform any truncation or division of the accumulated sam- ples. To get a correct average sampled value the accumulated sample value shall be rounded and divided by the number of samples used. For application where the truncation error is less import- GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 101 14-bits of the output data for a 14-bit mea- surement. To do so, we accumulate i.e. add 64 consecutive samples together. Once the results have GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 102 In this example we only gener- ate an interrupt when all samples has been transfered in order to minimize the interrupt load. In order to accomplish this we need to: • Setup timer and ADC according to chapter 12.2.3 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 103 0x80400004 0x000000FF ADC0 - Sampling configuration (Oversampling, no consecutive) 0x80400000 0x0008C001 ADC0 - Configuration (Speed, Channel, Enable) After completion 4 oversampled values should be located in the local processor data ram at 0x30002000. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 104 To enable the level detection and interrupt generation the corresponding bit in the interrupt mask reg- ister needs to be set. See table 100. 12.2.7 Access control ADC, Pre-Amplifier and Analog MUX status and configuration can be accessed via registers GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 105: Registers
The set of configuration and status registers available for each ADC controller is reported in table 59. The GR716 has 8 input pins for the ADC. They can be grouped as single ended (up to 8 single ended channels) or differential ADC channels (up to 4), or in a mixed way. Another differential channel is internally available, connected to the temperature sensor described in chapter 14.
Page 106 26: 16 Reserved 15: 0 SD: Sequence divisor determines the sequence-rate for the ADC.The sample rate is determined by the value (SD+1) / (System Frequency / (ACFG.AC + 1)) if no external synchronizer i selected. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 107 ADC digital output (AD) - Digital sampled value. The number of samples accumulated is determined by the number of samples defined in the ASAMPC register. If the field is filled with ones, overflow during oversample occurred. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 108 Amplifier Bypass (AB) - Bypass amplifier for no gain or single mode Amplifier Gain (AG) - Select pre-amplifier gain (effective when AB = 0) 0 dB 6 dB 12 dB 12 dB Table 102. 0x20 - AHT -ADC High Level detection register 19 18 Reserved GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 109 Note: To make use of this function the AD C must be enable the ACFG.AL bit must set Note2: There are 4 individual status registers GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 110: Ldo
VDD_CORE pins, i.e. in the order of 10nF per pin pair, and one larger capacitor (which can be common to other ICs on PCB, to be decided at convenience of the PCB designer). 13.2.3 Access control GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 111: Temperature Sensor
GR716 Temperature Sensor 14.1 Overview There is an integrated temperature sensor on the GR716 microcontroller, which can be used to super- vise the die temperature. 14.2 Operation 14.2.1 System overview The on-chip temperature sensor can be sampled via the internal ADC. It is not accessible externally.
Page 112: Dac
15.1 Overview The GR716 has 4 separate 12 bit Digital-to-Analog Converter (DAC) converters and 4 separate DAC control units. Each Digital-to-Analog Converter (DAC) is a 12 bit resolution DAC. The digital core logic provides a register control and status interface via registers for each DAC. The digital interface also provides more complex control logic in order to synchronize the DAC output to e.g.
Page 113: Operation
TABLE 105. Example of direction conversion of value 0xFF using DAC0 Address Data Description 0x80408004 0x000000FF DAC0 - Output Value 0x80408000 0x01FCC001 DAC0 - Configuration (Scaler, Mode, Enable) 15.2.4 Access control The integrated DAC is controlled via APB registers GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 114: Registers
Table 108. 0x04 - DOUT - DAC output register 12 11 0x00 0x000 31: 12 Reserved 11: 0 DAC Digital input (DI) - DAC Digital unsigned input. Conversion will start when a new value is written to this register. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 115 Table 111. 0x10 - DSTAT - DAC status register Reserved 31:1 Reserved DAC Waiting for Trigger (WT) - DAC is set to wait for trigger to start conversion. When ’0’ the DAC conver- sion has been completed. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 116 31: 1 Reserved Interrupt for DAC End of conversion (EM) Table 113. 0x18 - DMASK - DAC Interrupt Mask Register Reserved 0x00000000 31: 1 Reserved Interrupt Mask for DAC End of conversion (EM) - GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 117: Leon3/Ft - High-Performance Sparc V8 32-Bit Processor
The debug interfaces also allows single stepping, instruction tracing and hardware breakpoint/watchpoint control. An internal trace buffer can monitor and store executed instructions, which can later be read out via the debug interface. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 118: Leon3 Integer Unit
The LEON3 integer unit has the following main features: • 7-stage instruction pipeline • 31 register windows • Hardware multiplier • Radix-2 divider (non-restoring) • Static branch prediction • Single-vector trapping for reduced code size GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 119 XC (Exception) Traps and interrupts are resolved. For internal memory reads, the data is aligned as appropriate. WR (Write): The result of any ALU, logical, shift, or internal memory operations are written back to the register file. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 120 When this is done is specific to the FP/CP unit. 16.2.3 SPARC Implementor’s ID Cobham Gaisler is assigned number 15 (0xF) as SPARC implementor’s identification. This value is hard-coded into bits 31:28 in the %psr register. The version number for LEON3 is 3, which is hard- coded in to bits 27:24 of the %psr.
Page 121 30-bit time tag 16.2.9 Processor configuration register The ancillary state register 17 (%asr17) provides information on how various configuration options. This can be used to enhance the performance of software. See section 16.6.2 for layout. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 122 The data_store_error is delivered as a deferred exception but is non-resumable and therefore classed as interrupting. Likewise, r_register_access_error is delivered as a precise trap but since it is non- resumable it is classed as an interrupting trap. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 123 CWP must be set to a value between 0 and CWPMAX before accessing any non-global register. Writing CWPMAX to (otherwise illegal value) 0 in %asr20 will result in writing only AWP and keep- ing the values of STWIN and CWPMAX. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 124 16.2.19 Constant interrupt delay The LEON3FT is enhanced with an interrupt zero jitter feature. When the interrupt zero jitter feature is enabled all sources of interrupt jitter introduced by the hardware can be eliminated. The latency is GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 125 The processor interrupt delay bit fields are found and in the ASI2 register. Example of setting the interrupt delay to 10 clock cycles: asm volatile (" sta %0, [%1] 2" : : "r"(10), "r"(4) : "memory"); GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 126: Local Instruction And Data Ram
AHB from any AMBA master with access to the DMA bus. 16.4 Floating-point unit Cobham Gaisler’s GRFPU-Lite is connected with the LEON3 pipeline. The characteristics of the FPU’s are described in the next sections. 16.4.1 GRFPU-Lite GRFPU-Lite is a smaller version of GRFPU, suitable for implementations with limited logic resources.
Page 127: Amba Interface
16.5.2 Error handling An AHB ERROR response received while fetching instructions will normally cause an instruction access exception (tt=0x1). An AHB ERROR response while fetching data will normally trigger a data_access_exception trap (tt=0x9). GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 128: Configuration Registers
Table 121.LEON3 Trap base address register (%tbr) 31:12 Trap base address (TBA) - Top 20 bits used for trap table address 11:4 Trap type (TT) - Last taken trap type. Read only. Always zero, read only GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 129 MUL/DIV instructions available (V8) - Indicates SPARC V8 multiply and divide instructions are available Hardward watchpoints (NWP) - Number of watchpoints available is 4 Register windows (NWIM) - Number of implemented registers windows corresponds to NWIN+1 i.e. 31 for GR716. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 130 Write CWP - If written with 1, then the CWP field in PSR will simultaneously be written with the value written to AWP. Alternative Window Pointer (AWP). Continuously updated with the value of CWP when the alterna- tive window feature is disabled. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 131 When cleared, the counter will increment each processor clock cycle. Default (reset) value is ‘1’. 30:0 Reserved and not used Table 125.LEON3 up-counter LSbs (%ASR23) UPCNT(31:0) 31:0 Counter value (UPCNT(31:0)) - Least significant bits of internal up-counter. Read-only. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 132 When there is a hardware watchpoint match and DL or DS is set then trap 0x0B will be generated. Hardware watchpoints can be used with or without the LEON3 debug support unit (DSU) enabled. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 133 Write to FPU register (%f) will only write location of %rs2 Write to IU register (%i, %l, %o, %g) will only write location of %rs1 Write to FPU register (%f) will only write location of %rs1 IU and FPU registers written nominally GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 134: Software Considerations
IU and FPU register files before launching the main application. Initialization of IU and FPU register files is performed by the internal boot ROM before handover to application software. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 135: Ieee-754 Floating-Point Unit
Iteration unit operand1 (Add/Sub/Mul/Div) except operand2 round ctrl_in Control unit 17.2 Functional Description 17.2.1 Floating-point number formats The floating-point unit handles floating-point numbers in single or double precision format as defined in IEEE-754 standard. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 136 Below is a table of worst-case throughput of the floating point unit. Table 129.Worst-case instruction timing Instruction Throughput Latency FADDS, FADDD, FSUBS, FSUBD,FMULS, FMULD, FITOS, FITOD, FSTOI, FDTOI, FSTOD, FDTOS, FCMPS, FCMPD, FCMPES. FCMPED FDIVS FDIVD FSQRTS FSQRTD GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 137 (NX) exception conditions. Generation of special results such as NaNs and infinity is also supported. 17.2.4 Rounding All four rounding modes defined in the IEEE-754 standard are supported: round-to-nearest, round-to- +inf, round-to--inf and round-to-zero. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 138: Uart Serial Interface
GR716 UART Serial Interface The GR716 comprises 6 separate UART units and 2 debug and remote access UART units. The 2 debug and remote access UART units also called AHBUART units are described in section 48. This chapter only describes the UART units also called APBUART. The main difference between the UART units described in this section and the debug UART units are the debug and remote access UART units capability to respond to external UART singling without software support.
Page 139: Overview
(TS) will be set in the UART status register. Transmission resumes and the TS is cleared when a new character is GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 140: Baud-Rate Generation
8 times the desired baud-rate. One appropriate formula to calculate the scaler value for a desired baud rate, using integer division where the remainder is discarded, is: scaler value = (system_clock_frequency) / (baud_rate * 8 + 7). To calculate the exact required scaler value use: GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 141: Loop Back Mode
An interrupt can also be enabled for the transmitter shift register. When enabled the core will generate an interrupt each time the shift register goes from a non-empty to an empty state. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 142: Registers
UART4 Scaler register (UART4.SCALER) 0x80304010 UART4 FIFO debug register (UART4.FIFO) 0x80305000 UART5 Data register (UART5.DATA) 0x80305004 UART5 Status register (UART5.STATUS) 0x80305008 UART5 Control register (UART5.CTRL) 0x8030500C UART5 Scaler register (UART5.SCALER) 0x80305010 UART5 FIFO debug register (UART5.FIFO) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 143 Transmitter FIFO empty (TE) - indicates that the transmitter FIFO is empty. Reset: 1 Transmitter shift register empty (TS) - indicates that the transmitter shift register is empty. Reset: 1 Data ready (DR) - indicates that new data is available in the receiver FIFO. Reset: 0 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 144 Receiver FIFO interrupt enable (RF) - when set, Receiver FIFO level interrupts are enabled. Transmitter FIFO interrupt enable (TF) - when set, Transmitter FIFO level interrupts are enabled. RESERVED and should always be set to ’0’ for the GR716 device Loop back (LB) - if set, loop back mode will be enabled.
Page 145: Hardware Debug Support Unit
DSU control register • after a single-step operation • the processor has entered the debug mode • DSU AHB breakpoint or watchpoint hit GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 146: Ahb Trace Buffer
(BW) bit must be set in the DSU control register. This bit is set when DSUBRE is active after reset and should also be set by debug monitor software (like Cobham Gaisler’s GRMON) when initializing the DSU. When the debug mode is entered, the following actions are taken: •...
Page 147 Wait state Active when HREADY input to AHB slaves is low and AMBA response is OKAY. retry RETRY response Active when master receives RETRY response split SPLIT response Active when master receives SPLIT response GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 148: Instruction Trace Buffer
(processor in normal mode) the trace buffer and trace buffer control register 0 can not be written. The traced instructions can optionally be filtered on instruction types. Which instructions are traced is defined in the instruction trace register [31:28], as defined in the table below: GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 149: Using The Dsu Trace Buffer
IU register file, port1 (%asr16.dpsel = 0) IU register file, port 2 (%asr16.dpsel = 1) 0x300800 - 0x300FFC IU register file information for correctable and uncorrectable errors 0x301000 - 0x30107C FPU register file 0x400000 - 0x4FFFFC IU special purpose registers GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 150: Dsu Registers
(trap in trap). Trace enable (TE) - Enables instruction tracing. If set the instructions will be stored in the trace buffer. Remains set when then processor enters debug or error mode GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 151 The trace buffer time tag counter is incremented each clock as long as the processor is running. The counter is stopped when the processor enters debug mode and when the DSU is disabled (unless the GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 152 Break (BR) - If set, the processor will be put in debug mode when AHB trace buffer stops due to AHB breakpoint hit. Delay counter mode (DM) - Indicates that the trace buffer is in delay counter mode. Trace enable (EN) - Enables the trace buffer. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 153 The AHB trace buffer index register contains the address of the next trace line to be written. Table 148.0x000044 - ATBI - AHB trace buffer index register INDEX 31: 4 Trace buffer index counter (INDEX) 3: 0 Read as 0x0 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 154 Only address bits with the corresponding mask bit set to ‘1’ are compared during breakpoint detec- tion. To break on AHB load or store accesses, the LD and/or ST bits should be set. Table 151.0x000050, 0x000058 - ATBBA - AHB trace buffer break address register BADDR[31:2] GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 155 0 to generate the value in the TOV field below. Trace Overflow (TOV) - Gets set to ‘1’ when the DSU detects that TLIM equals the top three bits of ITPOINTER. 22: 0 RESERVED GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 156: On-Chip Dual-Port Memory With Edac Protection
0x80001FFF) 0x8000BFFF) 0x8010AFFF) Figure 16. GR716 LRAM bus connection System can be configured to protect and restrict access to the Local on-chip SRAM with EDAC (LRAM) units configuration and memory area in the MEMPROT units. For more information See section 47 for more information.
Page 157 Correctable errors are automatically corrected and not visible for the CPU (the auto-correction feature can be disabled by the LRAMCFG.ACOR configuration field). When an uncorrectable error is detected the access will terminate with a data_access/store_exception. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 158 SCRUBCFG.CB field. To perform the error injection, the address and pending bit need to be set in the scrub control register (SCRUBCTRL.ADDR and SCRUBCTRL.PEN). This would trigger a read-modify-write access to the memory location and xor:ed checksum is written to memory. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 159: Local Memory Memory Map And Register
IE - Interrupt enable. Enable the assertion of an interrupt when the scrubber detects a un-correctable error. 11: 10 ACOR - Auto-correction disable. Disable auto-correction for detected errors. Bit[11]: AHB port, bit[10]: CPU port. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 160 DISE - Disable the scrubber when a uncorrectable error is detected. Reserved. 10: 4 CB - Checksum. WCB - Write checksum. RCB - Read checksum. XCB - XOR checksum with the value of field CB. WASH - Enable wash mode. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 161 DATA - Data used by the scrubber in wash mode. Table 162. 0x8000B008 - AHBRAM1.SCRUBCTRL - Scrubber Control Register ADDR rw rw 31: 2 ADDR - Scrubber address offset. PEN - Scrub access pending. SEN - Scrubber enable. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 162 DISE - Disable the scrubber when a uncorrectable error is detected. Reserved. 10: 4 CB - Checksum. WCB - Write checksum. RCB - Read checksum. XCB - XOR checksum with the value of field CB. WASH - Enable wash mode. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 163: Fault Tolerant Prom/Sram Memory Interface
0x8000D03F) GPIO0 GPIO63 Figure 18. GR716 FTMCTRL bus and pin The primary clock gating unit GRCLKGATE described in section 26 is used to enable/disable the fault tolerant 8-bit memory controller (FTMCTRL). The unit GRCLKGATE can also be used to per- form reset of the fault tolerant 8-bit memory controller (FTMCTRL).
Page 164: Prom Access
PROM area. data1 data2 data1 data2 address romsn data Figure 19. Prom non-consecutive read cycles. data1 data2 data1 data2 data address romsn data Figure 20. Prom consecutive read cycles. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 165 Figure 21. Prom read access with two waitstates. lead-in data lead-out address romsn rwen data Figure 22. Prom write cycle (0-waitstates) data lead-out lead-in data data address romsn rwen data Figure 23. Prom write cycle (2-waitstates) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 166: Sram Access
CB0 = D0 ^ D4 ^ D6 ^ D7 ^ D8 ^ D9 ^ D11 ^ D14 ^ D17 ^ D18 ^ D19 ^ D21 ^ D26 ^ D28 ^ D29 ^ D31 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 167: Bus Ready Signalling
OEN/RAMOEN and BRDYN must be asserted for at least 1.5 clock cycle. It is recommended that BRDYN is asserted until the corresponding chip select signal is de-asserted, to ensure that the access has been properly completed and avoiding the system to stall. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 168 BRDYN is first asserted until it is visible internally. In figure 26 one cycle is added to the data2 phase. data1 data2 data2 lead-out address romsn/ramsn[4] data brdyn bexcn Figure 26. BRDYN (asynchronous) sampling and BEXCN timing. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 169: Access Errors
AHB bus. BEXCN can be enabled or disabled through memory configuration register 1, and is active for all areas (PROM and RAM). data1 data2 lead-out address romsn/iosn/ramsn data bexcn Figure 28. Read cycle with BEXCN. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 170: Registers
Asynchronous bus ready (ABRDY) - Enables asynchronous bus ready. 28 : 27 RESERVED RESERVED Bus error enable (BEXCN) - Enables bus error signalling for all areas. Reset to ‘0’. RESERVED 23 : 20 RESERVED GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 171 RAM width (RAM WIDTH) - Sets the data width of the RAM area (“00”=8, “01”=16, “1X”=32). For GR716 the data width is locked to 8 bits i.e. for GR716 this bit field shall always be set to "00". 3 : 2 RAM write waitstates (RAM WRITE WS) - Sets the number of wait states for RAM write cycles (“00”=0, “01”=1, “10”=2, “11”=3).
Page 172 MCFG5 contains fields to control lead out cycles for the ROM areas. Table 170.0x10 - MCFG5 - Memory configuration register 5 RESERVED RESERVED RESERVED RESERVED ROMHWS RESERVED 0x00 31 : 30 RESERVED 29:23 RESERVED GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 173 Table 171.0x14 - MCFG6 - Memory configuration register 6 RESERVED RESERVED RAMHWS RESERVED 0x00 31 : 14 RESERVED 13:7 RAM lead out (RAMHWS) - Lead out cycles added to RAM accesses are RAMHWS(6:4) RAMHWS(3:0)*2 6 : 0 RESERVED GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 174: Fault Tolerant Nvram Memory Interface
The LEON3FT microcontroller support up to four chip selects using this type of memory. The memory controller interface is not available on external pins on currently available GR716 mod- els and the documentation for the memory controller is not included in this document. For more infor- mation please contact Cobham Gaisler.
Page 175: Mil-Std-1553B / As15531 Interface
GR716 MIL-STD-1553B / AS15531 Interface The GR716 microcontroller comprises a MIL-STD-1553B / AS15531 Interface (GR1553B) unit. The MIL-STD-1553B / AS15531 Interface (GR1553B) unit controls its own external pins and has a unique AMBA address described in chapter 2.11. The MIL-STD-1553B / AS15531 Interface (GR1553B) unit is located on APB bus in the address range from 0x80101000 to 0x80101FFF.
Page 176: Electrical Interface
Figure 31. Interface between core and MIL-STD-1553B bus (dual-redundant, transformer coupled) 23.3 Operation 23.3.1 Operating modes The core contains three separate control units for the Bus Controller, Remote Terminal and Bus Mon- itor handling, with a shared 1553 codec. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 177 Loop-back checking logic checks that each transmitted word is also seen on the receive inputs. If the transmitted word is not echoed back, the transmitter stops and signals an error condition, which is then reported back to the user. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 178: Bus Controller Operation
‘0’, if it succeeds on bus B, the swap register bit is set to ‘1’. If the trans- fer fails, the bus swap register is set to the opposite value. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 179 This can be used for RT-to-RT transfers where the BC is not interested in the data transferred. 0x0C Result word, written by core (see table 175) Unused GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 180 Second RT Subaddress for RT-to-RT transfer (RTSA2) for different transfer types. 15:11 RT Address (RTAD1) Note that bits 15:0 correspond to the (first) Transmit/receive (TR) command word on the 1553 bus RT Subaddress (RTSA1) Word count/Mode code (WCMC) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 181 Don’t care Mode code Mode, BC-to-RT (17/20/21) (2 bytes) (*) The standard allows using either of subaddress 0 or 31 for mode commands. The branch condition word is formed as shown in table 177. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 182 Status Condition Code (STCC) - Mask with bits corresponding to status value of last transfer Note that you can get a constant true condition by setting MODE=0 and STCC=0xFF, and a constant false condition by setting STCC=0x00. 0x800000FF can thus be used as an end-of-list marker. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 183: Remote Terminal Operation
Descriptor ctrl/stat SA N Receive descr. ptr Data buffer ptr. Receive buffer Next pointer Descriptor ctrl/stat SA N+1 Data buffer ptr. Receive buffer Next pointer Subaddress table Figure 32. RT subaddress data structure example diagram GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 184 Enabled always, can not be logged or disabled. 10011 Transmit BIT word Responds with BIT word from RT Status Words 15:14 Register 10100 Selected transmitter No built-in action shutdown 10101 Override selected No built-in action transmitter shutdown GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 185 Interrupt on transmit transfers (TXIRQ) - Each transmit transfer will cause an interrupt (only if TXEN,TXLOG=1) 4 : 0 Maximum legal transmit size (TXSZ) from this subaddress - in 16-bit words, 0 means 32 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 186 011 = Protocol error (improperly timed data words or decoder error) 100 = The busy bit or message error bit was set in the transmitted status word and no data was sent 101 = Transfer aborted due to loop back checker error GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 187: Bus Monitor Operation
Reserved - Mask out on read for forward compatibility Receive data bus (BUS) - 0:A, 1:B 18 : 17 Word status (WST) - 00=word OK, 01=Manchester error, 10=Parity error Word type (WTP) - 0:Data, 1:Command/status 15 : 0 Word data (WD) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 188: Registers
0x5C BC Per-RT bus swap register 0x00000000 0x60...0x67 (Reserved) 0x68 BC Transfer list current slot pointer 0x00000000 0x6C BC Asynchronous list current slot pointer 0x00000000 0x70...0x7F (Reserved) (*) May differ depending on core configuration GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 189 BM RT Mode code filter register 0xffffffff 0xD4 BM Log buffer start 0x00000000 0xD8 BM Log buffer end 0x00000007 0xDC BM Log buffer position 0x00000000 0xE0 BM Time tag control register 0x00000000 0xE4...0xFF (Reserved) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 190 Codec clock frequency (CCFREQ) - Reserved for future versions of the core to indicate that the core runs at a different codec clock frequency. Frequency value in MHz, a value of 0 means 20 MHz. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 191 SCHEDULE TRANSFER LIST POINTER 31 : 0 Read: Currently executing (if SCST=001) or next transfer to be executed in regular schedule. Write: Change address. If running, this will cause a jump after the current transfer has finished. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 192 31 : 0 The current write pointer into the transfer-tirggered IRQ descriptor pointer ring. Bits 1:0 are constant zero (4-byte aligned) The ring wraps at the 64-byte boundary, so bits 31:6 are only changed by user GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 193 Bus B shutdown (SHDB) - Reads ‘1’ if bus B has been shut down by the BC (using the transmitter shutdown mode command on bus A) RT Running (RUN) - ‘1’ if the RT is listening to commands. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 194 31 : 16 BIT Word - Transmitted in response to the “Transmit BIT Word” mode command, if legal 15 : 0 Vector word - Transmitted in response to the “Transmit vector word” mode command, if legal. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 195 Transmitter shutdown & override transmitter shutdown (TS) 7 : 6 Synchronize with data word broadcast (SDB) 5 : 4 Synchronize with data word (SD) 3 : 2 Synchronize broadcast (SB) 1 : 0 Synchronize (S) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 196 BMSUP KEYEN RESERVED BM Supported (BMSUP) - Reads ‘1’ if BM support is in the core. Key Enabled (KEYEN) - Reads ‘1’ if the BM validates the BMKEY field when the control register is written. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 197 Enables logging of mode commands on sub address 31 30 : 1 Each bit position set to ‘1’ enables logging of transfers with the corresponding RT sub address Enables logging of mode commands on sub address 0 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 198 Only bits 21:3 are settable, i.e. the buffer can not cross a 4 MB boundary Bits 31:22 read the same as the buffer start address.Due to alignment, bits 2:0 are always equal to 1 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 199 31 : 24 Time tag resolution (TRES) - Time unit of BM:s time tag counter in microseconds, minus 1 23 : 0 Time tag value (TVAL) - Current value of running time tag counter GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 200: Adc / Dac Interface
Figure 33. Block diagram and usage example 24.1.1 Function The core implements the following functions: • ADC interface conversion: • ready feed-back, or • timed open-loop • DAC interface conversion: • timed open-loop • General purpose input output: GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 201 Blank/Convert*, RDY*, tri-state AD1671 12-bit Encode, RDY*, non-tri-state LTC141414-bitConvert*, RDY, non-tri-state STM1401 14-bit continuously sampling The DAC interface is intended for amongst others the following devices: Name:Width:Type: AD56110-bitParallel-Data-in-Analogue-out AD56512-bitParallel-Data-in-Analogue-out AD66712-bitParallel-Data-in-Analogue-out, CS* AD76712-bitParallel-Data-in-Analogue-out, CS* DAC08 8-bit Parallel-Data-in-Analogue-out GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 202: Operation
ADC conversion without the use of the Ready signal, by means of a programmable conversion time duration. This can be seen as an open-loop conversion. The Chip Select output signal is programmable in terms of: • Polarity • Number of assertions during a conversion, either GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 203 An ADC conversion is non-interruptible. It is possible to perform at least 1000 conversions per sec- ond. Start conversion Read result WS WS WS WS Trig Data Addr Settings: RCPOL=0 Sample data CSPOL=0 RDYPOL=1 TRIGPOL=1 RDYMODE=1 CSMODE=00 ADCWS=0 Figure 34. Analogue to digital conversion waveform, 0 wait states (WS) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 204: Registers
0x10§ ADC Data Input Register 0x14§ DAC Data Output Register 0x20§ Address Input Register 0x24§ Address Output Register 0x28§ Address Direction Register 0x30§ Data Input Register 0x34§ Data Output Register 0x38§ Data Direction Register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 205 The DACDW field defines what part of ADO.Dout[15:0] is written by the DAC. Parts of the data input/output signals used neither by ADC nor by DAC are available for the general purpose input output functionality. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 206 Note that the status bits can be used for monitoring the progress of a conversion or to ascertain that the interface is free for usage. 24.3.3 ADC Data Input Register [ADIN] R/W Table 226.ADC Data Input Register ADCIN 15-0: ADCIN ADC input data ADI.Din[15:0] GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 207 24.3.6 Address Output Register [ADAOUT] R Table 229.Address Output Register AOUT 7-0: AOUT Output address ADO.Aout[7:0] All bits are cleared to 0 at reset. 24.3.7 Address Direction Register [ADADIR] R Table 230.Address Direction Register ADIR 7-0: ADIR Direction: ADO.Aout[7:0] GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 208 1b = output = driven All bits are cleared to 0 at reset. Note that only the part of ADO.Dout[15:0] not used by the DAC can be used as general purpose input output, see ADCONF.DACDW. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 209: Can 2.0 Controller
Note: The CAN 2.0 Controller is planned to be replaced by a CAN-FD controller in the next revision of the silicon. See section 56. The GR716 microcontroller comprises two separate CAN 2.0 controller (GRCAN) units. Each CAN 2.0 controller unit controls its own external pins and has a unique AMBA address described in chapter 2.11.
Page 210: Overview
AMBA Slave GRCAN Figure 37. Block diagram 25.1.1 Function The core implements the following functions: • CAN protocol • Message transmission • Message filtering and reception • SYNC message reception • Status and monitoring GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 211: Interface
Note that there are three different CAN types generally defined: • 2.0A, which considers 29 bit ID messages as an error • 2.0B Passive, which ignores 29 bit ID messages • 2.0B Active, which handles 11 and 29 bit ID messages GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 212: Status And Monitoring
The difference between the write and the read pointers is the number of CAN messages available in the buffer for transmission. The difference is calculated using the buffer size, specified by the CanTx- SIZE.SIZE field, taking wrap around effects of the circular buffer into account. Examples: GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 213 SYNC Code Filter Register.SYNC and SYNC Mask Filter Reg- ister.MASK registers is successfully transmitted. Additional interrupts are provided to signal error conditions on the CAN bus and AMBA bus. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 214 It is also possible to wait for the Tx and TxLoss interrupts described hereafter. The channel can be re-enabled again without the need to re-configure the address, size and pointers. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 215: Reception
Note however that it is not possible to fill the buffer completely, leaving at least one message position in the buffer empty. This is to simplify wrap-around condition checking. E.g. CanRxSIZE.SIZE=2 means that 7 CAN messages fit in the buffer at any given time. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 216 The RxSync interrupt is issued when a message matching the SYNC Code Filter Register.SYNC and SYNC Mask Filter Register.MASK registers has been successfully received. Additional interrupts are provided to signal error conditions on the CAN bus and AMBA bus. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 217 Successful reception of one message • RxFull: Successful reception of all messages possible to store in buffer • RxIrq: Successful reception of a predefined number of messages • RxAHBErr: AHB access error during reception • Over-run during reception GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 218: Global Reset And Enable
Note that the CAN core requires that 10 recessive bits are received before any reception or transmission can be initiated. This can be caused either by no unit sending on the CAN bus, or by random bits in message transfers. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 219: Registers
00b = system clock / (SCALER +1) / 1 01b = system clock / (SCALER +1) / 2 10b = system clock / (SCALER +1) / 4 11b = system clock / (SCALER +1) / 8 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 220 AHB error occurs while the ABORT bit is set to 1b. The accesses will be disabled until the CanSTAT register is read. 25.8.2 Status Register [CanSTAT] R Table 236.Status register TxChannels RxChannels TxErrCntr RxErrCntr Acti Pass 31-28: TxChannelsNumber of TxChannels -1, 4-bit 27-24: RxChannelsNumber of RxChannels -1, 4-bit GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 221 Table 238.SYNC Code Filter Register SYNC 28-0: SYNC Message Identifier All bits are cleared to 0 at reset. Note that Base ID is bits 28 to 18 and Extended ID is bits 17 to 0. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 222 25.8.7 Transmit Channel Address Register [CanTxADDR] R/W Table 241.Transmit Channel Address Register ADDR 31-10: ADDR Base address for circular buffer All bits are cleared to 0 at reset. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 223 Note that the READ field can be automatically incremented even if the transmit channel has been dis- abled, since the last requested transfer is not aborted until CAN bus arbitration is lost. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 224 Base address for circular buffer All bits are cleared to 0 at reset. 25.8.14 Receive Channel Size Register [CanRxSIZE] R/W Table 248.Receive Channel Size Register SIZE 20-6: SIZE The size of the circular buffer is SIZE*4 messages GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 225 Software is responsible for not over-reading the buffer on wrap around (i.e. setting WRITE=READ). 25.8.17 Receive Channel Interrupt Register [CanRxIRQ] R/W Table 251.Receive Channel Interrupt Register 19-4: Interrupt is generated when CanRxWR.WRITE=IRQ, as a consequence of a message reception All bits are cleared to 0 at reset. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 226 Clearing interrupts: All bits of the Pending Interrupt Register are cleared when it is read or when the Pending Interrupt Masked Register is read. Reading the Pending Interrupt Masked Register yields the contents of the Pending Interrupt Register masked with the contents of the Interrupt Mask Register. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 227 Successful reception of a predefined number of messages TxAHBErr AHB error during transmission RxAHBErr AHB error during reception Over-run during reception Bus-off condition PASS Error-passive condition All bits in all interrupt registers are reset to 0b after reset. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 228: Memory Mapping
Base Identifier Extended Identifier Data Length Code, according to CAN standard: 0000b 0 bytes 0001b 1 byte 0010b 2 bytes 0011b 3 bytes 0100b 4 bytes 0101b 5 bytes 0110b 6 bytes 0111b 7 bytes GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 229 AHBErr AHB interface blocked due to AHB Error when 1b Reception Over run when 1b Bus Off mode when 1b PASS Error Passive mode when 1b Byte 00 to 07 Transmit/Receive data, Byte 00 first Byte 07 last GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 230: Clock Gating Unit (Primary)
GR716 Clock gating unit (Primary) The GR716 microcontroller have 2 separate clock gating units. Each clock gating unit will control its own clock domains and has a unique AMBA address described in chapter 2.11. 26.1 Overview The clock gating unit provides a mean to save power by disabling the clock to unused functional blocks.
Page 231: Registers
The core’s registers are mapped into APB address space. Table 256. Clock gate unit registers APB address offset Register 0x00 Unlock register 0 0x04 Clock enable register 0 0x08 Core reset register 0 0x0C CPU/FPU override register 0 0x10 - 0xFF Reserved GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 232 Clock enable I2CLSV0 (IS0) Clock enable I2CMST1 (IM1) Clock enable I2CMST0 (IM0) Clock enable SPICTRL1 (S1) Clock enable SPICTRL0 (S0) Clock enable SPIMCTRL1 (M1) Clock enable SPIMCTRL0 (M0) Clock enable FTMCTRL (MC) Clock enable GRPWTX (PX) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 233 %PSR.EF. 15: 1 RESERVED Override CPU clock gating (OVERRIDE) - If bit n of this field is set to ’1’ then the clock for the processor and FPU will always be active. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 234: Clock Gating Unit (Secondary)
GR716 Clock gating unit (Secondary) The GR716 microcontroller have 2 separate clock gating units. Each clock gating unit will control its own clock domains and has a unique AMBA address described in chapter 2.11. 27.1 Overview The clock gating unit provides a mean to save power by disabling the clock to unused functional blocks.
Page 235: Registers
The core’s registers are mapped into APB address space. Table 261. Clock gate unit registers APB address offset Register 0x00 Unlock register 1 0x04 Clock enable register 1 0x08 Core reset register 1 0x0C - 0xFF Reserved GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 236 Cock enable - A ‘1’ in a bit location will enable the corresponding clock, while a ‘0’ will disable the clock. ** Clock enable might be set to ’1’ by bootstrap signals or boot software during startup of the device GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 237 31: 22 RESERVED 21: 0 Reset (RESET) - A reset will be generated as long as the corresponding bit is set to ‘1’. See Table 263 for bit field description GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 238: Dma Controller With Internal Ahb/Apb Bridge
The system can be configured to protect and restrict access to DMA controller units. 28.1 Overview The GR716 provides 4 individual DMA cores. Each DMA core provides a flexible direct memory access controller. The core can perform burst transfers of data between AHB and APB peripherals at aligned or unaligned memory addresses.
Page 239: Configuration
M2B and B2M descriptor linked list. They are special descriptors that enable conditional behavior in a descriptor linked list and they are described in more detail in paragraph 28.3.2 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 240 M2B descriptor Fixed Address (FA) - If set to ‘1’, the data will be fetched from the same address for the entire size of the descriptor transfer. This is useful when reading from IO peripheral registers in combination with a conditional descriptor. If set to ‘0’, normal operation mode is attained. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 241 Must be set to ‘0’ for this type of descriptor. Table 273. GRDMAC B2M descriptor address field (address offset 0x04) ADDR 31: 0 B2M Address (ADDR) - Starting address the core will write data to. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 242 When the monitored input line is sampled to a value of ‘1’, the data descriptor will be executed. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 243 Table 278.GRDMAC Conditional descriptor format Address offset Field Conditional next_descriptor Conditional address/triggering line Conditional control Conditional mask Table 279. GRDMAC Conditional descriptor next_descriptor field (address offset 0x00) NEXT_PTR GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 244 Conditional descriptor Enable (EN) - If set to one, the descriptor will be enabled, otherwise it will be skipped and the next descriptor fetched from memory. Table 282. GRDMAC Conditional descriptor mask field (address offset 0x0C) COND_MASK GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 245 The conditional descriptor will considered to be complete when the data descriptors has been exe- cuted the number of times specified in the conditional loop counter field, COND_CNT. When the GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 246 The unit is number of clock cycles and the purpose is to provide a timer between polling requests onto the AMBA AHB bus with enough clock cycles in order not to clog the bus. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 247 If register is set to ’0xFFFF’ data and mask will be tested at every event until the DMA controller is disabled manually by software or until an error will occur. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 248: Operation
32-bit word at the COND_ADDR address. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 249 In Simplified Mode of Operation, the GRDMAC core configuration resides entirely in its configura- tion registers and the Channel Vector structure is not used. The core will not perform any memory access to fetch configuration data. This mode of operation makes use of only two data descriptors, GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 250: Ahb Transfers
AMBA AHB ERROR response. When a transfer error occurs on a descriptor which has the write-back flag enabled, the descriptor status will be written back to main memory with the error field set to one. An eventual interrupt will be generated only after the write back. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 251: Internal Buffer Readout Interface
Internal Buffer Pointers Register (offset 0x40). 28.8 Registers The core is programmed through registers mapped into APB address space. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 252 0x2C M2B Descriptor Status register* 0x30 Reserved 0x34 B2M Descriptor Address register* 0x38 B2M Descriptor Control register* 0x3C B2M Descriptor Status register* 0x800-0x81F Internal Buffer Readout Area *Only used in Simplified Mode of Operation GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 253 15: 0 Interrupt Mask for channel - Set to 0 to mask descriptor interrupt generation from channel. Interrupt generation depends on the global Interrupt Enable in the control register. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 254 Timer Reset VAlue (TIMER_RST) - Reset value for the triggered conditional descriptor timeout 28.8.7 Capability Register Table 301.GRDMAC capability register 16 15 12 11 10 BUFSZ RESERVED 31: 16 Buffer size (BUFSZ) - Internal DMA buffer is 4 words. Timer (TT) - Tmeout timer is enabled. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 255 Second AHB Master (H1) - If set to one, the second AHB master interface (AHBM1) is enabled. 7: 4 Channel Number (NCH) - The maximum number of supported DMA channels in the core is 15+1. 3: 0 Version (VER) - GRDMAC version number. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 256 M2B descriptor status (S) - If set to one, the descriptor is being executed and running. Otherwise set to zero. M2B descriptor completion (C) - If set to one, the descriptor was completed successfully. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 257: Dma Transfer Example
The B2M chain will only need one data descriptor. The conditional descriptor will poll the UART status register, mapped at 0xCCC00104, and will use the mask 0x00000100 for the termination condition. This mask will be ANDed with the status regis- GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 258 ADC to the local memory before interrupting the processor. The DMA can be pro- grammed to transfer a pre-defined or infinite number samples. (The software needs to disable the DMA if infinite transfer mode is enabled and no interrupt). The DMA controller can be programmed GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 259 ADC data written by the DMA controller 0x02004 0x02008 0x0200C 0x02010 0x02014 0x02018 0x0201C 0x01080 0x01000 Channel Vector - Channel 0 M2B descriptor chain pointer 0x01084 0x01040 Channel Vector - Channel 0 B2M descriptor chain pointer GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 260 0x80500004 0x000000FF ADC0 - Sampling configuration (Oversampling, no consecutive) 0x80500000 0x00081 ADC0 - Configuration (Speed, Channel, Enable) After completion 4 oversampled values should be located in the local processor data ram at 0x02000. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 261: General Purpose I/O Port
GR716 General Purpose I/O Port The GR716 microcontroller has 2 separate General Purpose I/O port (GRGPIO) units. Each General Purpose I/O port (GRGPIO) units controls its own external pins and has a unique AMBA address described in chapter 2.11. The General Purpose I/O port (GRGPIO) units are located on APB bus in the address range from 0x8030C000 to 0x8030CFFF and 0x8030D000 to 0x8030DFFF.
Page 262: Overview
0 while sequencer units 4, 5, 6 and 7 are connected and controlled via GPIO unit 1. This chapter describes one GPIO unit. The two GPIO units in the GR716 are identical except for the physical external pin connected to GPIO unit 1 and GPIO unit 2. For separation in this document GPIO unit 1 are connected to external pins 0 to 31 and includes sequencer 0, 1, 2 and 3.
Page 263 In the example of using GPIO1 to GPIO4 the following configuration should be used in order to out- put a sequence of 4x32 states per port: GPIO1: Cascade mode and START GPIO2: Cascade mode GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 264: Pulse Sampler
Sampling using combination of FD and consecutive mode will start consecutive sampling of the input when GPIO input state change occurs until SAMPDATA is full. 29.6 Registers The core is programmed through registers mapped into APB address space. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 265 I/O port output register, logical-Set&Clear 0xA0 I/O port direction register, logical-Set&Clear 0xA8 I/O port direction register, logical-Set&Clear 0xB0 Interrupt mask register, logical-Set&Clear 0xB8 Interrupt mask register, logical-Set&Clear GPIO input Sequencer/sampling functionality 0x100 + n*0x20 Sequence control register 0 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 266 Each GPIO pin have separate control register, synchronization and data register for sampling and generating out- put sequences Note 3: Each GPIO unit have 4 separate GPIO sequencer i.e. base address for sequencers are: Sequencer 0: 0x100 Sequencer 1: 0x120 Sequencer 2: 0x140 Sequencer 3: 0x160 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 267 Table 316.0x0C - IMASK - Interrupt mask register MASK Interrupt mask (MASK) - 0=interrupt masked, 1=intrrupt enabled 29.6.5 Interrupt Polarity Register Table 317.0x10 - IPOL - Interrupt polarity register Interrupt polarity (POL) - 0=low/falling, 1=high/rising GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 268 Interrupt mask register in order for the I/O line to drive the interrupt specified by the IRQMAP field. 29.6.9 Interrupt Available Register Table 321.0x40 - IAVAIL - Interrupt available register IMASK IMASK: Interrupt mask bit field. If IMASK[n] is 1 then GPIO line n can generate interrupts. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 269 New value = <Old value> logical-op <Write data> There exists logical-OR, AND and XOR registers for the Input enable, I/O port output, I/O port direction and Interrupt mask registers. 29.6.14 Logical-Set&Clear Register Table 326.0x80-0xB8 - Logical Set&Clear - Logical-OR/AND/XOR registers VALUE GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 270 The logical-Set&Clear registers will update the corresponding register according to: New value = (<Old value> OR < First write>) OR (<Old value> AND NOT <Second write>) The first write is used to ’set’ bits and second write is used to ’clear’ bits. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 271 CT: Continuously sampling of GPIO input. This feature will continuously sample at every clock cycle or when selected trigger event occur. If this feature isn’t selected sampling will stop immedi- ately when sampling buffer is full. TR: Sample input using external trigger source selected in SEQSYNC GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 272 Synchronize GPIO n to Timer unit 0 counter 2 Synchronize GPIO n to Timer unit 0 counter 1 Synchronize GPIO n to Timer unit 0 counter 0 Synchronize GPIO n to Timer unit 0 scaler tick GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 273 GPIO output pin sequence memory. The output sequence will be the following: 0, 1, .. 31 29.6.19 Sampling Sequence Memory Register n Table 331.0x110+n*0x20 - SAMPSEQ - Sampling Sequence memory register VALUE 0x00000000 GPIO input pin sampling sequence GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 274 Sequence start offset (OFFSET) - This register shifts the sequencer within the physical GPIO group.For group #1 this set start GPIO pad from 0 to 31. For GPIO group #2 this register sets the start pin from 32 to 64. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 275: Pulse Width Modulation Generator
GR716 Pulse Width Modulation Generator The GR716 comprises 2 separate pulse width modulator generator (PWM) units. PWM unit number 0 can generate 8 pairs of output signals in normal and complementary format. For example PWM out- put 1 (PWM1) is the complementary version of PWM output 0 (PWM0). PWM unit 1 is only con- nected to complementary outputs, i.e.
Page 276: Overview
Specific configuration required for symmetric PWM if dual compare mode should be used: • If the core should update the PWM’s compare register twice every PWM period, user has to con- figure dcen bit and c2e bit in the PWM control register accordingly. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 277 The PWM period in the example is 0x0800 and PWM signal is assumed to be activated at 0x0000 and 0x0200. PWM0 PWM1 PCOMP.COMP 0x0000 0xFFFF 0x0000 0xFFFF 0x0200 ..0x0200 0xFFFF 0x0200 0xFFFF 0x0800 ..PCOMP.COMP1 Figure 41. Example of entering and leaving IDLE states. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 278: Registers
* This register is implemented once for every PWM (the LEON3FT microcontroller have support for 8 PWM), with an offset of 0x10 from the previous PWM’s register. The functionality is the same for each PWM. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 279 Interrup pending bits for the PWM(s). When an interrupt event for a specific PWM occurs the core sets the corresponding bit in the interrupt pending register and generates an interrupt. Software can read this register to see which PWM that generated the interrupt. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 280 PWM the output could then be switched. When this register is written the actual PWM period value used inside the core is not updated immediately, instead a shadow register is used to hold the new value until a new PWM period starts. Reset value 0b0..0 (all zeroes). GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 281 This is done in order to prevent the dead band scaler register to change during the actual dead band time. Reset value is 0b0..0 (all zeroes). GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 282 PWM enable/disable bit. 0b0 = PWM is disabled. 0b1 = PWM is enabled. When this bit is set to 1 (from 0) and the wen bit (see bit 9 above) is set the core’s internal address counter for the waveform RAM is reset. Reset value is 0b0. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 283: Packetwire Receiver
(control), and for word transfer (address or data). Transmitted data should consist of multiples of eight bits otherwise the last bits will be lost. The message delimiter port GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 284: Operation
Enable (EN) - Set to one to enable the descriptor. Should always be set last of all the descriptor fields. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 285 If the Cyclic Redundancy Code (CRC) bit is set, a CRC calculated over all but the two last octets, will be checked and the results stored in the descriptor. The CRC is defined in There are multiple bits in the DMA status register that hold status information. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 286: Registers
Register 0x00 GRPWRX DMA Control register 0x04 GRPWRX DMA Status register 0x08 GRPWRX DMA Descriptor Pointer register 0x80 GRPWRX Control register 0x84 GRPWRX Status register 0x88 GRPWRX Configuration register 0x8C GRPWRX Physical Layer register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 287 Table 351. 0x80 - CTRL - control register RESERVED RxEN 31: 3 RESERVED Reset (RST) - resets complete core RESERVED Receiver Enable (RxEN) - enables receiver (should be done after the complete configuration of the receiver) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 288 (BUSYPOS) - Positive polarity of busy input signal (READYPOS) - Positive polarity of ready input signal (VALIDPOS) - Positive polarity of valid output signal (CLKRISE) - Rising clock edge in the middle of the serial data bit 3: 0 RESERVED GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 289: Packetwire Transmitter
(control), and for word transfer (address or data). Transmitted data should consist of multiples of eight bits otherwise the last bits will be lost. The message delimiter port GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 290: Operation
Enable (EN) - Set to one to enable the descriptor. Should always be set last of all the descriptor fields. Table 356.GRPWTX descriptor word 1 (address offset 0x4) ADDRESS 31: 0 Address (ADDRESS) - Pointer to the buffer area to where data will be fetched. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 291: Registers
Register 0x00 GRPWTX DMA Control register 0x04 GRPWTX DMA Status register 0x08 GRPWTX DMA Descriptor Pointer register 0x80 GRPWTX Control register 0x84 GRPWTX Status register 0x88 GRPWTX Configuration register 0x8C GRPWTX Physical Layer register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 292 Table 361. 0x80 - CTRL - control register RESERVED TxEN 31: 3 RESERVED Reset (RST) - resets complete core RESERVED Transmitter Enable (TxEN) - enables transmitter (should be done after the complete configuration of the transmitter) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 293 (READYPOS) - Positive polarity of ready input signal (VALIDPOS) - Positive polarity of valid output signal (CLKRISE) - Rising clock edge in the middle of the serial data bit (CLKMODE) - 0=when valid (default), 1=always (experimental) 2: 0 RESERVED GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 294: Spacewire Interface And Rmap Target
GR716 SpaceWire Interface and RMAP target The GR716 microcontroller comprises a SpaceWire interface with RMAP support (GRSPW2) units. The SpaceWire interface with RMAP controls its own external pins and has a unique AMBA address described in chapter 2.11. The nominal SpaceWire interface is connected via LVDS transceivers to external pins and the redundant interface is connected to external pins via the IOMUX.
Page 295: Operation
All packets arriving with the extended protocol ID (0x00) are stored to a DMA channel. This means that the hardware RMAP target will not work if the incoming RMAP packets use the extended proto- GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 296: Link Interface
The state of the FSM, credit counters, requests from the time-interface and requests from the DMA- interface are used to decide the next character to be transmitted. The type of character and the charac- GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 297 Figure 51. Schematic of the link interface receiver. 33.3.4 Dual port support With dual ports the transmitter drives an additional pair of data/strobe output signals and one extra receiver is added to handle a second pair of data/strobe input signals. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 298 An example of clock divisor and resulting link-rate, with a TXCLK frequency of 50 MHz, is shown in the table 365. Table 365.SpaceWire link-rate example with 50 MHz TXCLK Link-rate in Mbit/s Clock divisor value SDR output 16.67 12.5 8.33 7.14 6.25 5.56 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 299: Time-Code Distribution
INTCFG.NUMINT field. Either 1, 2, 4, or 32 interrupt numbers (in the range 0-31) can be sup- ported. When less than 32 interrupt numbers are supported it is programmable through the INTCFG GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 300 Each interrupt number has three corresponding timers, called the ISR timer, INT/ACK-timer, and ISR change timer. All three timers are implemented in GR716 with the width of 10 bits. A generic soft- ware can detect whether or not these timers are implemented in hardware, and how large they are, by probing the ISRTIMER, IATIMER, and ICTIMER registers respectively.
Page 301 33.5.4 Interrupt-code generation Interrupt-codes can be generated automatically due to a number of internal events. Which events that should force an interrupt-code to be sent, and what interrupt-number to use, is controlled from the GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 302: Receiver Dma Channels
1 N-Char is enough. If it is an RMAP packet with hardware RMAP enabled 3 N-Chars are needed since the command byte determines where the packet is processed. Packets smaller than these sizes are discarded. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 303 Channel enabled Last DMA channel Separate addressing RMAP enabled dma(n).addr* !dma(n).mask= defaddr*!defmask = rxaddr*!dma(n).mask rxaddr*!defmask Process RMAP Store packet to Discard packet DMA channel command Figure 52. Flow chart of packet reception. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 304 When new descriptors are added they must always be placed after the previous one written to the area. Otherwise they will not be noticed. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 305 ‘0’ and the nospill bit is ‘0’ the packets will be discarded. If nospill is ‘1’ the core waits until rxdescav is set and the characters are kept in the N-Char fifo during this time. If the fifo becomes full further N- char transmissions are inhibited by stopping the transmission of FCTs. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 306 If an AHB error occurs during reception the current packet is spilled up to and including the next EEP/EOP and then the currently active channel is disabled and the receiver enters the idle state. A bit in the channels control/status register is set to indicate this condition. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 307: Transmitter Dma Channels
The transmit descriptors are 16 bytes in size so the maximum number in a single table is 64. The dif- ferent fields of the descriptor together with the memory offsets are shown in the tables below. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 308 31: 0 Header address (HEADERADDRESS) - Address from where the packet header is fetched. Does not need to be word aligned. Table 370.GRSPW2 transmit descriptor word 2 (address offset 0x8) 24 23 RESERVED DATALEN GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 309 Lastly, if it occurs when status is written to the descriptor the packet has been successfully transmitted but the descriptor is not written and will continue to be enabled (this also means that no error bits are set in the descriptor for AHB errors). GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 310: Rmap
If there is a mismatch and a reply has been requested the error code in the reply is set to 3. Replies are sent if and only if the ack field is set to ‘1’. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 311 “Authorization failure” error code will be sent in the reply if a violation was detected even if the length field was zero. Also note that no data is sent in the reply if an error was detected i.e. if the status field is non-zero. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 312 The last control option for the target is the possibility to set the destination key which is found in a separate register. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 313 If alignment is before writ- violated nothing is done and ing, send error code is set to 10. If an AHB acknowledge error occurs error code is set to 1. Reply is sent. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 314: Amba Interface
A burst is always started when the FIFO is half-empty or if it can hold the last data for the packet. The burst containing the last data might have shorter length if the packet is not an even number of bursts in size. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 315: 33.10 Spacewire Plug-And-Play
0x0A (authorization failure) is sent. • RMAP read-modify-write command is replaced by a compare-and-swap command. The com- mand’s data fields shall contain the new data to be written, while the mask fields shall contain the GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 316 Device Information - Device Iden- read, tification - Device ID 0x00000009 SpaceWire Plug-and-Play - Unit Vendor PNPUVEND Device Information - Device Iden- read and Product ID tification - Unit Vendor and Prod- uct ID GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 317 Vendor ID (VEND) - SpaceWire vendor ID assigned at implementation time. 15: 0 Product ID (PROD) - Product ID assigned at implementation time. Table 378.0x00000001 - PNPVER - SpaceWire Plug-and-Play - Version 24 23 16 15 MAJOR MINOR PATCH RESERVED GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 318 Vendor and Product ID field has been written with a non-zero value, this bit will be set to 1. RESERVED 4: 0 Link count (LC) - Shows the number of router ports. Constant value of 0x13. Table 382.0x00000005 - PNPOA0 - SpaceWire Plug-and-Play - Owner Address 0 0x00000000 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 319 Unit serial number (USN) - Shows the unit serial number. This field is read-only through the SpaceWire Plug- and-Play protocol, however it is writable through the APB register (see section 33.11). Reset value is taken from the input signal PNPUSN. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 320 Network discovery (ND) - Constant value of 1, indicating that the link can be used for network discovery. Link type (LT) - Constant value of 1, indicating that the link is a SpaceWire link. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 321: 33.11 Registers
400 and described in detail in the subsequent tables. Addresses not listed in table 400 are reserved. A read access to a reserved register, or reserved field with a register, will always return zero, GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 322 Read-only. Writes have no effect. Readable and writable. Readable and writeable. Special condition for write, described in textual description of the bit-field. Write-clear. Readable, and cleared when written with a 1. Writing 0 has no effect. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 323 SpaceWire PnP Owner Address 1 0xF0 PNPOA2 SpaceWire PnP Owner Address 2 0xF4 PNPDEVID SpaceWire PnP Device ID 0xF8 PNPUVEND SpaceWire PnP Unit Vendor and Product ID 0xFC PNPUSN SpaceWire PnP Unit Serial Number GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 324 Tick-out IRQ (TQ) - Enables / disables AMBA interrupt generation when a valid time-code is received. Note that the CTRL.IE bit also must be set for this bit to have any effect. RESERVED Reset (RS) - Make complete reset of the SpaceWire node. Self clearing. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 325 SpaceWire RMAP enable, see section 3.1, otherwise the reset value is ’0’. Link Start (LS) - Start the link, i.e. allow a transition from ready-state to started-state. Link Disable (LD) - Disable the SpaceWire codec. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 326 DEFADDR.DEFADDR field are anded with the inverse of this field before the address check. 7: 0 Default address (DEFADDR) - Default address used for node identification on the SpaceWire net- work. Reset value: 254 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 327 TIMEIN[5:0] signals if TICKIN- RAW is asserted. Note that the register can be written, but that the written value is not transmitted, since the value is incremented before transmission. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 328 RX active (RX) - Is set to ‘1’ if a reception to the DMA channel is currently active, otherwise it is ‘0’. Abort TX (AT) - Set to one to abort the currently transmitting packet and disable transmissions. If no packet is currently being transmitted, the only effect is to disable transmissions. Self clearing. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 329 Note that it is only possible to set this bit to 1 if the TL bit is 0. This bit is automatically cleared when the SW-node encounters a descriptor which is disabled, or if a link error occurs during the transmis- sion of a packet, and the LE bit is set. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 330 The number of bits in this field depends on the size of the DMA receive descrip- tor table. The value of x is given by the formula: 9 + STS.NRXD 2: 0 RESERVED GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 331 AUTOACK / INTRXEXT register is set to 1 (even if the bit was already set when the code was received). GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 332 4:0 are set from the input signal IRQTXDEFAULT. Note that bits 4:0 of this field must be set to a value within the range defined by the NUMINT and BASEINT fields. A value outside the range will result in no interrupt-code being sent. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 333 Interrupt-code tick out mask register is set. Note that the number of implemented bits depends on the number of supported interrupts (INTC- TRL.NUMINT field). GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 334 1 in order for any interrupt- / interrupt-acknowledge-codes to be sent. Enable external interrupt (EE) - Enable the external interrupt mode, which enable the core to use and interpret the interrupt-acknowledge-code as interrupt 32-63. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 335 RL+1 cycle. The number of bits imple- mented for this field might be lower than the 31 depicted here. Any unimplemented bits are reserved. Reset value set from the input signal INTPRELOAD. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 336 Timer reload (RL) - The number of bits implemented for this field might be lower than the 31 depicted here. Any unimplemented bits are reserved. Reset value set from the input signal INTCRE- LOAD. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 337 SpaceWire Plug-and-Play - Owner Address 2 Table 430.0xF0 - PNPOA2 - SpaceWire Plug-and-Play - Owner Address 2 0x00000000 Note: Register is double mapped from SpaceWire Plug-and-Play address space into APB address space. See section 33.10 for details. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 338 Note: Register is double mapped from SpaceWire Plug-and-Play address space into APB address space. See section 33.10 for details. This register is read-only in SpaceWire Plug-and-Play interface, while it is writable from the APB address space. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 339: Spacewire - Time Distribution Protocol
CCSDS Time Codes through RMAP and support for latency measurement and correction. In this implementation the CCSDS Time Codes carried between the SpaceWire network is based on CCSDS Unsegmented Code format. The table below GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 340 (FS). The frequency synthesizer is incremented with a pre-calculated incre- ment value, which matches the available system clock frequency. The frequency synthesizer generates a tick every time it wraps around, which makes the ET time counter to step forward with the pre-cal- GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 341 The core is interfaced via an AMBA Advanced Peripheral Bus (APB) slave interface, providing a reg- ister view that is compatible with the Time Distribution Protocol (TDP). The core must be configured according to the requirement either as initiator or target. • Initializing initiator GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 342 Interrupt Enable register). Based on this interrupt the local time (ET counter) in initiator should be accessed from the Datation registers and used to calculate the time message needed to be transmitted. • Time message generation GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 343 Elapsed Time counter matches till the mapped SpaceWire Time-Code level (with a tolerance of previous value) and only modifies the local Elapsed Time if their is a mismatch. Since the GR716 tar- get is not implemented with a jitter and mitigation unit the synchronisation forces the target time (ET counter) with the time message received.
Page 344 RMAP transfer. When the latency values are written it will be adjusted to local time in the target. 34.3.10 Mitigation of jitter and drift No jitter and drift mitigation unit for SPWTDP is implemented in GR716. 34.3.11 External Datation The external signals latch and save are used to provide external datation services.
Page 345: Data Formats
1 34.5 Reference documents [CCSDS] Time Code Formats, CCSDS 301.0-B-4, www.CCSDS.org [SPW] Space engineering: SpaceWire - Links, nodes, routers and networks, ECSS-E-ST-50-12C [RMAP] Space engineering: SpaceWire - Remote memory access protocol, ECSS-E-ST-50-52C GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 346 Time-Stamp Elapsed Time 2 Rx 0x070 Time-Stamp Elapsed Time 3 Rx 0x074 Time-Stamp Elapsed Time 4 Rx 0x078 RESERVED 0x07C RESERVED 0x080 Time-Stamp SpaceWire Time-Code and Preamble Field Tx 0x084 Time-Stamp Elapsed Time 0 Tx GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 347 External Datation 0 Elapsed Time 3 0x124 External Datation 0 Elapsed Time 4 0x128 RESERVED 0x12C RESERVED 0x130-0x14F External Datation 1 Time 0x150-0x16F External Datation 2 Time 0x170-0x18F External Datation 3 Time 0x190-0x1FF RESERVED GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 348 ‘0’. (valid only when Mitigation unit available) Receiver Enable (only for target) Reset value: ‘0’. Transmit Enable (only for initiator) Reset value: ‘0’. Reset core. Makes complete reset when enabled. Reset value: ‘0’. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 349 Value of the Elapsed Time counter is to be incremented each time when the Fre- quency Synthesizer wraps around. Refer the spreadsheet provided along with this document to obtain this value. Reset value: Implementation dependent GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 350 9: 5 INRX Interrupt Received.(Distributed) The distributed interrupt number received by initiator or target. Reset value: 0b000000 4: 0 INTX Interrupt Transmitted.(Distributed) The distributed interrupt number transmitted by initiator or target. Reset value: 0b000000 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 351 Table 446.0x014 - STAT1 - Status Register 1 31 30 29 31: 30 RESERVED 29: 0 Increment Variation. The variation in FSINC while achieving the time synchroni- sation (only for target) Reset value: Implementation dependent (valid only when Mitigation unit available) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 352 Initialize or Synchronise local ET counter value (0 to 31). 34.6.9 Command Elapsed Time 1 Table 449.0x028 - CET1 - Command Elapsed Time 1 CET1 31: 0 CET1 Command Elapsed Time 1 Initialize or Synchronise local ET counter value (32 to 63) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 353 Table 453.0x040 - DPF - Datation Preamble Field 16 15 RESERVED 0x2F00 31: 16 RESERVED 15: 0 Datation Preamble Field The number of coarse and fine time implemented can be obtained from this Pre- amble Field. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 354 34.6.17 Datation Elapsed Time 3 Table 457.0x050 - DET3 - Datation Elapsed Time 3 DET3 31: 0 DET3 Datation Elapsed Time 3 CCSDS Time Code value (96 to 127) of local ET counter value. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 355 Time stamped local ET value (32 to 63) when distributed interrupt received. 34.6.22 Time Stamp Elapsed Time 2 Rx Table 462.0x06C - TR2 - Time Stamp Elapsed Time 2 Rx 31: 0 TR2 Time stamped local ET value (64 to 95) when distributed interrupt received. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 356 Field. 34.6.26 Time Stamp Elapsed Time 0 Tx Table 466.0x084 - TT0 - Time Stamp Elapsed Time 0 Tx 31: 0 TT0 Time stamped local ET value (0 to 31) when distributed interrupt transmitted. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 357 Table 471.0x0A0 - LPF - Latency Preamble Field 16 15 RESERVED 0x2F00 31: 16 RESERVED 15: 0 Latency Preamble Field The number of coarse and fine time implemented can be obtained from this Pre- amble Field. (only for target) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 358 34.6.36 Latency Elapsed Time 4 Table 476.0x0B4 - LE4 - Latency Elapsed Time 4 24 23 RESERVED 31: 24 LE4 Latency Value (128 to 135) written by initiator. (only for target) 23: 0 RESERVED GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 359 (only for initiator) Generated when SpaceWire Time-Code is received (only for target) Generated when the target is initialized or synchronized with initiator (only for target) The interrupts are cleared by writing value 1 on respective bits. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 360 External Datation 0 Elapsed Time 0 Table 482.0x114 - ED0ET0 - External Datation 0 Elapsed Time 0 ED0ET0 31: 0 ED0ET0 External Datation Elapsed Time 0 Latched CCSDS Time Code value (0 to 31) of local ET counter. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 361 The Definition of External Datation 1 Time, External Datation 2 Time and External Datation 3 Time registers are exactly same as External Datation 0 Time Registers (i.e. External Datation 0 Preamble Field and External Datation 0 Elapsed Time 0,1,2,3,4). GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 362: General Purpose Timer Unit With Watchdog
RESET_OUT_N output signal when expired. The watchdog timer also implements a window func- tionality. This enables a decrementing counter which reloads each time the timer is reloaded. If the timer is reloaded and the window counter hasn’t reach zero, this will also assert the RESET_OUT_N output. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 363 The watchdog window functionality is enabled when the bit field WDOGWINC is greater than 0x0 and smaller or equal to 0xFFFF. The programmed number specify the number of system clock cycles between 2 watchdog reload events. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 364: Registers
Timer 6 reload value register 0x80003068 Timer 6 control register 0x8000306C Timer 6 latch register 0x80003070 Timer 7 counter value register 0x80003074 Timer 7 reload value register 0x80003078 Timer 7 control register 0x8000307C Timer 7 latch register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 365 Table 489.0x04 - SRELOAD - Scaler reload value register 16-1 RESERVED SCALER RELOAD VALUE all 1 16-1: 0 Scaler reload value. Writes to this register also set the scaler value. Any unused most significant bits are reserved. Always read as ‘000...0’. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 366 Table 492.0xn0, when n selects the times - TCNTVALn - Timer n counter value register 32-1 TCVAL 32-1: 0 Timer Counter value. Decremented by 1 for each prescaler tick. Any unused most significant bits are reserved. Always reads as ‘000...0’. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 367 Enable (EN): Enable the timer. 35.3.8 Timer N Latch Register Table 495.0xnC, when n selects the times - TLATCHn - Timer n latch register LTCV 31: 0 Latched timer counter value (LTCV): Valued latched from corresponding timer. Read-only. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 368: General Purpose Timer Unit (Secondary)
Simultaneous start of multiple timers are supported via timer configuration register CONFIG.TIM- EREN. To simultaneously start two or more counters set the corresponding bits in the register CON- FIG.TIMEREN. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 369: Registers
Timer 6 reload value register 0x80004068 Timer 6 control register 0x8000406C Timer 6 latch register 0x80004070 Timer 7 counter value register 0x80004074 Timer 7 reload value register 0x80004078 Timer 7 control register 0x8000407C Timer 7 latch register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 370 Table 498.0x04 - SRELOAD - Scaler reload value register 16-1 RESERVED SCALER RELOAD VALUE all 1 16-1: 0 Scaler reload value. Writes to this register also set the scaler value. Any unused most significant bits are reserved. Always read as ‘000...0’. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 371 Table 501.0xn0, when n selects the times - TCNTVALn - Timer n counter value register 32-1 TCVAL 32-1: 0 Timer Counter value. Decremented by 1 for each prescaler tick. Any unused most significant bits are reserved. Always reads as ‘000...0’. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 372 Enable (EN): Enable the timer. 36.3.8 Timer N Latch Register Table 504.0xnC, when n selects the times - TLATCHn - Timer n latch register LTCV 31: 0 Latched timer counter value (LTCV): Valued latched from corresponding timer. Read-only. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 373: I2C To Ahb Bridge
GR716 C to AHB bridge The GR716 microcontroller comprises an I2C to AHB bridge (I2C2AHB). The I2C to AHB bridge controls its own external pins and has a unique AMBA address described in chapter 2.11. The I2C to AHB bridge is connected to external pins via the IOMUX.
Page 374: Operation
‘1’ the master would have acted as a receiver during this phase of the transfer. After the data byte has been transferred the receiver acknowledges the byte and the master generates a STOP condi- tion to complete the transfer. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 375 Updated after each AMBA access (read only) Memory exception (MEXC) - ‘1’ if core receives AMBA ERROR response. Updated after each AMBA access (read only) DMA active (DMAACT) - ‘1’ if core is currently performing a DMA operation. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 376 1. Generate START condition 2. Send I2C memory address with the R/W bit set to ‘0’. 3. Send four byte AMBA address, all zero. 4. Send four bytes to write to the specified address GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 377 The core will set the configuration register bit PROT if an access is attempted outside the allowed address range. This bit is updated on each AHB access and will be cleared by an access inside the allowed range. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 378: Registers
C slave registers Table 506.I APB address offset Register 0x00 Control register 0x04 Status register 0x08 Protection address register 0x0C Protection mask register 0x10 I2C slave memory address register 0x14 I2C slave configuration address register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 379 Protection Mask Register Table 510.0x0C - PMASK - Protection mask register PROTMASK 31 : 0 Protection mask (PROTMASK) - Selects which bits in the Protection address register that are used to define the protected memory area. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 380 Table 512.0x14 - SLVCFG - I2C slave configuration address register RESERVED I2CCFGADDR 0x51 31 : 7 RESERVED 6 : 0 I2C slave configuration address (I2CCFGADDR) - Address that slave responds to for configuration register accesses. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 381: I2C Master
The I C-master core is a modified version of the OpenCores I C-Master with an AMBA APB inter- face. The core is compatible with Philips I C standard and supports 7- and 10-bit addressing. Stan- GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 382: Operation
STOP condi- tion to complete the transfer. Section 38.2.3 contains three more example transfers from the perspec- tive of a software driver. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 383 To write a byte to a slave the I C-master must generate a START condition and send the slave address with the R/W bit set to ‘0’. After the slave has acknowledged the address, the master transmits the GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 384 To perform sequential reads the master can iterate over steps 13 - 15 by not setting the ACK and STO bits in step 13. To end the sequential reads the ACK and STO bits are set. Consult the documentation of the I C-slave to see if sequential reads are supported. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 385: Registers
Table 513.I APB address offset Register 0x00 Clock prescale register 0x04 Control register 0x08 Transmit register* 0x08 Receive register** 0x0C Command register* 0x0C Status register** 0x10 Dynamic filter register * Write only ** Read only GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 386 RW bit. ‘1’ reads from the slave and ‘0’ writes to the slave. 38.3.4 I C-Master Receive Register Table 517.0x08 - RX - I C-master receive register RESERVED RDATA 31 : 8 RESERVED Receive data (RDATA) - Last byte received over I C-bus. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 387 Dynamic filter reload value (FILT) - This field sets the reload value for the dynamic filter counter. The core will ignore all pulses on the bus shorter than 2 * (system clock period) and may also ignore pulses shorter than 2 * 2 * (system clock period) - 1. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 388: I2C Slave
C standard and supports 7- and 10-bit addressing with an optionally software programmable address. Standard-mode (100 kb/s) and Fast-mode (400 kb/s) oper- ation are supported directly. External pull-up resistors must be supplied for both bus lines. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 389: Operation
‘1’ the master would have acted as a receiver during this phase of the transfer. After the data byte has been transferred the receiver acknowledges the byte and the master generates a STOP condi- tion to complete the transfer. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 390 If the receive register is free the value of RMOD determines if the core should continue to listen to the bus for the master’s next action or if the core should drive SCL low to force the master GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 391: Registers
The core is programmed through registers mapped into APB address space. C slave registers Table 521.I APB address offset Register 0x00 Slave address register 0x04 Control register 0x08 Status register 0x0C Mask register 0x10 Receive register 0x14 Transmit register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 392 Enable core (EN) - Enables core. When this bit is set to ‘1’ the core will react to requests to the address set in the Slave address register. If this bit is ‘0’ the core will keep both SCL and SDA inputs in Hi-Z state. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 393 RESERVED RECBYTE 31 : 8 RESERVED Received Byte (RECBYTE) - Last byte received from master. This field only contains valid data if the Byte received (REC) bit in the status register has been set. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 394 GR716 39.3.6 Transmit Register Table 527.0x14 - TX - Transmit register RESERVED TRABYTE 31 : 8 RESERVED Transmit Byte (TRABYTE) - Byte to transmit on the next master read request. Reset value: Undefined GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 395: Interrupt Controller
(0x8001A000 - 0x8001AFFF) Figure 65. GR716 Interrupt controller bus connection It is not possible to disable clock to the interrupt controller since the interrupt controller is used to wake-up the processor from deep-sleep i.e. when the clock to the processor is disabled.
Page 396: Operation
For extended interrupt the extended acknowledge register will identify which extended interrupt that was most recently acknowledged. This register can be used by software to invoke the appropriate interrupt handler for the extended interrupts. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 397 The core can be configured to stamp only the first occurrence of an interrupt or to continuously stamp interrupts. The behavior is controlled via the Keep Stamp (KS) field in the Interrupt Timestamp Con- GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 398 Otherwise software should make sure that the watchdog signal is deas- serted before re-enabling interrupts during interrupt handling. The GR716 microcontroller supports soft watchdog events from GPTIMER0 timer 6 and GPTIMER0 timer 7. 40.2.7 Dynamic processor reset start address The interrupt controller can be used to start processor execution from a specified start address.
Page 399 40.2.8 Restart processor from internal on-chip memory To restart the processor from on-chip instruction memory set the register PROCBOOT- ADR=0x31000001. 40.2.9 Restart processor from external SRAM memory To restart the processor from on-chip instruction memory set the register PROCBOOT- ADR=0x40000001. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 400: Registers
Interrupt assertion timestamp 3 register 0x8000213C Interrupt acknowledge timestamp 3 register 0x80002200 Processor boot address register 0x80002300 + 0x4 * m Interrupt map register m * Number of interrupts in LEON3FT microcontroller is 64 hence m is 16 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 401 Table 532. 0x8000200C - ICLEAR - Interrupt Clear Register 16 15 EIC[31:16] IC[15:1] 31:16 Extended Interrupt Clear n (EIC[n]) 15:1 Interrupt Clear n (IC[n]) - Writing ‘1’ to IC[n] will clear interrupt n Reserved GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 402 WDOGIRQ field being set in the controller’s Interrupt Pending Register. Configurable soft watchdog inputs: Bit #0 - Enable soft watchdog for GPTIMER0 timer 7 Bit #1 - Enable soft watchdog for GPTIMER0 timer 6 Bit #2 to Bit #15 are unused GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 403 Timestamp Counter (TCNT) - Current value of timestamp counter. The counter increments when- ever a TSISEL field in a Timestamp Control Register is non-zero. The counter will wrap to zero upon overflow and is read only. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 404 Timestamp Counter (TCNT) - Current value of timestamp counter. The counter increments when- ever a TSISEL field in a Timestamp Control Register is non-zero. The counter will wrap to zero upon overflow and is read only. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 405 Timestamp Interrupt Select (TSISEL) - This field selects the interrupt number (1 - 31) to timestamp. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 406 Timestamp Interrupt Select (TSISEL) - This field selects the interrupt number (1 - 31) to timestamp. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 407 Table 550. 0x80002138 - ITSTMPAS3 - Interrupt Assertion Timestamp 3 register TASSERTION 31:0 Timestamp of Assertion (TASSERTION) - The current Timestamp Counter value is saved in this register when timestamping is enabled and the interrupt line selected by TSISEL is asserted. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 408 Timestamp of Acknowledge (TACKNOWLEDGE) - The current Timestamp Counter value is saved in this register when timestamping is enabled, the Acknowledge Stamped (S2) field is ‘0’, and the interrupt selected by TSISEL is acknowledged by a processor connected to the interrupt controller. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 409 Interrupt bus map n (ID[n*4+3]) - Map register for bus interrupt line [n*4+3] Number of interrupts in LEON3FT microcontroller is 64 hence n is 16 Default values for interrupt bus ID is found in table 557 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 410 ID17 GRGPIO ID18 GRGPIO ID19 GRGPIO 0x80002314 IRQMAP5 ID20 GRGPIO ID21 GRCAN0&1 ID22 GRCAN0&1 ID23 GRCAN0&1 0x80002318 IRQMAP6 ID24 APBUART0 ID25 APBUART1 ID26 ID27 0x8000231C IRQMAP7 ID28 ADC0 ID29 ADC1 ID30 ADC2 ID31 ADC3 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 411 SPICTRL ID50 I2CM ID51 I2CM 0x80002334 IRQMAP13 ID52 SPIMCTRL ID53 GPTIMER1 ID54 GPTIMER1 ID55 GPTIMER1 0x80002338 IRQMAP14 ID56 GPTIMER1 ID57 GPTIMER1 ID58 GPTIMER1 ID59 GPTIMER1 0x8000233C IRQMAP15 ID60 GRGPIOSEQ0 ID61 GRGPIOSEQ1 ID62 ID63 AHBSTAT GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 412: Leon3 Statistics Unit
AHB SPLIT responses. Filtered on CPU/AHBM if SU(1) = ‘1’ 0x4F AHB SPLIT delay. Filtered on CPU/AHBM if SU(1) = ‘1’ 0x50 AHB bus locked. Filtered on CPU/AHBM if SU(1) = ‘1’ 0x51-0x5F Reserved GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 413 0x80 to 0x83 is used for the main system bus and 0x80 to 0x87 is used for the DMA bus 0x80* Request by LEON3FT 0x81* Request by DMA => Main bridge 0x82* Request by Scrubber 0x80** Request by Debug UART 0x81** Request by 1553 core 0x82** Request by SpaceWire core GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 414: Using The Leon3 Statistics Unit
Counter 1 control register 0x108 Counter 2 control register 0x10C Counter 3 control register 0x200 Counter 0 max/latch register 0x204 Counter 1 max/latch register 0x208 Counter 2 max/latch register 0x20C Counter 3 max/latch register 0x300 Timestamp register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 415 CPU or AHB master to monitor.(CPU/AHBM) - The value of this field does not matter when select- ing one of the events coming from the Debug Support Unit or one of the external events. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 416 CL field is set, then the current counter value will be cleared when the counter value is saved into this register. 41.3.4 Timestamp Register Table 563.0x300 - TSTAMP - Timestamp register TSTAMP Timestamp (TSTAMP) - Timestamp taken at latch of counters GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 417: Memory Scrubber And Status Register
GR716 Memory Scrubber and Status Register The GR716 microcontroller have 1 AHB Memory Scrubber and Status Register unit (MEMSCRUB). The MEMSCRUB unit monitors the system main bus or scrubber bus for accesses triggering an error response, and for correctable errors signaled from fault tolerant slaves on the bus. The MEMSCRUB unit can be programmed to scrub memories.
Page 418: Overview
The memory scrubber can be commanded to scrub a certain memory area, by writing a start and end address to the scrubbers start/end registers, followed by writing “00” to the scrub mode field and ‘1’ to the scrub enable bit in the scrubber control register. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 419 42.2.8 Interrupts After an interrupt is generated, either the NE bit or the DONE bit in the status register is set, to indi- cate which type of event caused the interrupt. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 420: Registers
0xFFF0001C Scrubber range high address register 0xFFF00020 Scrubber position register 0xFFF00024 Scrubber error threshold register 0xFFF00028 Scrubber initialization data register 0xFFF0002C Scrubber second range start address register 0xFFF00030 Scrubber second range end address register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 421 31: 22 Interrupt threshold value for global correctable error count 21: 14 Interrupt threshold value for global uncorrectable error count 13: 2 RESERVED CECTE: Correctable error count threshold enable UECTE: Uncorrectable error count threshold enable GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 422 Table 570. 0x18 - RANGEL - Scrubber range low address register SCRUBBER RANGE LOW ADDRESS 31: 0 The lowest address in the range to be scrubbed The address bits below the burst size alignment are constant ‘0’ GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 423 Table 572. 0x20 - POS - Scrubber position register SCRUBBER POSITION 31: 0 The current position of the scrubber while active, otherwise zero. The address bits below the burst size alignment are constant ‘0’ GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 424 Table 576. 0x30 - RANGEH2 - Scrubber second range high address register SCRUBBER RANGE HIGH ADDRESS 31: 0 The highest address in the second range to be scrubbed The address bits below the burst size alignment are constant ‘1’ GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 425: Spi To Ahb Bridge
GR716 SPI to AHB bridge The GR716 microcontroller comprises a SPI to AHB bridge (SPI2AHB). The SPI to AHB bridge con- trols its own external pins and has a unique AMBA address described in chapter 2.11. The SPI to AHB bridge is connected to external pins via the IOMUX.
Page 426: Transmission Protocol
All AMBA accesses are done in big endian format. The first byte sent to or from the slave is the most significant byte. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 427: System Clock Requirements And Sampling
‘1’ allows higher SCK frequencies to be used but will also result in a data fetch as soon as the current data has been read out. This means that RAHEAD may not be suitable when accessing FIFO interfaces. (read/write) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 428 PADDR and PMASK the following way: Protection address, bits 31:16 ( [31:16]): ahbaddrh PADDR Protection address, bits 15:0 ( [15:0]): ahbaddrl PADDR GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 429: Registers
43.5 Registers The core is programmed through registers mapped into APB address space. Table 579.APB registers APB address offset Register 0x00 Control register 0x04 Status register 0x08 Protection address register 0x0C Protection mask register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 430 Protection Mask Register Table 583.0x0C - PMASK - Protection mask register PROTMASK 31 : 0 Protection mask (PROTMASK) - Selects which bits in the Protection address register that are used to define the protected memory area. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 431: Spi Controller
GR716 SPI Controller The GR716 microcontroller comprises two separate SPI controller (SPICTRL) units. Each SPI con- troller unit controls its own external pins and has a unique AMBA address described in chapter 2.11. Each SPI controller unit control and status registers are located on the APB bus in the address range from 0x80390000 to 0x803AFFFF.
Page 432: Operation
SCK. The figure does not include the MISO signal, the behavior of this line is the same as for the MOSI signal. However, due to synchronization issues the MISO signal will be delayed when the core is operating in slave mode, please see section 44.2.5 for details. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 433 Event register bit Not empty (NE) will be asserted. The receive register will only contain valid data if the Not empty bit is asserted and software should not access the receive register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 434 When the core is configured for master operation it will transmit a word when there is data available in the transmit queue. When the transmit queue is empty the core will drive SCK to its idle state. If the GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 435: Registers
APB address offset Register 0x00 Capability register 0x04-0x1C Reserved 0x20 Mode register 0x24 Event register 0x28 Mask register 0x2C Command register 0x30 Transmit register 0x34 Receive register 0x38 Slave Select register 0x3C Automatic slave select register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 436 Enable core (EN) - When this bit is set to ‘1’ the core is enabled. No fields in the mode register should be changed while the core is enabled. This can bit can be set to ‘0’ by software, or by the core if a multiple-master error occurs. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 437 This bit can only be set if the TWEN field of the Capa- bility register is set to ‘1’. Ignore SPISEL input (IGSEL) - If this bit is set to ‘1’ then the core will ignore the value of the SPI- SEL input. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 438 TIP status bit, and automatic slave select toggling at the end of a transfer, when the clock phase (CP field) is ‘0’. RESERVED (R) - Read as zero and should be written as zero to ensure forward compatibility. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 439 Not full (NF) - This bit is set when the transmit queue has room for one or more words. It is cleared automatically by the core when the queue is full, writes have no effect. 7 : 0 RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 440 Transmit data (TDATA) - Writing a word into this register places the word in the transmit queue. This register will only react to writes if the Not full (NF) bit in the Event register is set. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 441 ASEL field in the Mode register is set to ‘1’. After a transfer has been completed the core’s slave select signals are assigned the original value in the slave select register. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 442: Spi For Space Slave Controller
GR716 SPI for Space Slave Controller The GR716 microcontroller comprises an SPI for Space Slave controller (SPI4S). The SPI for Space Slave controller controls its own external pins and has a unique AMBA address described in chapter 2.11. The nominal SPI for Space Slave interface is connected via LVDS transceivers to external pins and the redundant interface is connected to external pins via the IOMUX.
Page 443: Implementation Of Spi Protocols
(0x55) being transferred MSb first over the SPI bus under the four different modes. Note that the idle state of the MOSI line is ‘1’ and that CPHA = 0 means that the devices must have data ready before GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 444: Spi 2 Protocol Handler
The message format transferred between a SPI master and SPI slave device is defined below. Table 594. Example message format (write data) Signal Message Header Payload Payload CRC MOSI Command #1 Command #2 Data CRC-16 MISO Response #1 Response #2 0x0000 0x0000 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 445: Message Header - Command Token
The number of payload words that will be transmitted in the current message. The number should not include the command token and the CRC checksum appended at the end of the message. Sub-address This field provide additional sub-address location for write and read commands. CRC-4 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 446 If the prefix and spare bits does not match or if the calculated CRC-4 does not match the expected value then the RESET_SPI command is discarded. Time synchronization command GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 447 <CMDTOKEN> < CRC-16> The SPI slave device after receiving the READBACK_CMD send the previous command token trans- mitted by the SPI master. This command is useful only when some other command (other than GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 448 0x00 MOSI: The command can be used to notify the READ_ADDR <CR1> slave about the address from which the data <CR2> to the master is read, used for READ_SA <CRC-16> command. MISO: <all zeros> GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 449 Any other commands which are not implemented is received then the command token is discarded and Status illegal command (SIC) bit is enabled and also transmitted to master as part of the next response token. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 450 (with a and write, this bit is delay of one com- enabled when an mand) AHB error is reported. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 451: Redundancy
The intention is to keep only one bus active for normal operation but using the redundant bus to achieve switchover. The SPI protocol 2 implementa- tion supports dedicated commands to achieve the activation and deactivation of interfaces. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 452: Registers
Reset (RESET) - Resets all the registers in the core except time registers (TIME1, TIME2) and core enable registers (ENN and ENR). Enable redundant port transfer (ENR) - Enable bit for redundant port transfer. Enable nominal port transfer (ENN)- Enable bit for nominal port transfer. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 453 Nominal Receive data (NRDATA) - This register contains received data from the nominal port. Valid only for SPI protocol 0 and 1. 45.8.5 Redundant Receive Register Table 615.0x10 - RRDATA - Redundant receive register RRDATA GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 454 Sync command received interrupt enable (SYNCE). Valid only for SPI protocol 2. Data received in redundant port interrupt enable (RXRE).Valid only for SPI protocol 0 and 1. Data received in nominal port interrupt enable (RXNE). Valid only for SPI protocol 0 and 1. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 455 Time 1 register (TIME1) - Provides the most significant 32 bits of the time register. This is a status (read only) register, the contents of this register is a reflection of the time modified/incremented using the sync and tick command respectively. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 456 Configuration read address (CONFR) - Defines the base address for the memory area where the core is allowed to make accesses. This is a status (read only) register, the contents of this register can be modified by the configuration read address command. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 457: Spi Memory Controller
GR716 SPI Memory Controller The GR716 microcontroller comprises 2 separate SPI memory controller units (SPIMCTRLx). Each SPI memory controller unit controls its own external pins and has a unique AMBA address described in chapter 2.11. SPI memory controller unit 0 (SPIMCTRL0) has dedicated external signals, while SPI memory controller unit 1 (SPIMCTRL1) has access to external signals via IO switch matrix described in section 2.5.
Page 458: Overview
1. Check Status register and verify that the BUSY and DONE bits are cleared. Also verify that the core is initialized and not in error mode. 2. Optionally enable DONE interrupt by setting the Control register bit IEN. 3. Write command to Transmit register. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 459 Dummy Byte (0x1) MOSI Data #1 Data #2 MISO High Impedance Figure 81. Read Data Bytes at higher speed (FAST_READ) Instruction sequence and Data-Out sequence The expected read performance is determined by the following factors: • Scaler mode (CTRL.EAS) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 460 If an uncorrectable EDAC error is detected during a read operation, the MERR bit in the EDAC Status Register will be set and an error response will be generated on the AHB access. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 461: Registers
The core is programmed through registers mapped into AHB address space. Table 623.SPIMCTRL registers AHB address offset Register 0x00 Configuration register 0x04 Control register 0x08 Status register 0x0C Receive register 0x10 Transmit register 0x14 EDAC configuration register 0x18 EDAC status register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 462 Accesses to the ROM area should only be performed when this bit is set to ‘1’. Core busy (BUSY) - This bit is set to ‘1’ when the core is performing an SPI operation. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 463 Enable EDAC BCH Protection (EE) - Enables BCH protection and correction 46.3.7 EDAC Status Register Table 630.0x18 - ESTAT - EDAC Status register RESERVED MERR 31 :2 RESERVED Data word with multiple bit errors has been detected Correctable Errors has been detected GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 464: Amba Protection Unit
GR716 AMBA Protection Unit The GR716 microcontroller comprises two separate AMBA memory protection units (MEMPROT). The MEMPROT units described in this section have the capability to detect and protect memory areas from write accesses. The first AMBA memory protection units (MEMPROT0) is connected to Main AHB bus and the sec- ond AMBA memory protection units (MEMPROT1) is connected to the DMA AMBA bus.
Page 465 Access control for CPU and BRIDGE on APB bus 1 0x80005144 Access control for Scrubber on APB bus 1 0x80005148 - 0x8000514F Not used 0x80005150 Access control for DMA controller #0 and # 1 on APB bus 1 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 466 Protection Segment 3 Configuration register 0x8010A040 - 0x8010AFFF Not used 47.3.1 System Protection register description This chapter specifies access control registers for peripherals and registers accessible 0x40000000 to 0x4FFFFFFF and the range 0x80000000 to 0x8041FFFF. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 467 G0 - Grant LEON3FT processor exclusive write permission 15: 1 RESERVED EN - Enable Memory Protection for specified memory segments. This bit will grant exclusive write permission to specified masters within protected memory segment GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 468 B15 B14 B13 B12 B11 B10 B9 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 469 Modular Timer Unit 0 (B13) Modular Timer Unit 1 (B12) Memory Protection Unit for system bus (B11) Clock gating configuration register unit 0 (B10) Clock gating configuration register unit 1 (B9) Configuration and test registers (B8) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 470 On-chip Instruction memory control registers (B5) CCSDS TDP / SpaceWire I/F (B4) IO Mux configuration register (B3) CCSDS TDP / SpaceWire I/F (B2) Test register used for test purpose (B1) Slave UART configuration (B0) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 471 B15 B14 B13 B12 B11 B10 B9 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 472 MIL-STD-1553B Interface (B14) CAN Controller with DMA (B13) CAN Controller with DMA (B12) SPI to AHB Bridge (B11) I2C to AHB Bridge (B10) Stand alone DMA unit 0 (B9) Stand alone DMA unit 1 (B8) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 473 Stand alone DMA unit 3 (B6) Memory protection for DMA bus (B5) CCSDS TDP / SpaceWire I/F (B4) Brown-Out detection control registers (B3) PLL control registers (B2) PacketWire Receiver with DMA (B1) PacketWire Transmitter with DMA (B0) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 474 B15 B14 B13 B12 B11 B10 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 475 General Purpose I/O port 32 to 64 (A2) I2C-master 0 (A1) I2C-master 1 (A0) Generic UART 0 (B15) Generic UART 1 (B14) Generic UART 2 (B13) Generic UART 3(B12) Generic UART 4 (B11) Generic UART 5 (B10) unused unused GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 476 External ADC / DAC Interface (B7) SPI Controller 0 (B6) SPI Controller 1 (B5) PWM generator (B4) General Purpose I/O port 0 to 31(B3) General Purpose I/O port 32 to 64 (B2) I2C-master 0 (B1) I2C-master 1 (B0) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 477 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 31: 16 Not Used GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 478 I2C-slave 0 (B3) I2C-slave 1 (B2) PWM generator 1 (B1) SPI for Space slave (B0) ADC0 (B15) ADC1 (B14) ADC2 (B13) ADC3 (B12) ADC4 (B11) ADC5 (B10) ADC6 (B9) ADC7 (B8) DAC0 (B7) DAC1 (B6) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 479 ADC2 (B13) ADC3 (B12) ADC4 (B11) ADC5 (B10) ADC6 (B9) ADC7 (B8) DAC0 (B7) DAC1 (B6) DAC2 (B5) DAC3 (B4) I2C-slave 0 (B3) I2C-slave 1 (B2) PWM generator 1 (B1) SPI for Space slave (B0) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 480 SADDR - Start address of segment. Start address should be in the range 0x30000000 to 0x31FFFFFF. Table 654. 0x8010A5008 + segment*0x10 - PEA - Protection Segment End Address register EADDR 31: 0 EADDR - End address of segment. End address should be in the range 0x30000000 to 0x31FFFFFF. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 481: Example Of Configure And Use The Memory Protection
(For this example we use segment number #0 but any segment can be used for protec- tion)  PSA0.SADDR = 0x40100000 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 482 APB0PROT0, APB1PROT1, APBPROT2 and APBPROT3. To deny all DMA controllers access: APB1PROT2.A9 = 0x1 APB1PROT2.A10 = 0x1 APB1PROT2.B9 = 0x1 APB1PROT2.B10 = 0x1 APB1PROT3.A9 = 0x1 APB1PROT3.A10 = 0x1 APB1PROT3.B9 = 0x1 APB1PROT3.B10 = 0x1 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 483: Serial Debug And Remote Access Interface
DSU_EN to low. The second serial debug interface unit is to be used for remote access of the GR716 microcontroller in mission mode i.e. when DSU_EN is low. The second unit is available via the IO switch matrix described in chapter 2.5.
Page 484: Overview
Figure 85. Data frame Write Command 11 Length -1 Addr[31:24] Addr[23:16] Addr[15:8] Addr[7:0] Data[31:24] Data[23:16] Data[15:8] Data[7:0] Send Read command 10 Length -1 Addr[31:24] Addr[23:16] Addr[15:8] Addr[7:0] Send Receive Data[31:24] Data[23:16] Data[15:8] Data[7:0] Figure 86. Commands GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 485: Registers
= (((system_clk*10)/(baudrate*8))-5)/10 48.3 Registers The core is programmed through registers mapped into APB address space. Table 656.AHB UART registers APB address offset Register AHB UART status register AHB UART control register AHB UART scaler register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 486 Counter State (TCNT) - Internal Counter state 48.3.3 AHB UART scaler register Table 659.0x0C - SCALER - AHB UART scaler register 18 17 RESERVED SCALER RELOAD VALUE 0x3FFFB 17: 0 Baudrate scaler reload value = (((system_clk*10)/(baudrate*8))-5)/10. Reset value: “3FFFF“. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 487: Ahb Status Registers
GR716 AHB Status Registers The GR716 microcontroller have 2 separate AHB Status Register units (AHBSTAT). The 2 separate AHB Status Register units AHBSTAT0 and AHBSTAT1 monitors the DMA bus and the system bus respectively for accesses triggering an error response.
Page 488: Registers
APB address offset Registers AHB Status Register unit #1 (AHBSTAT1) 0x8000A000 AHB Status register 0x8000A004 AHB Failing address register AHB Status Register unit #1 (AHBSTAT2) 0x80306000 AHB Status register 0x80306004 AHB Failing address register GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 489 The HSIZE signal of the AHB transaction that caused the error 49.3.2 AHB Failing address register Table 662.0x04 - AHBFAR - AHB Failing address register AHB FAILING ADDRESS 31: 0 The HADDR signal of the AHB transaction that caused the error. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 490: Trace Buffer
GR716 Trace buffer The GR716 microcontroller have 2 separate AMBA trace buffer (AHBTRACE) units. The AHB- TRACE units described in this section have the capability to trace all transactions on the main AHB bus and Debug AHB bus. The first AMBA trace buffer (AHBTRACE0) is tracing the Main AHB bus and the second AMBA trace buffer (AHBTRACE1) is tracing the DMA AMBA bus.
Page 491: 50.2.1 Overview
Active when HTRANS is SEQUENTIAL or NON-SEQUENTIAL, slave has asserted HREADY and the HWRITE input is low. write Write access Active when HTRANS is SEQUENTIAL or NON-SEQUENTIAL, slave has asserted HREADY and the HWRITE input is high. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 492: Using The Ahb Trace Buffer
50.3 Using the AHB trace buffer The debug monitor GRMON3 has build-in support for using AHB trace buffer. For more information see chapter for using the trace buffer in the GRMON3 User’s Manual [GRMON3]. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 493: Registers
Filter Reads (FR) - If this bit is set to ‘1’, read accesses will not be included in the trace buffer. Filter Writes (FW) - If this bit is set to ‘1’, write accesses will not be included in the trace buffer. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 494 Slave Mask (SMASK) - If SMASK[n] is set to ‘1’, the trace buffer will not save accesses performed to slave n. 15: 0 Master Mask (MMASK) - If MMASK[n] is set to ‘1’, the trace buffer will not save accesses per- formed by master n. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 495 Table 671.Trace buffer AHB breakpoint mask register BMASK[31:2] LD ST rw rw 31: 2 Breakpoint mask (BMASK) - Bits 31:2 of breakpoint mask Load (LD) - Break on data load address Store (ST) - Break on data store address GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 496: Boot Rom
51.1 Overview The GR716 microcontroller contains a on-chip Boot ROM for low-level initialization and optional self-testing, standby and application loading. The Boot ROM contains instructions executed by the CPU. The Boot ROM may be configured via bootstraps signals controlled by the user at reset.
Page 497: Rom Architecture
The Standby mode is entered when the GR716 microcontroller is configured via bootstraps to be con- figured remotely via external interface, for example SpW, SPI, UART, etc. The watchdog timer is ini- tialized.
Page 498 PSR_CWP Default CWP PSR_PIL Processor interrupt level for application and remote access PIL_EF FPU disabled fp_start 0x3000FF00 Frame pointer sp_start 0x3000FEA6 Stack pointer boot_image_header 0x3000FF48 Boot image header start boot_report 0x3000FFF8 Boot report start GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 499 External I2C Memory Non-Volatile R/W Application software to be copied into the on-chip RAM (I2CMST) and executed from on-chip RAM (Application software can be available at two different areas for dual module redundancy check) GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 500 In case of using the ASW container the application can read and check the latest ASW header located in the data memory on address specified in table 672 and ASW header format in table 677. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 501 The image header start is always set to ’boot_image_header’ from the end of the last address in the local data memory. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 502: Loader Description
See sections below for more information about which pins are used for respective interface. Full access is granted to the unit accessing the GR716 Microcontroller via the selected remote control and access interface. When remote control unit upload new software to the GR716 Microcontroller the remote unit can reset and re-start the processor via the interrupt controller unit, see chapter 40 for more information.
Page 503: State At Handover To Application Software
Information on which pins used to connect to the external SPI bus is described in Table TBD. 51.4.4 UART There are two AHBUART interfaces on the GR716, only the AHBUART connected directly to the AHB DMA bus is used for the remote control in Standby mode.
Page 504: Boot Source Requirements
Redundant ASW load image • Watchdog timer SPI Memory: • BCH EDAC protection • ASW load image protection • Redundant ASW load image with CRC protection • Watchdog timer I2C Memory: • ASW load image protection GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 505 All externally memory boot options have the capability to boot from redundant memory in case of bad CRC is detected on first boot image. An error on the second will force the GR716 microcontroller to reboot and retry the first image.
Page 506 0 and In case memory test passes, the memory area is cleared. In case of failure a flag will be raised in the boot report. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 507: Electrical Description
All electrical specifications are defined at package solder point level, unless otherwise stated. All the figures provided in this section have been derived from post-layout simulations or prototype validation of the GR716 microcontroller. The GR716 microcontroller has not yet been fully character- ized in production test.
Page 508: Absolute Maximum Ratings
5.11kΩ ±3.5% (EOL). The tolerance of the reference resistor will directly affect the accuracy of the DAC output. For application with requirement for high precision DAC outputs selection of reference resistors with better tolerance should be considered. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 509 Note 5: Decoupled to ground via 4.7nF capacitor Note 6: 5.11kΩ ±1% tolerance, 10ppm/°C Note 7: Analog supply voltage for PLL is generated from internal voltage regulator. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 510: Recommended Operating Conditions
There is no direct ESD protection between V and V so they can be powered up independently. DDIO, However, it is recommended to power up V before V in order to minimize toggling, and hence DDIO reduce the rush-in currents. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 511: Input Voltages, Leakage Currents And Capacitances
Recommended operating conditions, see chapter 52.2 Note 2: Digtial GPIO[x] input signals Note 3: TESTEN, DSU_ENA and DSU_BREAK input signals only. Note 4: CLK, SPWCLK, DUART_RX, SPIM_SEL, SPIM_SCK and SPIM_MOSI input signals only. Note 5: RESET_IN_N input signals only. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 512: Output Voltages, Leakage Currents And Capacitances
Output Leakage Current Outputs at OLEAK tri-state. DDIO and V LVTTL Output capaci- O_LVTTL tance Note 1: Recommended operating conditions, see chapter 52.2 Note 2: All outputs defined with 2mA drive capability in Table 715 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 513 , otherwise the output current limits for I are not valid due to the on-chip ESD protection diodes will DDIO conduct current. This is planned to be updated in the next revision of the silicon. See section 56. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 514: Simplified Io Buffer Schematics
Simplified input and output buffer schematics presented in this chapter is applicable within absolute maximum rating conditions, see chapter 52.1 52.6.1 Simplified Bidir buffer with analog capability schematic Figure 92. Simplified bidir buffer with analog capability schematic GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 515 GR716 52.6.2 Simplified LVDS input buffer schematic Figure 93. Simplified LVDS input buffer schematic 52.6.3 Simplified LVDS output buffer schematic Ω Figure 94. Simplified LVDS output buffer schematic GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 516: Dac Electrical Characteristics
DAC Electrical Characteristics All the figures provided in this section have been derived from post-layout simulations or prototype validation of the GR716 microcontroller. The GR716 microcontroller has not yet been fully character- ized in production test. Table 687. Electrical characteristics for internal DAC outputs...
Page 517 ADC Electrical Characteristics All the figures provided in this section have been derived from post-layout simulations or prototype validation of the GR716 microcontroller. The GR716 microcontroller has not yet been fully character- ized in production test. Table 688. Electrical characteristics for internal ADC inputs...
Page 518 Gain x2 Gain x4 Input resistance, com- Gain x1 kΩ IN,CM mon mode Gain x2 Gain x4 Input current Per input pin. VIN: VSSA to VDDA Input capacitance Per input pin to ground GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 519 The values are derived from block-level simulations and have not yet been verified with bench measure- ments. Note 3: CM impedance is defined as small-signal current per input pin, when applying only CM small-signal volt- age. The internal CM termination DC voltage is about 1.6V. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 520: Reference Voltages And Currents Electrical Characteristics
Current consumption No shutdown mode available. VDD_CORE Supply voltage -0.1 CORE Note 1: Unless otherwise noted: VDD -GND =-0.1 - 2.0V, typical values are at 25C, min/max values are CORE CORE at full temperature range. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 521 No shutdown mode available. VDDA_BO Note 1: Unless otherwise noted: VDD -GND =-0.1 - 2.0V, VDDA -VSSA =-0.1 - 3.6V, typical val- CORE CORE ues are at 25C, min/max values are at full temperature range. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 522: 52.11 Ac Characteristics
When SpaceWire clock is used as source to the PLL the internal SpaceWire clock shall not exceed 100MHz Note 5: The current revision of the silicon does not support 20 ns period time, see errata in section 55. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 523 Table 695. External 1553B clock timing parameters Name Parameter Reference edge Unit Clock period 1553CLK0 Clock high/low pulse length 1553CLK1 Note 1: External MIL-1553B clock is only available via IO mux, see chapter 2.5 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 524 Table 698. External PacketWire clock timing parameters Name Parameter Reference edge Unit Clock period SPI4SCLK0 Clock high/low pulse length SPI4SCLK1 Clock cycle jitter -100 SPI4SCLK2 Note 1: External SPI4S clock is only available via IO mux, see chapter 2.5 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 525 Input to clock hold Rising CLK edge SPIM1 Input to clock setup Rising CLK edge SPIM2 Note: The SPI_MISO input is re-synchronized internally, and does not have to meet any setup or hold requirements. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 526 Table 702.SPI interface timing parameters Name Parameter Reference edge Unit Clock to output delay Rising SPI4S_CLK edge SPI4S0 Input to clock hold Rising SPI4S_CLK edge SPI4S1 Input to clock setup Rising SPI4S_CLK edge SPI4S2 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 527 Table 703.SPI interface timing parameters Name Parameter Reference edge Unit Clock to output delay Rising SPI4S_CLK edge SPI4S0_LVDS Input to clock hold Rising SPI4S_CLK edge SPI4S1_LVDS Input to clock setup Rising SPI4S_CLK edge SPI4S2_LVDS GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 528 Unit Output data bit period SPW1 Data & strobe output skew & jitter SPW2 Input data bit period SPW3 Data & strobe input skew, jitter & hold SPW4 Data & strobe edge separation SPW5 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 529 Unit Output data bit period SPW1_LVDS Data & strobe output skew & jitter SPW2_LVDS Input data bit period SPW3_LVDS Data & strobe input skew, jitter & hold SPW4_LVDS Data & strobe edge separation SPW5_LVDS GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 530 Parameter not measured during production test. Note 2: The 1553RXA, 1553RXAN, 1553RXB and 1553RXBN inputs are re-synchronized internally. Note 3: The core frequency must be lower than the internal system frequency: t < F 1553BRM3 GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 531 PWRXCLK edge GRPWRX1 data/active/abort input to clock setup rising PWRXCLK edge GRPWRX2 clock to output delay rising PWRXCLK edge GRPWRX3 Note 1: Verified by static timing analysis, not tested GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 532 Reference edge Unit bit period rising SYS_CLK GRPWTX0 edge data/active/abort input to clock hold rising SYS_CLK GRPWTX1 edge data/active/abort input to clock setup rising SYS_CLK GRPWTX2 edge clock to output delay rising SYS_CLK GRPWTX3 edge GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 533 FTMCTRL10 Timing values are relative to the internal clock for the PROM/SRAM memory controller. 2) Guaranteed by design, not tested 3) Verified by static timing analysis, not tested GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 534 APBUART2 Guaranteed by design, not tested. Verified by static timing analysis, not tested The _cstn and _rxd inputs are re-synchronized internally. These signals to not have to meet any setup or hold require- ments. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 535 GPIO3 Input to clock setup Rising CLK edge GPIO4 Note 1: The GPIO[...] inputs are re-synchronized to the internal system clock Note 2: Parameter is determined by static timing analysis and is not tested GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 536: Component And Package
GR716 Mechanical description 53.1 Component and package 132-lead CQFP The GR716 microcontroller is provided in a package. 53.2 Pin assignment The pin assignment in table 715 shows the implementation characteristics of each signal indicating how each pin has been configured in terms of electrical levels, drive capability and internal pull-up or pull-down.
Page 537 LVTTL GPIO[8] inout LVTTL GPIO[9] inout LVTTL GPIO[10] inout LVTTL GPIO[11] inout LVTTL GPIO[12] inout LVTTL GPIO[13] inout LVTTL GPIO[14] inout LVTTL GPIO[15] inout LVTTL GPIO[16] inout LVTTL GPIO[17] inout LVTTL GPIO[18] inout LVTTL GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 538: Pin Assignment
62, 75, 88, 102, 116, VDDA_ADC 10) 12) Analog ADC supply VSSA_ADC 10) 12) Analog ADC ground VDDA_REF 10) 12) Analog reference supply VSSA_REF 10) 12) Analog reference ground. VDDA_DAC 10) 12) Analog DAC supply GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 539 It is recommended to use separate power supplies for analog supply or to insert local LP filters, such that supply noise becomes lower than TBD V_rms between analog supply and ground. Note 13: VDD_CORE shall not be supplied when LDO_IN is supplied. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 540: Mechanical Package Drawings
GR716 53.3 Mechanical package drawings Figure 117. 132 CQFP package top view GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 541 (L2+L3) Length of lead with width b1 Length of lead with width b2 Note 1: The lid is connected to ground Note 2: Mass of case, including the lead frames, shall be 7±1 grams. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 542: Ordering Information
GR716 Ordering information Please contact Cobham Gaisler AB through sales@gaisler.com. Ordering information is provided in table 717 and a legend is provided in table 718. Table 717.Ordering information, available models Product Description Prototype 2)3) GR716-XX-CQ132-AAAA GR716-XX-CQ132-AAAB Prototype Note 1: Contact Cobham Gaisler AB through sales@gaisler.com for availability.
Page 543: Errata
Workaround: To get to a known state after power-on toggle the power down signals to each of the brown out blocks. First set the signals to logic high, followed by logic low. After this sequence the brown out is in a known state and will work as intended. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 544 The gain of the ADC pre-amplifiers are too low. Gain values are 0.95-1.0 (gain x1), 1.85-2.0 (gain x2) and 3.5-4.0 (gain x4). The gain can be different for the 8 input channels for both amplifiers. Contact support for more information. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 545 GR716 Workaround: n/a. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 546: Features
56.2.4 SPI memory controller with support for 4 byte address ID: GR716-FEATURE-20190409 Contact support@gaisler.com for more information. 56.2.5 SpaceWire TDP synchronization to PPS 1Hz input ID: GR716-FEATURE-20190410 Contact support@gaisler.com for more information. 56.2.6 SpaceWire router capability ID: GR716-FEATURE-20190411 Contact support@gaisler.com for more information. GR716-DS-UM, May 2019, Version 1.29 www.cobham.com/gaisler...
Page 547 Cobham convey a license under any patent rights, copyrights, trademark rights, or any other of the intellec- tual rights of Cobham or of third parties. All information is provided as is. There is no warranty that it is cor- rect or suitable for any purpose, neither implicit nor explicit.