Related Manuals for GENNUM GS1572
Summary of Contents for GENNUM GS1572
- Page 1 GS1572 A Guide to Designing with the GS1572 (EB1572) Reference Design www.gennum.com GS1572 A Guide to Designing with the GS1572 1 of 18 (EB1572) Reference Design Proprietary & Confidential 46282 - 1 November 2009...
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Page 2: Table Of Contents
4. Board Schematic ............................11 5. Board Layout..............................13 6. Bill of Materials............................15 7. Recommended Components ........................17 8. References..............................18 GS1572 A Guide to Designing with the GS1572 2 of 18 (EB1572) Reference Design Proprietary & Confidential 46282 - 1... -
Page 3: Overview
An example of a board design including the GS1572 is shown below. A 10-bit or 20-bit signal at HD or SD rates must be supplied, along with a parallel clock. The serialized output is driven by an internal cable driver. -
Page 4: Design And Layout Guide
NOTE: Optionally, 3.3V digital can be replaced with 1.8V digital to run with 1.8V 2.1.1 Isolation Methods Because of the noise sensitive nature of the PLL and analog components of the GS1572, an isolation technique should be used to filter power to these sections. -
Page 5: Serial Digital Outputs
Additional points relating to SDO layout and component placement (Figure 2-2): 1. Place the pull-up resistors close to the SDO and SDO pins of the GS1572. 2. Try to avoid running high speed traces through vias. Plane Layer, Negative Image... -
Page 6: Vco Power
Gennum’s external GO1555 VCO is required for operation of the GS1572. VCO_VCC (pin A8) and VCO_GND (pins B8 and B9) are provided by the GS1572’s internal regulator and supply +2.5V to the GO1555. The +2.5V is derived from the +3.3V ANALOG connection to CP_VDD (pin A10) and CP_GND (pin B10) of the GS1572. -
Page 7: Evaluation Board User's Guide
The board contains headers and leads allowing output signals to be easily probed and chip features to be enabled. It also provides a JTAG interface and access to the GS1572’s internal registers via the Gennum Serial Peripheral Interface (GSPI). A push button allows the board to easily be reset. -
Page 8: Outputs
The LOCK LED on the GS1572 indicates the status of the LOCKED pin on the GS1572. The LED will be on whenever the GS1572 PLL is locked to PCLK. -
Page 9: Modes Of Operation
D18 and D19 directly to the DIN18 and DIN19 pins on the GS1572. If the device is in DVB_ASI mode, the two jumpers should be placed vertically to tie KIN on the DIN18 pin of the device and tie INSSYNCIN (DIN19) to GND. -
Page 10: External Control Interface
The GS1572 contains a set of internal status and configuration registers. These registers are available to the host via the GS1572’s GSPI pins. Access to the applicable pins on the GS1572 is provided using the JTAG/HOST interface section of the GS1572 (see Figure 3-5). -
Page 11: Board Schematic
4. Board Schematic Figure 4-1 shows the top level schematic of the GS1572. Figure 4-2 shows the chip level in more detail. DATA_IN[19..0] Install HORIZONTAL for SMPTE Install VERTICAL for DVB/ASI DATA_IN19 DATA_IN[19:0] GND_A DATA_IN18 SDOn DATA_IN17 DATA_IN16 PCLK DATA_IN15... -
Page 13: Board Layout
The following illustrations show the top, ground, power, and bottom layers of the GS1572 evaluation board. Figure 5-1: Layer 1 (Top Layer) Figure 5-2: Layer 2 (Ground Plane, Negative Image) GS1572 A Guide to Designing with the GS1572 13 of 18 (EB1572) Reference Design Proprietary &... - Page 14 Figure 5-3: Layer 3 (Power Plane, Negative Image) Figure 5-4: Layer 4 (Bottom Routing Layer) GS1572 A Guide to Designing with the GS1572 14 of 18 (EB1572) Reference Design Proprietary & Confidential 46282 - 1 November 2009...
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Page 15: Bill Of Materials
HEADER 5X2 LP 5.00/4/90 (Power Connect) J6, J7, J8, J9, J10, J11, J12, J13, J14, J15, J16, JMP_3_OPP L1, L2 GS1572 A Guide to Designing with the GS1572 15 of 18 (EB1572) Reference Design Proprietary & Confidential 46282 - 1... - Page 16 B3S_1002 TP1, TP2, TP3, TP4, TP5 HEADER2MM_1_1X1 TP_0 TP6, TP7 Test Points GO1555 MIC94060 GS1572 IRU1206-33CY/SOT-223 IRU1206-18CY/SOT-223 74LVC04/SO GS1572 A Guide to Designing with the GS1572 16 of 18 (EB1572) Reference Design Proprietary & Confidential 46282 - 1 November 2009...
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Page 17: Recommended Components
Canare End launch BNC connector for meeting return loss at 1.5Gb/s. SD rates are less touchy. Any 75Ω will do. (alternative) www.canare.com GS1572 A Guide to Designing with the GS1572 17 of 18 (EB1572) Reference Design Proprietary & Confidential 46282 - 1... -
Page 18: References
E-mail: gennum-taiwan@gennum.com Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement.
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