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Technical Reference Note Rev.12.5.14 HPR12K-00 Page 1 HPR12K-00 1. General Install Connecting the input power cable, output load cable and communication wire according to the below figure. 2. General Settings Unless otherwise specified, when the PSON# switch is de-asserted (48V o/p is disabled).
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Status Down Down Down Down Down Down Down Down Down Down Down Down Note. The status Down means set to ON position. The status UP means set to OFF position. Figure 1: DIP Switch for ON/OFF Operation Artesyn Embedded Technologies...
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PSON# = Open Logic level low (power supply ON) Logic level high (power supply OFF) 0.4V Source current, Vpson = low 2.4V 3.4V Power up delay: T pson_on_delay 400msec 5msec Refer to IPS of HPS3000-9 PN: 41966008950 Artesyn Embedded Technologies...
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Return sense for Stby gnd 5Vsb 5Vsb External Bus Sys_GND Standby GND Unused 5.4 Signal Output Connector CN3 Table 8 Signal Output Connector Self Connector Mating Connector Tyco 2-5178238-4 Tyco: 2-5175677-4 (Astec P/N: 13870011610) Figure 5: Connector CN3 Artesyn Embedded Technologies...
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Minimize arching damage to the power pins UNIT2_PSKILL Minimize arching damage to the power pins UNIT3_PSKILL Minimize arching damage to the power pins UNIT4_PSKILL Minimize arching damage to the power pins UNIT1_#ALERT Warning signal UNIT2_#ALERT Warning signal UNIT3_#ALERT Warning signal UNIT4_#ALERT Warning signal Artesyn Embedded Technologies...
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Technical Reference Note Technical Reference Note Rev.12.5.14 HPR12K-00 Page 7 5.5 Input Connection Definition For Functional Test (NHR – initial testing), the following connection applies. Table 10 Input Connection Definition Designation Identification Terminal Type VINP Input Voltage Positive Ring Lug, #12 screw...
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