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Holtek HT45F4050 Manual

A/d nfc flash mcu
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A/D NFC Flash MCU
HT45F4050
Revision: V1.00
Date: September 11, 2018

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  • Page 1 A/D NFC Flash MCU HT45F4050 Revision: V1.00 Date: September 11, 2018...

  • Page 2: Table Of Contents

    HT45F4050 A/D NFC Flash MCU Table of Contents Features ......................7 CPU Features ......................... 7 Peripheral Features ......................... 7 General Description ..................8 Block Diagram ....................9 Pin Assignment ....................10 Pin Description ....................10 Absolute Maximum Ratings ................15 D.C.
  • Page 3 HT45F4050 A/D NFC Flash MCU Look-up Table Registers – TBLP, TBHP, TBLH ..............36 Status Register – STATUS ....................36 EEPROM Data Memory .................. 38 EEPROM Data Memory Structure ..................38 EEPROM Registers ......................38 Reading Data from the EEPROM ..................39 Writing Data to the EEPROM ....................
  • Page 4 HT45F4050 A/D NFC Flash MCU TM Interrupts ......................... 78 TM External Pins ........................79 Programming Considerations ....................80 Compact Type TM – CTM ................81 Compact Type TM Operation ....................81 Compact Type TM Register Description................81 Compact Type TM Operating Modes ..................85 Standard Type TM –...
  • Page 5 HT45F4050 A/D NFC Flash MCU Near Field Communication – NFC .............. 167 NFC Power Management ....................167 NFC Memory ........................168 NFC Control Registers ....................... 171 Collisions between the MCU and NFC RF Interface ............178 NFC State Diagram and Logical Status Descriptions ............179 NFC Command Set ......................
  • Page 6 HT45F4050 A/D NFC Flash MCU Instruction Set Summary ................211 Table Conventions ........................211 Extended Instruction Set ..................... 213 Instruction Definition ................... 215 Extended Instruction Definition ................... 224 Package Information ................... 231 48-pin LQFP (7mm × 7mm) Outline Dimensions ..............232 Rev. 1.00...

  • Page 7: Features

    HT45F4050 A/D NFC Flash MCU Features CPU Features • Operating Voltage =4MHz: 1.8V~5.5V ♦ =8MHz: 2.0V~5.5V ♦ =12MHz: 2.7V~5.5V ♦ =16MHz: 3.3V~5.5V ♦ • Up to 0.25μs instruction cycle with 16MHz system clock at V • Power down and wake-up functions to reduce power consumption •...

  • Page 8: General Description

    HT45F4050 A/D NFC Flash MCU • NFC AFE (can only be tuned under V =2.2V~5.5V) Standards: NFC Forum Type 2 and ISO14443 Type A ♦ Demodulation: 100% ASK ♦ RF data rate: 106 kbit/s ♦ LDO supply power (1.8V) for 100% ASK demodulator and NFC clock recovery ♦...

  • Page 9: Block Diagram

    HT45F4050 A/D NFC Flash MCU Block Diagram Pin-Shared With Port B Port A PA0~PA7 Driver Reset Circuit 8K × 16 256 × 8 Port B PB0~PB7 Driver UART Interrupt EEPROM Stack Port C INT0~INT1 PC0~PC7 Driver Controller 64 × 8...

  • Page 10: Pin Assignment

    HT45F4050 A/D NFC Flash MCU Pin Assignment PB4/CTCK/CTPB PC5/AN5 PB5/RES PC4/AN4 VSSN PC3/PTCK/PTPB/AN3 PC2/PTPI/PTP/AN2 PC1/AN1/CX/VREF HT45F4050/HT45V4050 PC0/AN0/VREFI 48 LQFP-A AVSS PB6/OSC1 PF5/XT1 PB7/OSC2 PF4/XT2 AVDD PA0/ICPDA/OCDSDA PA2/ICPCK/OCDSCK PF3/SCK/SCL/SCOM3 PE0/STCK/STPB PF2/SDI/SDA/SCOM2 13 14 15 16 17 18 19 20 21 22 23 24 Notes: 1.
  • Page 11 HT45F4050 A/D NFC Flash MCU Pin Name Function Description PAPU General purpose I/O. Register enabled pull-high and PAWU CMOS wake-up. PA2/ICPCK/ PAS0 OCDSCK ICPCK — — ICP Clock pin OCDSCK — — OCDS Clock pin, for EV chip only PAPU General purpose I/O.
  • Page 12 HT45F4050 A/D NFC Flash MCU Pin Name Function Description PBPU CMOS General purpose I/O. Register enabled pull-high. PBS0 PB2/PTCK/PTPB PBS0 PTCK — PTM clock input IFS0 PTPB PBS0 — CMOS PTM inverted output PBPU CMOS General purpose I/O. Register enabled pull-high.
  • Page 13 HT45F4050 A/D NFC Flash MCU Pin Name Function Description PCPU CMOS General purpose I/O. Register enabled pull-high. PCS1 PCS1 PC6/STPI/STP/ STPI — STM capture input IFS0 PCS1 — CMOS STM output PCS1 — A/D Converter analog input PCPU CMOS General purpose I/O. Register enabled pull-high.
  • Page 14 HT45F4050 A/D NFC Flash MCU Pin Name Function Description PFPU CMOS General purpose I/O. Register enabled pull-high. PFS0 PF1/SDO/ SCOM1 PFS0 — CMOS SPI data output SCOM1 PFS0 — SCOM Software controlled LCD COM output PFPU CMOS General purpose I/O. Register enabled pull-high.

  • Page 15: Absolute Maximum Ratings

    HT45F4050 A/D NFC Flash MCU Absolute Maximum Ratings Supply Voltage ....................V −0.3V to V +6.0V Input Voltage ....................V −0.3V to V +0.3V Storage Temperature ....................-50˚C to 125˚C Operating Temperature ....................-40˚C to 85˚C Total ............................-80mA Total ............................. 80mA Total Power Dissipation ......................500mW Note: These are stress ratings only.
  • Page 16 HT45F4050 A/D NFC Flash MCU Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions — No load, all peripherals off, =4MHz — HIRC No load, all peripherals off, — =4MHz, HIRC — NFC communication is in progress — No load, all peripherals off, =8MHz —...
  • Page 17 HT45F4050 A/D NFC Flash MCU Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions — Input Low Voltage for I/O — Ports — — 0.2V PMPS[1:0]=10B or 11B, V — Input Low Voltage for PA1, DDIO PA3~PA7 Pins — PMPS[1:0]=10B or 11B —...

  • Page 18: A.c. Characteristics

    HT45F4050 A/D NFC Flash MCU Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions NFC Function 2.2V LDO Output Voltage =700μA, Ta=-40°C~85°C 1.71 1.80 1.89 LOAD 2.2V LDO Output Current ΔV =-3%, Ta=-40°C~85°C ─ ─ μA 2.2V LDO Quiescent Current No load, Ta=-40°C~85°C...
  • Page 19 HT45F4050 A/D NFC Flash MCU Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions 3.0V Ta=25°C 3.0V~5.5V Ta=25°C 3.0V Ta=0°C~70°C High Speed Internal RC Oscillator 3.0V Ta=-40°C~85°C (HIRC=8MHz, 3.0V~5.5V Ta=0°C~70°C trim 8MHz @ V =3V) 3.0V~5.5V Ta=-40°C~85°C -10% +10% 3.0V Ta=25°C...

  • Page 20: Memory Characteristics

    HT45F4050 A/D NFC Flash MCU Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions — — 1024 — System Start-up Timer Period — /64, f — — (Wake-up from Power Down — /64, f — — Mode and f Off)

  • Page 21: A/D Converter Electrical Characteristics

    HT45F4050 A/D NFC Flash MCU A/D Converter Electrical Characteristics , Ta=-40°C~85°C, unless otherwise specified Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Operating Voltage — — — Input Voltage — — — Reference Voltage — — — SAINS[3:0]=0000B, SAVRS[1:0]=01B, 1.8V...

  • Page 22: Internal Reference Voltage Electrical Characteristics

    HT45F4050 A/D NFC Flash MCU Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions 2.2V +0.1 — -0.1 PGA Maximum Output — +0.1 — -0.1 Voltage Range +0.1 — -0.1 2.2V~ Ta=-40°C~85°C, 5.5V (PGAIS=1) BGREF 3.2V~ Ta=-40°C~85°C, Fix Voltage Output of PGA 5.5V...

  • Page 23: Lvd & Lvr Electrical Characteristics

    HT45F4050 A/D NFC Flash MCU LVD & LVR Electrical Characteristics Ta=-40°C~85°C, unless otherwise specified Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions — LVR enable, voltage select 1.65V — LVR enable, voltage select 1.9V Low Voltage Reset Voltage —...

  • Page 24: Comparator Electrical Characteristics

    HT45F4050 A/D NFC Flash MCU Comparator Electrical Characteristics Ta=-40°C~85°C, unless otherwise specified Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Operating Voltage — — — 1.8V — CNVT[1:0]=00B — — 1.8V — CNVT[1:0]=01B — — Additional Current for Comparator μA...

  • Page 25: Software Controlled Lcd Driver Electrical Characteristics

    Time System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of the device take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance.

  • Page 26: Clocking And Pipelining

    HT45F4050 A/D NFC Flash MCU Clocking and Pipelining The main system clock, derived from either a HXT, LXT, HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions.

  • Page 27: Stack

    HT45F4050 A/D NFC Flash MCU Program Counter High Byte Low Byte (PCL) PC12~PC8 PCL7~PCL0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly.

  • Page 28: Flash Program Memory

    HT45F4050 A/D NFC Flash MCU • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA, LAND, LANDM, LOR, LORM, LXOR, LXORM, LCPL, LCPLA • Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC, LRR, LRRA, LRRCA, LRRC, LRLA, LRL, LRLCA, LRLC •...

  • Page 29: Look-Up Table

    HT45F4050 A/D NFC Flash MCU Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP.

  • Page 30: In Circuit Programming - Icp

    The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in- circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage.

  • Page 31: On-Chip Debug Support - Ocds

    * must be less than 1nF. On-Chip Debug Support – OCDS There is an EV chip named HT45V4050, which is used to emulate HT45F4050 device. The EV chip device also provides an "On-Chip Debug" function to debug the real MCU device during the development process.

  • Page 32: Structure

    HT45F4050 A/D NFC Flash MCU Structure The Data Memory is subdivided into several sectors, all of which are implemented in 8-bit wide Memory. Each of the Data Memory Sectors is categorized into two types, the special Purpose Data Memory and the General Purpose Data Memory.

  • Page 33: Special Purpose Data Memory

    HT45F4050 A/D NFC Flash MCU Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section.

  • Page 34: Special Function Register Description

    HT45F4050 A/D NFC Flash MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers.
  • Page 35 HT45F4050 A/D NFC Flash MCU Example 2 data .section ‘data’ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ‘code’ org 00h start: mov a,04h ; setup size of block...

  • Page 36: Accumulator - Acc

    HT45F4050 A/D NFC Flash MCU Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory...
  • Page 37 HT45F4050 A/D NFC Flash MCU • PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction. • TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out.

  • Page 38: Eeprom Data Memory

    HT45F4050 A/D NFC Flash MCU EEPROM Data Memory The device contains an area of internal EEPROM Data Memory. EEPROM is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer.

  • Page 39: Reading Data From The Eeprom

    HT45F4050 A/D NFC Flash MCU • EED Register Name Bit 7 ~ 0 D7~D0: Data EEPROM data bit 7 ~ bit 0 • EEC Register Name — — — — WREN RDEN — — — — — — — —...

  • Page 40: Writing Data To The Eeprom

    HT45F4050 A/D NFC Flash MCU Writing Data to the EEPROM To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. Then the write enable bit, WREN, in the EEC register must first be set high to enable the write function.

  • Page 41: Programming Considerations

    HT45F4050 A/D NFC Flash MCU Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Memory Pointer high byte register could be normally cleared to zero as this would inhibit access to Sector 1 where the EEPROM control register exist.

  • Page 42: Oscillators

    HT45F4050 A/D NFC Flash MCU Oscillators Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and relevant control registers.

  • Page 43: External Crystal/Ceramic Oscillator - Hxt

    HT45F4050 A/D NFC Flash MCU High Speed Oscillators HIRC HIRCEN IDLE0 Prescaler HXTEN SLEEP CKS2~ CKS0 LXTEN IDLE2 LIRC SLEEP LIRC Low Speed Oscillators LIRC System Clock Configurations External Crystal/Ceramic Oscillator – HXT The External Crystal/Ceramic System Oscillator is one of the high frequency oscillator choices, which is selected via a software control bit, FHS.

  • Page 44: Internal Rc Oscillator - Hirc

    HT45F4050 A/D NFC Flash MCU Crystal Oscillator C1 and C2 Values Crystal Frequency 16MHz 12MHz 8MHz 4MHz 1MHz 100pF 100pF Note: C1 and C2 values are for guidance only. Crystal Recommended Capacitor Values Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components.

  • Page 45: Internal 32Khz Oscillator - Lirc

    As Holtek has provided the device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio.

  • Page 46: System Operation Modes

    HT45F4050 A/D NFC Flash MCU High Speed Oscillators HIRC HIRCEN IDLE0 Prescaler HXTEN SLEEP CKS2~ CKS0 LXTEN IDLE2 LIRC SLEEP LIRC PSC0 Prescaler 0 Time Base 0 Low Speed Oscillators TB0 [2:0] CLKSEL0[1:0] PSC1 Time Base 1 Prescaler 1 TB1 [2:0]...

  • Page 47: Control Register

    HT45F4050 A/D NFC Flash MCU NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators.
  • Page 48 HT45F4050 A/D NFC Flash MCU • SCC Register Name CKS2 CKS1 CKS0 — FHIDEN FSIDEN — — Bit 7~5 CKS2~CKS0: System clock selection 000: f 001: f 010: f 011: f 100: f 101: f 110: f 111: f These three bits are used to select which clock is used as the system clock source. In...
  • Page 49 HT45F4050 A/D NFC Flash MCU HIRCF: HIRC oscillator stable flag Bit 1 0: HIRC unstable 1: HIRC stable This bit is used to indicate whether the HIRC oscillator is stable or not. When the HIRCEN bit is set to 1 to enable the HIRC oscillator or the HIRC frequency selection is changed by application program, the HIRCF bit will first be cleared to 0 and then set to 1 after the HIRC oscillator is stable.

  • Page 50: Operating Mode Switching

    HT45F4050 A/D NFC Flash MCU Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications.
  • Page 51 HT45F4050 A/D NFC Flash MCU NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the CKS2~CKS0 bits to "111"...
  • Page 52 HT45F4050 A/D NFC Flash MCU SLOW Mode to NORMAL Mode Switching In SLOW mode the system clock is derived from f . When system clock is switched back to the NORMAL mode from f , the CKS2~CKS0 bits should be set to "000" ~"110" and then the system clock will respectively be switched to f /64.
  • Page 53 HT45F4050 A/D NFC Flash MCU Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the FHIDEN bit in the SCC register equal to "0" and the FSIDEN bit in the SCC register equal to "1".

  • Page 54: Standby Current Considerations

    HT45F4050 A/D NFC Flash MCU Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised.

  • Page 55: Watchdog Timer

    HT45F4050 A/D NFC Flash MCU Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is sourced from the LIRC oscillator. The LIRC internal oscillator has an approximate frequency of 32kHz and this specified internal clock period can vary with V temperature and process variations.

  • Page 56: Watchdog Timer Operation

    HT45F4050 A/D NFC Flash MCU LRF: LVR control register software reset flag Bit 1 Refer to the Low Voltage Reset section. Bit 0 WRF: WDT control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the WDT control register software reset and cleared by the application program.

  • Page 57: Reset And Initialisation

    HT45F4050 A/D NFC Flash MCU Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to execute the first program instruction.
  • Page 58 HT45F4050 A/D NFC Flash MCU For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference.
  • Page 59 HT45F4050 A/D NFC Flash MCU • RSTC Register Name RSTC7 RSTC6 RSTC5 RSTC4 RSTC3 RSTC2 RSTC1 RSTC0 Bit 7~0 RSTC7~RSTC0: Reset function control 01010101: PB5 10101010: RES pin Other values: Reset MCU If these bits are changed due to adverse environmental conditions, the microcontroller will be reset.
  • Page 60 HT45F4050 A/D NFC Flash MCU RSTD Internal Reset Low Voltage Reset Timing Chart • LVRC Register Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 LVS7~LVS0: LVR voltage select Bit 7~0 01100110: 1.65V 01010101: 1.90V 00110011: 2.55V 10011001: 3.15V 10101010: 3.80V 11110000: LVR disable Any other value: Generates a MCU reset –...

  • Page 61: Reset Initial Conditions

    HT45F4050 A/D NFC Flash MCU Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as the RES reset except that the Watchdog time-out flag TO will be set to "1". WDT Time-out RSTD...
  • Page 62 HT45F4050 A/D NFC Flash MCU RES Reset LVR Reset WDT Time-out WDT Time-out Register Power On Reset (Normal (Normal (Normal (IDLE/SLEEP) Operation) Operation) Operation) IAR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...
  • Page 63 HT45F4050 A/D NFC Flash MCU RES Reset LVR Reset WDT Time-out WDT Time-out Register Power On Reset (Normal (Normal (Normal (IDLE/SLEEP) Operation) Operation) Operation) HXTC - - - - - 0 0 0 - - - - - 0 0 0...
  • Page 64 HT45F4050 A/D NFC Flash MCU RES Reset LVR Reset WDT Time-out WDT Time-out Register Power On Reset (Normal (Normal (Normal (IDLE/SLEEP) Operation) Operation) Operation) SADC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

  • Page 65: Input/Output Ports

    A/D NFC Flash MCU Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities.

  • Page 66: Pull-High Resistors

    HT45F4050 A/D NFC Flash MCU Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using the relevant pull-high control registers PAPU~PFPU and LVPUC and are implemented using weak PMOS transistors.

  • Page 67: I/O Port Control Registers

    HT45F4050 A/D NFC Flash MCU • PAWU Register Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 Bit 7~0 PAWU7~PAWU0: PA7~PA0 wake-up function control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC~PFC, to control the input/output configuration.
  • Page 68 HT45F4050 A/D NFC Flash MCU • SLEDC0 Register Name SLEDC07 SLEDC06 SLEDC05 SLEDC04 SLEDC03 SLEDC02 SLEDC01 SLEDC00 Bit 7~6 SLEDC07~SLEDC06: PB7~PB4 source current selection 00: Source current=Level 0 (min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (max.)

  • Page 69: I/O Port Power Source Control

    HT45F4050 A/D NFC Flash MCU • SLEDC2 Register Name SLEDC27 SLEDC26 SLEDC25 SLEDC24 SLEDC23 SLEDC22 SLEDC21 SLEDC20 Bit 7~6 SLEDC27~SLEDC26: PF7~PF4 source current selection 00: Source current=Level 0 (min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (max.)

  • Page 70: Pin-Shared Functions

    HT45F4050 A/D NFC Flash MCU Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome.
  • Page 71 HT45F4050 A/D NFC Flash MCU • PAS0 Register Name PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 Bit 7~6 PAS07~PAS06: PA3 pin-shared function selection 00: PA3/INT1 01: PA3/INT1 10: PA3/INT1 11: SDO Bit 5~4 PAS05~PAS04: PA2 pin-shared function selection 00: PA2...
  • Page 72 HT45F4050 A/D NFC Flash MCU • PBS0 Register Name PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 Bit 7~6 PBS07~PBS06: PB3 pin-shared function selection 00: PB3 01: PB3 10: PB3 11: CTP Bit 5~4 PBS05~PBS04: PB2 pin-shared function selection 00: PB2/PTCK...
  • Page 73 HT45F4050 A/D NFC Flash MCU • PCS0 Register Name PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 Bit 7~6 PCS07~PCS06: PC3 pin-shared function selection 00: PC3/PTCK 01: PC3/PTCK 10: PTPB 11: AN3 Bit 5~4 PCS05~PCS04: PC2 pin-shared function selection 00: PC2/PTPI...
  • Page 74 HT45F4050 A/D NFC Flash MCU • PDS0 Register Name PDS07 PDS06 PDS05 PDS04 PDS03 PDS02 PDS01 PDS00 Bit 7~6 PDS07~PDS06: PD3 pin-shared function selection 00: PD3 01: PD3 10: PD3 11: AN11 Bit 5~4 PDS05~PDS04: PD2 pin-shared function selection 00: PD2...
  • Page 75 HT45F4050 A/D NFC Flash MCU • PES1 Register Name — — — — — — PES11 PES10 — — — — — — — — — — — — Bit 7~2 Unimplemented, read as "0" Bit 1~0 PES11~PES10: PE4 pin-shared function selection...
  • Page 76 HT45F4050 A/D NFC Flash MCU PFS13~PFS12: PF5 pin-shared function selection Bit 3~2 00: PF5 01: PF5 10: PF5 11: XT1 Bit 1~0 PFS11~PFS10: PF4 pin-shared function selection 00: PF4 01: PF4 10: PF4 11: XT2 • IFS0 Register Name SCSBPS SDISDAPS SCKSCLPS STPIPS...

  • Page 77: I/O Pin Structures

    HT45F4050 A/D NFC Flash MCU I/O Pin Structures The accompanying diagram illustrates the internal structure of the I/O logic function. As the exact logical construction of the I/O pin will differ from this diagram, it is supplied as a guide only to assist with the functional understanding of the logc function I/O pins.

  • Page 78: Timer Modules - Tm

    HT45F4050 A/D NFC Flash MCU Timer Modules – TM One of the most fundamental functions in any microcontroller devices is the ability to control and measure time. To implement time related functions the device includes several Timer Modules, generally abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals.

  • Page 79: Tm External Pins

    HT45F4050 A/D NFC Flash MCU TM External Pins Each of the TMs, irrespective of what type, has one or two TM input pins, with the label xTCK and xTPI respectively. The xTM input pin, xTCK, is essentially a clock source for the xTM and is selected using the xTCK2~xTCK0 bits in the xTMC0 register.

  • Page 80: Programming Considerations

    HT45F4050 A/D NFC Flash MCU PTCK CCR capture input PTPI CCR output PTPB PTM Function Pin Block Diagram Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way.

  • Page 81: Compact Type Tm - Ctm

    HT45F4050 A/D NFC Flash MCU Compact Type TM – CTM Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive two external output pins.
  • Page 82 HT45F4050 A/D NFC Flash MCU • CTMC0 Register Name CTPAU CTCK2 CTCK1 CTCK0 CTON — — — — — — — — — Bit 7 CTPAU: CTM Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation.
  • Page 83 HT45F4050 A/D NFC Flash MCU CTIO1~CTIO0: Select CTM function Bit 5~4 Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode 00: PWM output inactive state 01: PWM output active state...
  • Page 84 HT45F4050 A/D NFC Flash MCU CTCCLR: CTM Counter Clear condition selection Bit 0 0: CTM Comparator P match 1: CTM Comparator A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter.

  • Page 85: Compact Type Tm Operating Modes

    HT45F4050 A/D NFC Flash MCU • CTMRP Register Name CTRP7 CTRP6 CTRP5 CTRP4 CTRP3 CTRP2 CTRP1 CTRP0 Bit 7~0 CTRP7~CTRP0: CTM CCRP 8-bit register, compared with the CTM Counter bit 15 ~ bit 8 Comparator P Match Period= 0: 65536 CTM clocks 1~255: 256 ×...
  • Page 86 HT45F4050 A/D NFC Flash MCU Counter overflow Counter Value CTCCLR = 0; CTM [1:0] = 00 CCRP > 0 CCRP=0 Counter cleared by CCRP value 0xFFFF CCRP > 0 Counter Resume Restart CCRP Pause Stop CCRA Time CTON CTPAU CTPOL CCRP Int.
  • Page 87 HT45F4050 A/D NFC Flash MCU Counter Value CTCCLR = 1; CTM [1:0] = 00 CCRA = 0 CCRA > 0 Counter cleared by CCRA value Counter overflow 0xFFFF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time CTON CTPAU CTPOL...
  • Page 88 HT45F4050 A/D NFC Flash MCU Timer/Counter Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the CTM output pin is not used.
  • Page 89 HT45F4050 A/D NFC Flash MCU Counter Value CTDPX = 0; CTM [1:0] = 10 Counter cleared by CCRP Counter Reset when CTON returns high CCRP Counter Stop if Pause Resume CTON bit low CCRA Time CTON CTPAU CTPOL CCRA Int.
  • Page 90 HT45F4050 A/D NFC Flash MCU Counter Value CTDPX = 1; CTM [1:0] = 10 Counter cleared by CCRA Counter Reset when CTON returns high CCRA Counter Stop if Pause Resume CTON bit low CCRP Time CTON CTPAU CTPOL CCRP Int.

  • Page 91: Standard Type Tm - Stm

    HT45F4050 A/D NFC Flash MCU Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with two external input pins and can drive two external output pins.
  • Page 92 HT45F4050 A/D NFC Flash MCU • STMC0 Register Name STPAU STCK2 STCK1 STCK0 STON — — — — — — — — — Bit 7 STPAU: STM Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation.
  • Page 93 HT45F4050 A/D NFC Flash MCU STIO1~STIO0: Select STM external pin function Bit 5~4 Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state...
  • Page 94 HT45F4050 A/D NFC Flash MCU STDPX: STM PWM duty/period control Bit 1 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform.

  • Page 95: Standard Type Tm Operation Modes

    HT45F4050 A/D NFC Flash MCU • STMRP Register Name STRP7 STRP6 STRP5 STRP4 STRP3 STRP2 STRP1 STRP0 Bit 7~0 STRP7~STRP0: STM CCRP 8-bit register, compared with the STM counter bit 15~bit 8 Comparator P match period= 0: 65536 STM clocks 1~255: (1~255) ×...
  • Page 96 HT45F4050 A/D NFC Flash MCU Counter overflow STCCLR = 0; STM [1:0] = 00 Counter Value CCRP > 0 CCRP=0 Counter cleared by CCRP value 0xFFFF CCRP > 0 Counter Resume Restart CCRP Pause Stop CCRA Time STON STPAU STPOL CCRP Int.
  • Page 97 HT45F4050 A/D NFC Flash MCU Counter Value STCCLR = 1; STM [1:0] = 00 CCRA = 0 CCRA > 0 Counter cleared by CCRA value Counter overflow 0xFFFF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time STON STPAU STPOL...
  • Page 98 HT45F4050 A/D NFC Flash MCU Timer/Counter Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the STM output pin is not used.
  • Page 99 HT45F4050 A/D NFC Flash MCU Counter Value STDPX = 0; STM [1:0] = 10 Counter cleared by CCRP Counter Reset when STON returns high CCRP Counter Stop if Pause Resume STON bit low CCRA Time STON STPAU STPOL CCRA Int.
  • Page 100 HT45F4050 A/D NFC Flash MCU Counter Value STDPX = 1; STM [1:0] = 10 Counter cleared by CCRA Counter Reset when STON returns high CCRA Counter Stop if Pause Resume STON bit low CCRP Time STON STPAU STPOL CCRP Int.
  • Page 101 HT45F4050 A/D NFC Flash MCU Single Pulse Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin.
  • Page 102 HT45F4050 A/D NFC Flash MCU Counter Value STM [1:0] = 10 ; STIO [1:0] = 11 Counter stopped by CCRA Counter Reset when STON returns high CCRA Counter Stops Resume Pause by software CCRP Time STON Auto. set by STCK pin...
  • Page 103 HT45F4050 A/D NFC Flash MCU Capture Input Mode To select this mode bits STM1 and STM0 in the STMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements.
  • Page 104 HT45F4050 A/D NFC Flash MCU Counter Value STM [1:0] = 01 Counter cleared by CCRP Counter Counter Stop Reset CCRP Resume Pause Time STON STPAU Active Active Active edge edge edge STM capture pin STPI CCRA Int. Flag STMAF CCRP Int.

  • Page 105: Periodic Type Tm - Ptm

    HT45F4050 A/D NFC Flash MCU Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can also be controlled with two external input pins and can drive two external output pins.
  • Page 106 HT45F4050 A/D NFC Flash MCU • PTMC0 Register Name PTPAU PTCK2 PTCK1 PTCK0 PTON — — — — — — — — — Bit 7 PTPAU: PTM Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation.
  • Page 107 HT45F4050 A/D NFC Flash MCU PTIO1~PTIO0: Select PTM external pin function Bit 5~4 Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state...
  • Page 108 HT45F4050 A/D NFC Flash MCU PTCAPTS: PTM Capture Triiger Source selection Bit 1 0: From PTPI pin 1: From PTCK pin PTCCLR: PTM Counter Clear condition selection Bit 0 0: Comparator P match 1: Comparator A match This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter.

  • Page 109: Periodic Type Tm Operation Modes

    HT45F4050 A/D NFC Flash MCU • PTMRPL Register Name PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0 Bit 7~0 PTRP7~PTRP0: PTM CCRP Low Byte Register bit 7 ~ bit 0 PTM 10-bit CCRP bit 7 ~ bit 0 • PTMRPH Register Name —...
  • Page 110 HT45F4050 A/D NFC Flash MCU Counter overflow Counter Value PTCCLR = 0; PTM [1:0] = 00 CCRP > 0 CCRP=0 Counter cleared by CCRP value 0x3FF CCRP > 0 Counter Resume Restart CCRP Pause Stop CCRA Time PTON PTPAU PTPOL CCRP Int.
  • Page 111 HT45F4050 A/D NFC Flash MCU Counter Value PTCCLR = 1; PTM [1:0] = 00 CCRA = 0 CCRA > 0 Counter cleared by CCRA value Counter overflow 0x3FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time PTON PTPAU PTPOL...
  • Page 112 HT45F4050 A/D NFC Flash MCU Timer/Counter Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the PTM output pin is not used.
  • Page 113 HT45F4050 A/D NFC Flash MCU Counter Value PTM [1:0] = 10 Counter cleared by CCRP Counter Reset when PTON returns high CCRP Counter Stop if Pause Resume PTON bit low CCRA Time PTON PTPAU PTPOL CCRA Int. Flag PTMAF CCRP Int. Flag...
  • Page 114 HT45F4050 A/D NFC Flash MCU Single Pulse Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTIO1 and PTIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTM output pin.
  • Page 115 HT45F4050 A/D NFC Flash MCU Counter Value PTM [1:0] = 10 ; PTIO [1:0] = 11 Counter stopped by CCRA Counter Reset when PTON returns high CCRA Counter Stops Resume Pause by software CCRP Time PTON Auto. set by Software...
  • Page 116 HT45F4050 A/D NFC Flash MCU Capture Input Mode To select this mode bits PTM1 and PTM0 in the PTMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements.
  • Page 117 HT45F4050 A/D NFC Flash MCU Counter Value PTM [1:0] = 01 Counter cleared by CCRP Counter Counter Stop Reset CCRP Resume Pause Time PTON PTPAU Active Active Active edge edge edge PTM capture pin PTPI or PTCK CCRA Int. Flag PTMAF CCRP Int.

  • Page 118: Analog To Digital Converter - Adc

    HT45F4050 A/D NFC Flash MCU Analog to Digital Converter – ADC The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters.

  • Page 119: A/D Converter Register Description

    HT45F4050 A/D NFC Flash MCU A/D Converter Register Description Overall operation of the A/D converter is controlled using six registers. A read only register pair exists to store the A/D converter data 12-bit value. The remaining three registers are control registers which setup the operating and control function of the A/D converter.
  • Page 120 HT45F4050 A/D NFC Flash MCU The relevant pin-shared function selection bits determine which pins on I/O Ports are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input.
  • Page 121 HT45F4050 A/D NFC Flash MCU • SADC1 Register Name SAINS3 SAINS2 SAINS1 SAINS0 — SACKS2 SACKS1 SACKS0 — — Bit 7~4 SAINS3~SAINS0: A/D converter input signal selection 0000: External signal – External analog channel input, ANn 0001: Internal signal – Internal A/D converter power supply voltage AV 0010: Internal signal –...

  • Page 122: A/D Converter Reference Voltage

    HT45F4050 A/D NFC Flash MCU SAVRS1~SAVRS0: A/D converter reference voltage selection Bit 3~2 00: Internal A/D converter power, AV 01: External VREF pin 1x: Internal PGA output voltage, V These bits are used to select the A/D converter reference voltage. When the internal A/D converter power or the internal PGA output voltage is selected as the reference voltage, the hardware will automatically disconnect the external VREF input.

  • Page 123: A/D Converter Input Signals

    HT45F4050 A/D NFC Flash MCU SAVRS[1:0] Reference Source Description Internal A/D converter power supply voltage VREF pin External A/D converter reference pin VREF Internal A/D converter PGA output voltage A/D Converter Reference Voltage Selection A/D Converter Input Signals All of the external A/D Converter analog input pins are pin-shared with the I/O pins as well as other functions.

  • Page 124: A/D Converter Operation

    HT45F4050 A/D NFC Flash MCU A/D Converter Operation The START bit is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated.

  • Page 125: A/D Conversion Rate And Timing Diagram

    HT45F4050 A/D NFC Flash MCU A/D Conversion Rate and Timing Diagram A complete A/D conversion contains two parts, data sampling and data conversion. The data sampling which is defined as t takes 4 A/D conversion clock cycles and the data conversion takes 12 A/D converter clock cycles.

  • Page 126: Summary Of A/D Conversion Steps

    HT45F4050 A/D NFC Flash MCU Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Select the required A/D conversion clock by properly programming the SACKS2~SACKS0 bits in the SADC1 register.

  • Page 127: Programming Considerations

    HT45F4050 A/D NFC Flash MCU Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D conversion internal circuitry can be switched off to reduce power consumption, by clearing the ADCEN bit in the SADC0 register. When this happens, the internal A/D conversion circuits will not consume power irrespective of what analog voltage is applied to their input lines.

  • Page 128: A/D Converter Programming Examples

    HT45F4050 A/D NFC Flash MCU A/D Converter Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the ADBZ bit in the SADC0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D converter interrupt is used to determine when the conversion is complete.
  • Page 129 HT45F4050 A/D NFC Flash MCU Example: using the interrupt method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H ; select f /8 as A/D clock and A/D input signal comes from external ; channel mov SADC1,a mov a,00H ; select AV...

  • Page 130: Comparator

    HT45F4050 A/D NFC Flash MCU Comparator An analog comparator is contained within the device. The comparator function offers flexibility via their register controlled features such as power-down, polarity select, hysteresis etc. In sharing their pins with normal I/O pins the comparators do not waste precious I/O pins if there functions are otherwise unused.
  • Page 131 HT45F4050 A/D NFC Flash MCU • CMPC Register Name — CMPEN CPOL CMPO CNVT1 CNVT0 — — — — — — — — Bit 7 Unimplemented, read as "0" Bit 6 CMPEN: Comparator function control 0: Disable 1: Enable This bit is used to enable/disable the comparator function. If this bit is cleared to zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs.

  • Page 132: Input Offset Calibration

    HT45F4050 A/D NFC Flash MCU COF4~COF0: Comparator input offset calibration value Bit 4~0 This 5-bit field is used to perform the comparator input offset calibration operation and the value after the input offset calibration can be restored into this bit field. Refer to the "Input Offset Calibration"...

  • Page 133: Serial Interface Module - Sim

    HT45F4050 A/D NFC Flash MCU Serial Interface Module – SIM The device contains a Serial Interface Module, which includes both the four line SPI interface and the two line I C interface types, to allow an easy method of communication with external peripheral hardware.
  • Page 134 HT45F4050 A/D NFC Flash MCU The SPI function in the device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag •...
  • Page 135 HT45F4050 A/D NFC Flash MCU SPI Data Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register.
  • Page 136 HT45F4050 A/D NFC Flash MCU SIMEN: SIM enable control Bit 1 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and...
  • Page 137 HT45F4050 A/D NFC Flash MCU MLS: SPI data shift order Bit 3 0: LSB first 1: MSB first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.
  • Page 138 HT45F4050 A/D NFC Flash MCU SIMEN=1, CSEN=0 (External Pull-high) SIMEN, CSEN=1 SCK (CKPOLB=1, CKEG=0) SCK (CKPOLB=0, CKEG=0) SCK (CKPOLB=1, CKEG=1) SCK (CKPOLB=0, CKEG=1) SDO (CKEG=0) D7/D0 D6/D1 D5/D2 D4/D3 D3/D4 D2/D5 D1/D6 D0/D7 SDO (CKEG=1) D7/D0 D6/D1 D5/D2 D4/D3 D3/D4 D2/D5...
  • Page 139 HT45F4050 A/D NFC Flash MCU SPI Transfer Write Data Clear WCOL Master Slave into SIMD Master or Slave WCOL=1? SIM[2:0]=000, 001, SIM[2:0]=101 010, 011 or 100 Transmission completed? Configure CKPOLB, (TRF=1?) CKEG, CSEN and MLS Read Data SIMEN=1 from SIMD...
  • Page 140 HT45F4050 A/D NFC Flash MCU SPI Bus Enable/Disable To enable the SPI bus, set CSEN=1 and SCS=0, then wait for data to be written into the SIMD (TXRX buffer) register. For the Master Mode, after data has been written to the SIMD (TXRX buffer) register, then transmission or reception will start automatically.
  • Page 141 HT45F4050 A/D NFC Flash MCU • Step 8 Clear TRF. • Step 9 Go to step 4. Slave Mode • Step 1 Select the SPI Slave mode using the SIM2~SIM0 bits in the SIMC0 control register • Step 2 Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Master devices.

  • Page 142: I 2 C Interface

    HT45F4050 A/D NFC Flash MCU C Interface The I C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications.
  • Page 143 HT45F4050 A/D NFC Flash MCU START signal from Master Send slave address and R/W bit from Master Acknowledge from slave Send data byte from Master Acknowledge from slave STOP signal from Master The SIMDEB1 and SIMDEB0 bits determine the debounce time of the I C interface.
  • Page 144 HT45F4050 A/D NFC Flash MCU • SIMD Register Name "x": unknown D7~D0: SIM data register bit 7 ~ bit 0 Bit 7~0 C Address Register The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored.
  • Page 145 HT45F4050 A/D NFC Flash MCU Bit 4 Unimplemented, read as "0" SIMDEB1~SIMDEB0: I Bit 3~2 C debounce time selection 00: No debounce 01: 2 system clock debounce 1x: 4 system clock debounce These bits are used to select the I C debounce time when the SIM is configured as the C interface function by setting the SIM2~SIM0 bits to "110".
  • Page 146 HT45F4050 A/D NFC Flash MCU TXAK: I Bit 3 C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8 bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device.
  • Page 147 HT45F4050 A/D NFC Flash MCU C Bus Communication Communication on the I C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on...
  • Page 148 HT45F4050 A/D NFC Flash MCU C Bus Start Signal The START signal can only be generated by the master device connected to the I C bus and not by the slave device. This START signal will be detected by all devices connected to the I C bus.
  • Page 149 HT45F4050 A/D NFC Flash MCU C Bus Data and Acknowledge Signal The transmitted data is 8-bit wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8 bits of data, the receiver must transmit an acknowledge signal, level "0", before it can...
  • Page 150 HT45F4050 A/D NFC Flash MCU Start SIMTOF=1? SET SIMTOEN HAAS=1? CLR SIMTOF HTX=1? SRW=1? RETI Read from SIMD to CLR HTX release SCL Line SET HTX CLR TXAK RETI Write data to SIMD to Dummy read from SIMD release SCL Line...
  • Page 151 HT45F4050 A/D NFC Flash MCU Start Slave Address C time-out counter start Stop C time-out counter reset on SCL negative transition C Time-out When an I C time-out counter overflow occurs, the counter will stop and the SIMTOEN bit will be cleared to zero and the SIMTOF bit will be set high to indicate that a time-out condition has occurred.

  • Page 152: Uart Interface

    HT45F4050 A/D NFC Flash MCU UART Interface The device contains an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed.

  • Page 153: Uart External Pins

    HT45F4050 A/D NFC Flash MCU UART External Pins To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX and RX pins are the UART transmitter and receiver pins respectively. The TX and RX pin function should first be selected by the corresponding pin-shared function selection register before the UART function is used.
  • Page 154 HT45F4050 A/D NFC Flash MCU • TXR_RXR Register The TXR_RXR register is the data register which is used to store the data to be transmitted on the TX pin or being received from the RX pin. Name TXRX7 TXRX6 TXRX5...
  • Page 155 HT45F4050 A/D NFC Flash MCU RIDLE: Receiver status Bit 3 0: Data reception is in progress (Data being received) 1: No data reception is in progress (Receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is "0", it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit.
  • Page 156 HT45F4050 A/D NFC Flash MCU • UCR1 Register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function, such as overall on/off control, parity control, data transfer bit length etc.
  • Page 157 HT45F4050 A/D NFC Flash MCU TXBRK: Transmit break character Bit 2 0: No break character is transmitted 1: Break characters transmit The TXBRK bit is the Transmit Break Character bit. When this bit is "0", there are no break characters and the TX pin operates normally. When the bit is "1", there are transmit break characters and the transmitter will send logic zeros.
  • Page 158 HT45F4050 A/D NFC Flash MCU BRGH: Baud Rate speed selection Bit 5 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the baud rate register BRG, controls the Baud Rate of the UART.

  • Page 159: Baud Rate Generator

    HT45F4050 A/D NFC Flash MCU • BRG Register Name BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 "x": unknown 0: Baud Rate values Bit 7~0 By programming the BRGH bit in UCR2 Register which allows selection of the related formula described above and programming the required value in the BRG register, the required baud rate can be setup.

  • Page 160: Uart Setup And Control

    HT45F4050 A/D NFC Flash MCU UART Setup and Control For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity is supported by the UART hardware, and can be setup to be even, odd or no parity.

  • Page 161: Uart Transmitter

    HT45F4050 A/D NFC Flash MCU The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. Next Parity Bit Start Start Stop Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6...

  • Page 162: Uart Receiver

    HT45F4050 A/D NFC Flash MCU The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR_RXR register is empty and that other data can now be written into the TXR_RXR register without overwriting the previous data. If the TEIE bit is set then the TXIF flag will generate an interrupt.
  • Page 163 HT45F4050 A/D NFC Flash MCU • Make the correct selection of BNO, PRT and PREN bits to define the word length, parity type. • Setup the BRG register to select the desired baud rate. • Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin.

  • Page 164: Managing Receiver Errors

    HT45F4050 A/D NFC Flash MCU Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – OERR The TXR_RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a third byte can continue to be received.

  • Page 165: Uart Interrupt Structure

    HT45F4050 A/D NFC Flash MCU UART Interrupt Structure Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up.

  • Page 166: Uart Power Down And Wake-Up

    HT45F4050 A/D NFC Flash MCU Address Detect Mode Setting the Address Detect Mode bit, ADDEN, in the UCR2 register, enables this special mode. If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag.

  • Page 167: Near Field Communication - Nfc

    HT45F4050 A/D NFC Flash MCU Near Field Communication – NFC The device contains a highly integrated Near Field Communication function, otherwise known as NFC function, for contactless communication. Originally developed by Philips and Sony based on RFID contractless transponder and interconnection technologies, the NFC technology has gradually evolved into various standards by ECMA, ISO/IEC and ETSI.

  • Page 168: Nfc Memory

    HT45F4050 A/D NFC Flash MCU NFC Memory The total NFC memory is organized into 80 pages with each page containing 4 bytes. The 256 bytes from page 0 to page 63 form the NFC EEPROM area and the 64 bytes from page 64 to page 79 form the NFC SRAM area.
  • Page 169 HT45F4050 A/D NFC Flash MCU Block Check Characteristic Bytes • BCCn Byte (n=0~1) Name Default "x": unknown Bit 7~0 D7~D0: Block Check Character byte n According to ISO/IEC 14443A, BCC0 is defined as CT SN0 SN1 SN2, and BCC1 is defined as SN3 SN4 SN5 SN6, where "CT" stands for Cascade Tag byte (88h), SNn stands for Serial Number n stored in UIDn and "...
  • Page 170 HT45F4050 A/D NFC Flash MCU The static lock and block lock bits in these two lock bytes are set by a WRITE or COMPATIBILITY_ WRITE command to page 02h. Bytes 2 and 3 of the WRITE or COMPATIBILITY_WRITE command and the current contents of the lock bytes are bit-wise OR’ed, after which the results become the new contents of the lock bytes.

  • Page 171: Nfc Control Registers

    HT45F4050 A/D NFC Flash MCU As shown in the CC3 bit description, if CC3=00h, the NFC Forum Type 2 Tag Capability bytes are set and allow read/write access. If CC3=0Fh, the NFC Forum Type 2 Tag Capability bytes are set and only allow read access.
  • Page 172 HT45F4050 A/D NFC Flash MCU Register Name NFC_INTE MRDE MWRE NRDE NWRE RIPE WIPE NFC_INTF MRDF MWRF NRDF NWRF RIPF WIPF NFC_STATUS — — — — NFCBOOT HFPON NFCEEA — NFCEED0 NFCEED1 NFCEED2 NFCEED3 NFCEEC — — NFCWA MFCRA NFCWREN...
  • Page 173 HT45F4050 A/D NFC Flash MCU WIPE: Interrupt control for the MCU read/write the NFC memory when the RF is Bit 2 writing to the NFC memory 0: Disable 1: Enable To enable this interrupt function, both the WIPE bit and the NFC overall interrupt enable bit NFCE should be set high.
  • Page 174 HT45F4050 A/D NFC Flash MCU RIPF: Interrupt request flag for MCU read/write the NFC memory when the RF is Bit 3 reading NFC memory 0: MCU reading/writing NFC memory does not occur when the RF is reading NFC memory 1: MCU reading/writing NFC memory occurs when the RF is reading NFC memory...
  • Page 175 HT45F4050 A/D NFC Flash MCU RIP: RF reading NFC memory status flag Bit 2 0: RF reading NFC memory is not in progress 1: RF reading NFC memory is in progress There will still be the possibility of collision occurrence with the RIP bit low since the NFC memory access by the RF interface is asynchronous with the MCU access operation.
  • Page 176 HT45F4050 A/D NFC Flash MCU • NFCEED1 Register Name Bit 7~0 D17~D10: NFC memory data byte 1 bit 7 ~ bit 0 • NFCEED2 Register Name Bit 7~0 D27~D20: NFC memory data byte 2 bit 7 ~ bit 0 • NFCEED3 Register...
  • Page 177 HT45F4050 A/D NFC Flash MCU NFCWREN: MCU write NFC memory enable Bit 3 0: Disable 1: Enable This is the MCU writing NFC memory enable bit which must be set high before MCU write operations to the NFC memory are carried out. Clearing this bit to zero will inhibit MCU write operations to the NFC memory.

  • Page 178: Collisions Between The Mcu And Nfc Rf Interface

    HT45F4050 A/D NFC Flash MCU • NFCCTRL Register Name — — — — STMODEN FCONF1 FCONF0 NFCEN — — — — — — — — Bit 7~4 Unimplemented, read as "0" Bit 3 STMODEN: Strong modulation mode enable control 0: Disable 1: Enable This bit is used to enhance the field detection ability.

  • Page 179: Nfc State Diagram And Logical Status Descriptions

    Commands shown in the NFC tag state diagram below are initiated by external NFC devices and controlled by the HT45F4050 command interpreter. In this way the NFC module internal state is processed and the appropriate response will be generated accordingly.
  • Page 180 HT45F4050 A/D NFC Flash MCU READY1 State When a REQA or WUPA command is received by the NFC tag device in the IDLE state, the NFC tag device will exit the IDLE state and then enter the READY1 state. However, the NFC tag device can exit the HALT state and enter the READY1 state only if a WUPA command is received.

  • Page 181: Nfc Command Set

    HT45F4050 A/D NFC Flash MCU The response of the selected NFC tag device to the Select CL2 command is the Select Acknowledge (SAK) byte, which in accordance with ISO/IEC 14443 indicates that the anticollision cascade procedure has finished. After this the selected NFC tag device is now uniquely selected and only this device will communicate with the NFC polling device even if other contactless devices are present within the NFC field.
  • Page 182 HT45F4050 A/D NFC Flash MCU REQA – NFC Request Command for Type A Code (CMD.) Parameter (PAR.) Data Integrity Mechanism Response 26h (7-bit) — — Parity 0044h The NFC tag device can only accept the REQA command in the IDLE state. The response is a 2-byte Answer-To-reQuest for type A abbreviated to "ATQA"...
  • Page 183 HT45F4050 A/D NFC Flash MCU UID collided conditions and the Data field will be determined bit-by-bit after the anticollision identification. Eventually the 3-byte UID for the cascade level 1 will be identified. After the 3-byte UID has been successfully identified, the NFC tag device can be selected by the Select CL1 command for the cascade level 1.
  • Page 184 HT45F4050 A/D NFC Flash MCU CMD. PAR. Command Tag Device UID3 UID4 UID5 UID6 BCC1 Response Cascade Level 2 UID 90μs Anticollision CL2 Execution Diagram CMD. PAR. Cascade Level 2 UID Command UID3 UID4 UID5 UID6 BCC1 CRC0 CRC1 Tag Device...
  • Page 185 HT45F4050 A/D NFC Flash MCU HLTA – Halt Command for Type A Code (CMD.) Parameter (PAR.) Data Integrity Mechanism Response — Parity, CRC Passive ACK, NAK The HLTA command is used to set the recognized NFC tag device into the HALT state. It is simple to distinguish between devices whose UIDs have been identified and devices whose UIDs have not been resolved after the recognized NFC tag devices is set into the HALT state.
  • Page 186 HT45F4050 A/D NFC Flash MCU COMPATIBILITY_WRITE – Compatibility Write Command Code (CMD.) Parameter (PAR.) Data Integrity Mechanism Response ADR: ‘02h’ to ‘4Fh’ 16 Bytes Parity, CRC ACK or NAK The COMPATIBILITY_WRITE command is provided to be compliant with different write command versions for different NFC devices.
  • Page 187 HT45F4050 A/D NFC Flash MCU CMD. CRC0 CRC1 Command Tag Device CRC0 CRC1 Response 90μs CRC/Parity error 90μs GET_VERSION Execution Diagram Byte No. Description HT45F4050 Interpretation Fixed header Vendor ID UID0 Vendor Code which is identical to UID0 Product type...
  • Page 188 HT45F4050 A/D NFC Flash MCU CMD. PAR. SADR EADR CRC0 CRC1 Command Tag Device D(4xN-1) CRC0 CRC1 Response 90μs < Response time < *t + 90μs : Collision time, including *t or *t respectively exists if the collision of the NFC memory access by MCU occurs SADR/EADR error 90μs...

  • Page 189: Scom Controlled Lcd Driver

    HT45F4050 A/D NFC Flash MCU SCOM Controlled LCD Driver The device has the capability of driving external LCD panels. The common pins, SCOM0~SCOM3, for LCD driving are pin shared with certain pins on the I/O ports. The LCD signals (COM) are generated using the application program.

  • Page 190: Lcd Bias Current Control

    HT45F4050 A/D NFC Flash MCU LCD Bias Current Control The LCD COM driver enables a range of selections to be provided to suit the requirement of the LCD panel which is being used. The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in the SCOMC register.

  • Page 191: Interrupts

    HT45F4050 A/D NFC Flash MCU Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs.
  • Page 192 HT45F4050 A/D NFC Flash MCU Register Name INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — MF0F INT0F MF0E INT0E INTC1 TB0F MF2F MF1F TB0E MF2E MF1E INTC2 SIMF INT1F TB1F SIME INT1E TB1E INTC3 — — —...
  • Page 193 HT45F4050 A/D NFC Flash MCU CPE: Comparator interrupt control Bit 2 0: Disable 1: Enable INT0E: INT0 interrupt control Bit 1 0: Disable 1: Enable Bit 0 EMI: Global interrupt control 0: Disable 1: Enable • INTC1 Register Name TB0F...
  • Page 194 HT45F4050 A/D NFC Flash MCU INT1F: INT1 pin interrupt request flag Bit 5 0: No request 1: Interrupt request TB1F: Time Base 1 interrupt request flag Bit 4 0: No request 1: Interrupt request Bit 3 URE: UART interrupt control...
  • Page 195 HT45F4050 A/D NFC Flash MCU • MFI1 Register Name CTMAF CTMPF PTMAF PTMPF CTMAE CTMPE PTMAE PTMPE Bit 7 CTMAF: CTM Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 6 CTMPF: CTM Comparator P match interrupt request flag...

  • Page 196: Interrupt Operation

    HT45F4050 A/D NFC Flash MCU Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A match or A/D conversion completion etc., the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit.

  • Page 197: External Interrupts

    HT45F4050 A/D NFC Flash MCU Legend EMI auto disabled Request Flag, no auto reset in ISR in ISR Request Flag, auto reset in ISR Interrupt Request Enable Master Priority Enable Bits Vector Name Flags Bits Enable High INT0 Pin INT0F...

  • Page 198: Comparator Interrupt

    HT45F4050 A/D NFC Flash MCU Comparator Interrupt The comparator interrupt is controlled by the internal comparator. A comparator interrupt request will take place when the comparator interrupt request flag, CPF, is set, a situation that will occur when the comparator output bit changes state. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and comparator interrupt enable bit, CPE, must first be set.
  • Page 199 HT45F4050 A/D NFC Flash MCU The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source, f or f , originates from the internal clock source f /4 or f and then...

  • Page 200: Serial Interface Module Interrupt

    HT45F4050 A/D NFC Flash MCU TB02~TB00: Time Base 0 time-out period selection Bit 2~0 000: 2 PSC0 001: 2 PSC0 010: 2 PSC0 011: 2 PSC0 100: 2 PSC0 101: 2 PSC0 110: 2 PSC0 111: 2 PSC0 • TB1C Register...

  • Page 201: Nfc Interrupt

    HT45F4050 A/D NFC Flash MCU NFC Interrupt The NFC Interrupt is controlled by several NFC communication conditions. These conditions are MCU reading/writing NFC memory completed, RF reading/writing NFC memory completed, MCU reading/writing NFC memory when RF reading/writing NFC memory is in progress, field condition detected, NFC memory accessed by MCU or RF error occurance, which are detailly defined in the NFC_INTF register.

  • Page 202: Interrupt Wake-Up Function

    HT45F4050 A/D NFC Flash MCU To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place.

  • Page 203: Low Voltage Detector - Lvd

    HT45F4050 A/D NFC Flash MCU Low Voltage Detector – LVD This device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, V , and provide a warning signal should it fall below a certain level.

  • Page 204: Lvd Operation

    HT45F4050 A/D NFC Flash MCU LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, V , with a pre-specified voltage level stored in the LVDC register. This has a range of between 1.8V and 4.0V. When the power supply voltage, V , falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition.

  • Page 205: Configuration Options

    HT45F4050 A/D NFC Flash MCU Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program.

  • Page 206: Application Descriptions

    APP opening, resulting in faster data link. The HT45F4050 acts as a passive NFC tag which can only be accessed by other NFC active devices. NFC tags are usually used in advertisement, small amount of data storage and data transmission to the NFC active devices, etc.
  • Page 207 4. Regarding the data read stage, the domo board acts as a passive NFC tag after the data are stored into the Flash memory and the HT45F4050 is still power-supplied by VDD. An induction antenna on board is used for radio frequency communication between the tag and reader.

  • Page 208: Hardware Circuit

    HT45F4050 A/D NFC Flash MCU Hardware Circuit HT45F4050 SPI Flash PF1/SDO/SCOM1 AVDD PF2/SDI/SDA/SCOM2 PF3/SCK/SCL/SCOM3 PF0/SCS/SCOM0 0.1uF HOLD 10uF 0.1uF AVSS STOP PC5/AN5 START PC4/AN4 C2 20pF LED1 LED2 LED3 LOW BAT ALARM MODE DHT12 PB3/CTP PB2/PTCK/PTPB 4.7K 4.7K 10uF PA4/SDI/SDA...

  • Page 209: Instruction Set

    In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads.

  • Page 210: Logical And Rotate Operation

    The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps.

  • Page 211: Instruction Set Summary

    HT45F4050 A/D NFC Flash MCU Instruction Set Summary The instructions related to the data memory access in the following table can be used when the desired data memory is located in Data Memory sector 0. Table Conventions x: Bits immediate data...
  • Page 212 HT45F4050 A/D NFC Flash MCU Mnemonic Description Cycles Flag Affected Data Move MOV A,[m] Move Data Memory to ACC None MOV [m],A Move ACC to Data Memory Note None MOV A,x Move immediate data to ACC None Bit Operation CLR [m].i...

  • Page 213: Extended Instruction Set

    HT45F4050 A/D NFC Flash MCU Extended Instruction Set The extended instructions are used to support the full range address access for the data memory. When the accessed data memory is located in any data memory sector except sector 0, the extended instruction can be used to directly access the data memory instead of using the indirect addressing access.
  • Page 214 HT45F4050 A/D NFC Flash MCU Mnemonic Description Cycles Flag Affected Branch LSZ [m] Skip if Data Memory is zero Note None LSZA [m] Skip if Data Memory is zero with data movement to ACC Note None LSNZ [m] Skip if Data Memory is not zero...

  • Page 215: Instruction Definition

    HT45F4050 A/D NFC Flash MCU Instruction Definition Add Data Memory to ACC with Carry ADC A,[m] Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C...
  • Page 216 HT45F4050 A/D NFC Flash MCU CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address.
  • Page 217 HT45F4050 A/D NFC Flash MCU DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. Operation [m] ← [m] − 1 Affected flag(s) DECA [m] Decrement Data Memory with result in ACC Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator.
  • Page 218 HT45F4050 A/D NFC Flash MCU No operation Description No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation.
  • Page 219 HT45F4050 A/D NFC Flash MCU RLA [m] Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
  • Page 220 HT45F4050 A/D NFC Flash MCU RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
  • Page 221 HT45F4050 A/D NFC Flash MCU Set Data Memory SET [m] Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1.
  • Page 222 HT45F4050 A/D NFC Flash MCU SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
  • Page 223 HT45F4050 A/D NFC Flash MCU TABRD [m] Read table (specific page) to TBLH and Data Memory Description The low byte of the program code (specific page) addressed by the table pointer pair (TBLP and TBHP) is moved to the specified Data Memory and the high byte moved to TBLH.

  • Page 224: Extended Instruction Definition

    HT45F4050 A/D NFC Flash MCU Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added.
  • Page 225 HT45F4050 A/D NFC Flash MCU LCPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. Operation [m] ← [m]...
  • Page 226 HT45F4050 A/D NFC Flash MCU LMOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ← [m] Affected flag(s) None LMOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory.
  • Page 227 HT45F4050 A/D NFC Flash MCU LRR [m] Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0...
  • Page 228 HT45F4050 A/D NFC Flash MCU LSDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction.
  • Page 229 HT45F4050 A/D NFC Flash MCU LSNZ [m] Skip if Data Memory is not 0 Description If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction.
  • Page 230 HT45F4050 A/D NFC Flash MCU LSZ [m].i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction.

  • Page 231: Package Information

    HT45F4050 A/D NFC Flash MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website the latest version of the Package/Carton Information.

  • Page 232: 48-Pin Lqfp (7Mm × 7Mm) Outline Dimensions

    HT45F4050 A/D NFC Flash MCU 48-pin LQFP (7mm × 7mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. — 0.354 BSC — — 0.276 BSC — — 0.354 BSC — — 0.276 BSC — — 0.020 BSC — 0.007 0.009...
  • Page 233 However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise.

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