1. Manuals
  2. Brands
  3. Holtek Manuals
  4. Storage
  5. HT66F0175
  6. Manual

Holtek HT66F0175 Manual

A/d flash mcu with eeprom
Hide thumbs
Table of Contents

Advertisement

Quick Links

A/D Flash MCU with EEPROM
HT66F0175/HT66F0185
Revision: V1.50
Date: ����st ��� �01�
����st ��� �01�

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the HT66F0175 and is the answer not in the manual?

Questions and answers

Related Manuals for Holtek HT66F0175

Summary of Contents for Holtek HT66F0175

  • Page 1: 0-Pin Sop (300Mil) O�Tline Dimensions

    A/D Flash MCU with EEPROM HT66F0175/HT66F0185 Revision: V1.50 Date: ����st ��� �01� ����st ��� �01�...

  • Page 2: Table Of Contents

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Table of Contents Features ........................ 7 CPU Feat�res ..........................� Peripheral Feat�res ........................� General Description ..................... 8 Selection Table ..................... 8 Block Diagram ...................... 9 Pin Assignment ....................9 Pin Descriptions ....................11 Absolute Maximum Ratings ................17 D.C.

  • Page 3: Tm Inp�T/O�Tp�T Pin Control Re�Ister

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM EEPROM Data Memory ..................37 EEPROM Data Memory Str�ct�re .....................3� EEPROM Re�isters ........................3� Readin� Data from the EEPROM ....................39 Writin� Data to the EEPROM .....................39 Write Protection ..........................39 EEPROM Interr�pt ........................39 Pro�rammin� Considerations .....................40 Oscillator ......................

  • Page 4: 4-Pin Ssop (150Mil) O�Tline Dimensions

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Timer Modules – TM ..................71 Introd�ction ..........................�1 TM Operation ..........................�1 TM Clock So�rce ........................�� TM Interr�pts ..........................�� TM External Pins ........................�� TM Inp�t/O�tp�t Pin Control Re�ister ..................�3 Pro�rammin� Considerations .....................�5 Compact Type TM – CTM .................. 76 Compact TM Operation ......................�6...

  • Page 5: Pro�Rammin� Considerations

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Comparators ....................146 Comparator Operation ......................146 Comparator Interr�pt ........................146 Pro�rammin� Considerations ....................146 SCOM/SSEG Function for LCD ............... 148 LCD Operation .........................14� LCD Control Re�isters ......................150 UART Interface ....................155 U�RT External Pin ........................156 U�RT Data Transfer Scheme....................156 U�RT Stat�s and Control Re�isters..................156...

  • Page 6: Rithmetic And Lo�Ic Unit

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Instruction Set ....................187 Introd�ction ..........................1�� Instr�ction Timin� ........................1�� Movin� and Transferrin� Data ....................1�� �rithmetic Operations .......................1�� Lo�ical and Rotate Operation ....................1�� Branches and Control Transfer ....................1�� Bit Operations ..........................1�� Table Read Operations ......................1��...

  • Page 7: Features

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Features CPU Features • Operating voltage = 8MHz: 2.2V~5.5V ♦ =12MHz: 2.7V~5.5V ♦ =20MHz: 4.5V~5.5V ♦ • Up to 0.2μs instruction cycle with 20MHz system clock at V • Power down and wake-up functions to reduce power consumption • Oscillator type External High Speed Crystal – HXT ♦ External 32.768kHz Crystal – LXT ♦ Internal High Speed RC – HIRC ♦ Internal 32kHz RC – LIRC ♦ • Fully integrated internal 8/12/16 MHz oscillator requires no external components • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one to two instruction cycles • Table read instructions • 63 powerful instructions • 8-level subroutine nesting...

  • Page 8: General Description

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM General Description The series of devices are Flash Memory A/D type 8-bit high performance RISC architecture microcontroller. Offering users the convenience of Flash Memory multi-programming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile data such as serial numbers, calibratuib data, etc. Analog features include a multi-channel 12-bit A/D converter and a comparator functions. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HXT, LXT, HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically...

  • Page 9: Block Diagram

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Block Diagram Internal Watchdog HIRC/LIRC Timer Reset Oscillators Circuit Flash/EEPROM 8-bit Programming Circuitry Interrupt RISC Controller Voltage Voltage Core Detect Reset External HXT/LXT Oscillators EEPROM Flash RAM Data Time Data Program Memory Base Memory...
  • Page 10 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM VSS&�VSS VDD&�VDD �4 PC0/SSEG1�/OSC1 � PB0/INT0/SSEG16/�N0/XT1 �3 PB1/INT1/SSEG15/�N1/XT� PC1/SSEG1�/OSC� �� PC�/SDO/SSEG0/SCOM0 PB�/TCK0/SSEG14/�N� �1 P�4/TCK1/SSEG13/�N3 P�0/TP0/ICPD�/OCDSD� �0 PC3/SDI/SD�/SSEG19 PC6/[INT0]/SSEG1� PC4/SCK/SCL/SSEG1/SCOM1 � PC5/[INT1]/SSEG11 1� P�1/[SDO]/SCS/SSEG�/SCOM� � P�5/SSEG10/�N4/VREFI 1� P��/ICPCK/OCDSCK P�6/SSEG9/�N5/VREF P�3/[SDI/SD�]/SSEG3/SCOM3 P��/TP1/SSEG�/�N6 PB6/[SCK/SCL]/SSEG4/SCOM4 PB3/SSEG�/�N� PB5/[SCS]/SSEG5/SCOM5 1�...

  • Page 11: Pin Descriptions

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Pin Descriptions With the exception of the power pins, all pins on these devices can be referenced by their Port name, e.g. PA0, PA1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Analog to Digital Converter, Timer Module pins, etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. HT66F0175 Pad Name Function Description P�WU General p�rpose I/O. Re�ister enabled p�ll-�p and P�0 CMOS P�PU wake-�p. P�0/TP0/ICPD�/ TMPC CMOS TM0 inp�t/o�tp�t OCDSD� ICPD� — CMOS ICP Data/�ddress pin OCDSD�...
  • Page 12 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Pad Name Function Description P�WU General p�rpose I/O. Re�ister enabled p�ll-�p and P�6 CMOS P�PU wake-�p. P�6/SSEG9/�N5/ SSEG9 SLCDC� — SSEG Software controlled LCD se�ment o�tp�t VREF �N5 �CERL �N — �/D Converter analo� inp�t VREF S�DC�...
  • Page 13 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Pad Name Function Description PC� PCPU CMOS General p�rpose I/O. Re�ister enabled p�ll-�p. SIMC0 — CMOS SPI data o�tp�t PC�/SDO/SSEG0/ SLCDC0 SCOM0 SSEG0 — SSEG Software controlled LCD se�ment o�tp�t SLCDC1 SLCDC0 SCOM0 —...
  • Page 14 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Pad Name Function Description P�WU General p�rpose I/O. Re�ister enabled p�ll-�p and P�1 CMOS P�PU wake-�p. SLCDC0 [SDO] SIMC0 — CMOS SPI data o�tp�t P�1/[SDO]/SSEG�/ SCOM� SLCDC0 SSEG� — SSEG Software controlled LCD se�ment o�tp�t...
  • Page 15 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Pad Name Function Description PBPU CMOS General p�rpose I/O. Re�ister enabled p�ll-�p. INTEG INT1 — External Interr�pt 1 PB1/INT1/SSEG1�/ �N1/XT� SSEG1� SLCDC3 — SSEG Software controlled LCD se�ment o�tp�t �N1 �CERL �N — �/D Converter analo� inp�t XT�...
  • Page 16 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Pad Name Function Description PCPU CMOS General p�rpose I/O. Re�ister enabled p�ll-�p. SIMC0 PC3/SDO/SSEG�1 — CMOS SPI data o�tp�t SSEG�1 SLCDC3 — SSEG Software controlled LCD se�ment o�tp�t PCPU CMOS General p�rpose I/O. Re�ister enabled p�ll-�p.

  • Page 17: Absolute Maximum Ratings

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Absolute Maximum Ratings Supply Voltage ....................V −0.3V to V +6.0V Input Voltage .....................V −0.3V to V +0.3V Storage Temperature ...................... -50˚C to 125˚C Operating Temperature .....................-40˚C to 85˚C Total ............................-80mA Total ............................80mA Total Power Dissipation ......................500mW Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to these devices. Functional operation of these devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect devices reliability.
  • Page 18 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions 3V No load� all peripherals off� — μA Standby C�rrent (IDLE0 Mode) — μA 3V f — m� =�MHz on� f No load� all peripherals off —...

  • Page 19: A.c. Characteristics

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM A.C. Characteristics Ta=�5°C Test Condition Symbol Parameter Min. Typ. Max. Unit Condition �.�V~5.5V f =�MHz — � — �.�V~5.5V f =1�MHz — 1� — System Clock (HXT) 4.5V~5.5V f =16MHz — — 4.5V~5.5V f =�0MHz...

  • Page 20: Hirc Electrical Characteristics

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM HIRC Electrical Characteristics Ta=�5°C Frequency Accuracy trimmed 8MHz at V Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Ta = �5°C -�% � +�% 3V ± 0.3V Ta = 0°C ~ �0°C �...

  • Page 21: A/D Converter Electrical Characteristics

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Frequency Accuracy trimmed 12MHz at V Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Ta = �5°C -�% 1� +�% 5V ± 0.5V Ta = 0°C ~ �0°C 1� 5V ± 0.5V Ta = -40°C ~ �5°C -�%...

  • Page 22: Lvd/Lvr Electrical Characteristics

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM LVD/LVR Electrical Characteristics Ta=�5°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions LVR Enable� volta�e select �.1V �.1 LVR Enable� volta�e select �.55V �.55 Low Volta�e Reset Volta�e — LVR Enable� volta�e select 3.15V 3.15...

  • Page 23: Software Controlled Lcd Driver Electrical Characteristics

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Software Controlled LCD Driver Electrical Characteristics Ta=�5°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions ISEL[1:0]=00 4.� �.3 μA ISEL[1:0]=01 �.3 16.� �5 μA Bias c�rrent BI�S ISEL[1:0]=10 �5 �5 μA ISEL[1:0]=11 μA [(�/3) ×...

  • Page 24: System Architecture

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator...
  • Page 25 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. F e t c h I n s t . 1 E x e c u t e I n s t . 1 M O V A , [ 1 2 H ] F e t c h I n s t .

  • Page 26: Pro�Ram Co�Nter

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. Pro�ram Co�nter Top of Stack Stack Level 1 Stack Level � Stack Stack Level 3 Pointer Pro�ram Memory Bottom of Stack Stack Level �...

  • Page 27: Flash Program Memory

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Flash Program Memory The Program Memory is the location where the user code or program is stored. For these devices series the Program Memory are Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Device Capacity HT66F01�5 �K × 16 HT66F01�5 4K × 16 Structure The Program Memory has a capacity of 2K×16 to 4K×16 bits. The Program Memory is addressed...
  • Page 28 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the “TABRD [m]” or “TABRDL [m]” instructions respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as “0”.

  • Page 29: In Circ�It Pro�Rammin� - Icp

    In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in- circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re- insertion of the device. Holtek Writer Pins MCU Programming Pins Pin Description ICPD� P�0 Pro�rammin� Serial Data/�ddress ICPCK P�� Pro�rammin� Clock Power S�pply...

  • Page 30: On-Chip Deb�� S�Pport Data/�Ddress Inp�T/O�Tp�T

    On-Chip Debug Support – OCDS There is an EV chip named HT66V01x5 which is used to emulate the real MCU device named HT66F01x5. The EV chip device also provides the “On-Chip Debug” function to debug the real MCU device during development process. The EV chip and real MCU devices, HT66V01x5 and HT66F01x5, are almost functional compatible except the “On-Chip Debug” function. Users can use the EV chip device to emulate the real MCU device behaviors by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip device for debugging, the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the real MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”.

  • Page 31: Data Memory

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Data Memory The Data Memory is an 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two banks, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into two banks. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for the device is the address 00H. The address range of the Special Purpose Data Memory for the device is from 00H to 7FH while the address range of the General Purpose Data Memory is from 80H to FFH. Device Capacity Banks HT66F01�5 1�� × � 0: �0H~FFH 0: �0H~FFH HT66F01�5 �56 × � 1: �0H~FFH...
  • Page 32 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Bank 0� 1 Bank 0 Bank 1 Bank 0� 1 Bank 0 Bank 1 I�R0 3�H TM1C0 I�R0 3�H TM1C0 3�H TM1C1 3�H TM1C1 0�H I�R1 TM1DL 0�H I�R1 TM1DL 3�H TM1DH 3�H TM1DH TM1�L...

  • Page 33: Special Function Register Description

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section. However, several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data only from Bank 0 while the IAR1 register together with MP1 register pair can access data from any Data Memory bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 The Memory Pointers, known as MP0 and MP1, are provided. These Memory Pointers are...

  • Page 34: Bank Pointer - Bp

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Bank Pointer – BP For the HT66F0185 device, the Data Memory is divided into two banks, Bank0 and Bank1. Selecting the required Data Memory area is achieved using the Bank Pointer. Bit 0 of the Bank Pointer is used to select Data Memory Banks 0~1. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed...

  • Page 35: Stat�S Re�Ister - St�Tus

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing the “HALT” or “CLR WDT” instruction or during a system power-up. The Z, OV, AC, and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. • TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
  • Page 36 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM STATUS Register Name — — �C — — — — “x”: �nknown Bit 7~6 Unimplemented, read as “0” Bit 5 TO: Watchdog Time-out flag 0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred Bit 4 PDF: Power down flag 0: After power up or executing the “CLR WDT” instruction 1: By executing the “HALT” instructin Bit 3 OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: No auxiliary carry...

  • Page 37: Eeprom Data Memory

    — EE�6 EE�5 EE�4 EE�3 EE�� EE�1 EE�0 D� D� — — — — WREN RDEN EEPROM Registers List EEA Register – HT66F0175 Name — — EE�5 EE�4 EE�3 EE�� EE�1 EE�0 — — — — Bit 7~6 Unimplemented, read as “0” Bit 5~0 EEA5~EEA0: Data EEPROM address bit 5 ~ bit0 Rev.
  • Page 38 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM EEA Register – HT66F0185 Name — EE�6 EE�5 EE�4 EE�3 EE�� EE�1 EE�0 — — Bit 7 Unimplemented, read as “0” EEA6~EEA0: Data EEPROM address bit 6 ~ bit0 Bit 6~0 EED Register Name D� D� Bit 7~0 D7~D0: Data EEPROM data bit 7~bit0 EEC Register Name — — — — WREN RDEN —...

  • Page 39: Readin� Data From The Eeprom

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. Then the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the...

  • Page 40: Pro�Rammin� Considerations

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer register could be normally cleared to zero as this would inhibit access to bank 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Programming Example Reading data from the EEPROM − polling method MOV A, EEPROM_ADRES ; user defined address MOV EEA, A MOV A, 040H ;...

  • Page 41: Oscillator

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Oscillator Various oscillator types offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and relevant control registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through configuration options. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Type Name Frequency Pins Hi�h Speed External Crystal 400 kHz~�0 MHz OSC1/OSC� Hi�h Speed Internal RC HIRC �/1�/16 MHz...

  • Page 42: External Crystal/Ceramic Oscillator - Hxt

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Hi�h Speed /� Oscillator /� Prescaler HIRC /3� Hi�h Speed Oscillator Low Speed Confi��ration Option Oscillator Fast Wake-�p from IDLE or SLEEP Mode Control HLCLK� (for HXT only ) CKS�~CKS0 LIRC Low Speed Oscillator Confi��ration Option...

  • Page 43: Internal Hi�H Speed Rc Oscillator - Hirc

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Internal High Speed RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has three fixed frequencies of 8MHz, 12MHz, 16MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of either 3V or 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 8MHz, 12MHz or 16MHz will have a tolerance within 2%. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins are free for use as normal I/O pins. External 32.768 kHz Crystal Oscillator – LXT The External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. This clock source has a fixed frequency of 32.768 kHz and requires a 32.768 kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768 kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. During power-up...

  • Page 44: Internal 3�Khz Oscillator - Lirc

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM LXT Oscillator C1 and C2 Values Crystal Frequency 3�.�6�kHz 10pF 10pF Note: 1. C1 and C� val�es are for ��idance only. �. R =5MΩ~10MΩ is recommended. 32.768kHz Crystal Recommended Capacitor Values LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the TBC register.

  • Page 45: Operating Modes And System Clocks

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The devices have many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency f or low frequency f source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from either an HXT or HIRC oscillator, selected via a configuration option. The low speed system clock source can be sourced from internal clock f . If f is selected then it can be sourced by either the LXT or LIRC oscillator, selected via a configuration option. The other choice, which is a divided version of the high speed system oscillator has a range of f /2~ f /64. There are two additional internal clocks for the peripheral circuits, the substitute clock, f , and the Time Base clock, f . Each of these internal clocks is sourced by either the LXT or LIRC oscillators, selected via configuration options. The f clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times.

  • Page 46: System Operation Modes

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0,...
  • Page 47 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. Control Registers A single register, SMOD, is used for overall control of the internal clocks within the devices. SMOD Register Name CKS� CKS1 CKS0 FSTEN IDLEN HLCLK Bit 7~5 CKS2~CKS0: System clock selection when HLCLK is “0” 000: f 001: f 010: f 011: f 100: f 101: f 110: f 111: f These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be either the LXT or LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source.
  • Page 48 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM HTO: High speed system oscillator ready flag Bit 2 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to “0” by hardware when the devices are powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as “1” by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake- up has occurred, the flag will change to a high level after 512 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if the HIRC oscillator is used. Bit 1 IDLEN: IDLE mode control 0: Disable 1: Enable This is the IDLE mode control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is execured, the device will enter the IDLE mode. In the IDLE mode the CPU will stop running but the system clock will continye to keep the peripheral functions operational, if the FSYSON bit is high. If the FSYSON bit is low, the CPU and the system clock will all...

  • Page 49: Fast Wake-�P

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Fast Wake-up To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system clock source to the devices will be stopped. However when the devices are woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. To ensure the devices are up and running as fast as possible a Fast Wake- up function is provided, which allows f , namely either the LXT or LIRC oscillator, to act as a temporary clock to first drive the system until the original system oscillator has stabilised. As the clock source for the Fast Wake-up function is f , the Fast Wake-up function is only available in the SLEEP1 and IDLE0 modes. When the devices are woken up from the SLEEP0 mode, the Fast Wake-up function has no effect because the f clock is stopped. The Fast Wake-up enable/disable function is controlled using the FSTEN bit in the SMOD register. If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up function is enabled, then it will take one to two t clock cycles of the LIRC or LXT oscillator for the system to wake-up. The system will then initially run under the f clock source until 512 HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator. If the HIRC oscillator or LIRC oscillator is used as the system oscillator then it will take 15~16 clock cycles of the HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases. System FSTEN Wake-up Time Wake-up Time Wake-up Time Wake-up Time...

  • Page 50: Operatin� Mode Switchin

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Operating Mode Switching These devices can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the devices enter the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and the FSYSON bit in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock, f , to the clock source, f /2~f /64 or f . If the clock is from the f , the high speed clock source will stop running to conserve power. When this happens, it must be noted that...
  • Page 51 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to “0” and set the CKS2~CKS0 bits to “000” or “001” in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the configuration option and therefore requires this oscillator to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. NORMAL Mode CKS�~CKS0 = 00xB & HLCLK = 0 SLOW Mode WDT and LVD are all off IDLEN=0 H�LT instr�ction is exec�ted...
  • Page 52 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM SLOW Mode to NORMAL Mode Switching In SLOW mode the system uses either the LXT or LIRC low speed system oscillator. To switch back to the NARMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to “1” or HLCLK bit is “0”, but CKS2~CKS0 field is set to “010”, “011”, “100”, “101”, “110” or “111”. As a certain amount of time will be required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. SLOW Mode CKS2~CKS0 ≠ 000B or 001B as HLCLK = 0 or HLCLK = 1 NORMAL Mode WDT and LVD are all off...
  • Page 53 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Entering the SLEEP1 Mode There is only one way for the devices to enter the SLEEP1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in the SMOD register equal to “0” and the WDT on. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock will be stopped and the application program will stop at the "HALT" instruction, but the WDT will remain with the clock source coming from the f clock. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT function is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. Entering the IDLE0 Mode There is only one way for the devices to enter the IDLE0 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in the SMOD register equal to “1” and the FSYSON bit in the CTRL register equal to “0”. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the “HALT”...

  • Page 54: Standby C�Rrent Considerations

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LIRC oscillator has enabled. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed oscillator, the additional standby current will also be perhaps in the order of several hundred micro- amps. Wake-up To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the CPU will be switched off. However, when the device is woken up again, it will take a considerable...

  • Page 55: Pro�Rammin� Considerations

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Programming Considerations The high speed and low speed oscillators both use the same SST counter. For example, if the system is woken up from the SLEEP0 Mode and both the HIRC and LXT oscillators need to start-up from an off state. The LXT oscillator uses the SST counter after the HIRC oscillator has finished its SST period. • If the devices are woken up from the SLEEP0 Mode to the NORMAL Mode, the high speed system oscillator needs an SST period. The devices will execute first instruction after HTO is “1”. At this time, the LXT oscillator may not be stability if f is from LXT oscillator. The same situation occurs in the power-on state. The LXT oscillator is not ready yet when the first instruction is executed. • If the devices are woken up from the SLEEP1 Mode to NORMAL Mode, and the system clock source is from the HXT oscillator and FSTEN is “1”, the system clock can be switched to the LIRC oscillator after wake up. • There are peripheral functions, such as WDT and TMs, for which the f is used. If the system clock source is switched from f to f , the clock source to the peripheral functions mentioned above will change accordingly. • The on/off condition of f and f depends upon whether the WDT is enabled or disabled as the WDT clock source is selected from f Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source...
  • Page 56 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM WDTC Register Name WE� WS� Bit 7~3 WE4~WE0: WDT function enable control 10101: Disabled 01010: Enabled Other values: Reset MCU If these bits are changed due to adverse environmental conditions, the microcontroller will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit in the CTRL register will be set to 1. WS2~WS0: WDT time-out period selection Bit 2~0 000: 2 001: 2 010: 2 011: 2 100: 2 101: 2 110: 2 111: 2 These three bits determine the division ratio of the watchdog timer source clock, which in turn determines the time-out period.

  • Page 57: Watchdo� Timer Operation

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instruction. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/disable function, there are five bits, WE4~WE0, in the WDTC register to offer the enable/disable control and reset control of the Watchdog Timer. The WDT function will be disabled when the WE4~WE0 bits are set to a value of 10101B while the WDT function will be enabled if the WE4~WE0 bits are equal to 01010B. If the WE4~WE0 bits are set to any other values, except 01010B and 10101B, it will reset the device after 2~3 f clock cycles. After power LIRC on these bits will have a value of 01010B. WE4 ~ WE0 Bits WDT Function 10101B Disable 01010B Enable �ny other val�e Reset MCU Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer...

  • Page 58: Reset And Initialisation

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, another reset exists in the form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. Another type of reset is when the Watchdog Timer overflows and resets the...
  • Page 59 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM RSTD Internal Reset Note: t is power-on delay with typical time = 50 ms RSTD Low Voltage Reset Timing Chart • LVRC Register Name LVS� LVS6 LVS5 LVS4 LVS3 LVS� LVS1 LVS0 Bit 7~0 LVS7~LVS0: LVR voltage select 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Other values: Generates a MCU reset – register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage value above, an MCU reset will generated. The reset operation will be activated after 2~3 f clock cycles. In this situation the register contents will remain LIRC the same after such a reset occurs.

  • Page 60: Reset Initial Conditions

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as the hardware Low Voltage Reset except that the Watchdog time-out flag TO will be set to “1”. WDT Time-o�t RSTD Internal Reset Note: t is power-on delay with typical time = 16.7 ms RSTD WDT Time-out Reset during NORMAL Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for...
  • Page 61 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Reset LVR Reset WDT Time-out WDT Time-out Register (Power On) (Normal Operation) (Normal Operation) (IDLE or SLEEP)* ● ● x x x x x x x x x x x x x x x x x x x x x x x x �...
  • Page 62 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Reset LVR Reset WDT Time-out WDT Time-out Register (Power On) (Normal Operation) (Normal Operation) (IDLE or SLEEP)* PBPU ● ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - �...
  • Page 63 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Reset LVR Reset WDT Time-out WDT Time-out Register (Power On) (Normal Operation) (Normal Operation) (IDLE or SLEEP)* SLCDC3 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 �...

  • Page 64: Input/Output Ports

    PBC1 PBC0 PBPU — PBPU6 PBPU5 PBPU4 PBPU3 PBPU� PBPU1 PBPU0 — PC� — PCC6 PCC5 PCC4 PCC3 PCC� PCC1 PCC0 PCPU — PCPU6 PCPU5 PCPU4 PCPU3 PCPU� PCPU1 PCPU0 I/O Registers List – HT66F0175 Rev. 1.50 ����st ��� �01�...

  • Page 65: P�Ll-Hi�H Resistors

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Register Name P�WU P�WU� P�WU6 P�WU5 P�WU4 P�WU3 P�WU� P�WU1 P�WU0 P� P�� P�6 P�5 P�4 P�3 P�� P�1 P�0 P�C P�C� P�C6 P�C5 P�C4 P�C3 P�C� P�C1 P�C0 P�PU P�PU� P�PU6 P�PU5 P�PU4 P�PU3...

  • Page 66: I/O Port Control Re�Isters

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM I/O Port Control Registers Each Port has its own control register, known as PAC~PDC, which controls the input/output configuration. With this control register, each I/O pin with or without pull-high resistors can be reconfigured dynamically under software control. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a “1”. This will then allow the logic state...
  • Page 67 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM SLEDC1 Register – HT66F0175 Name — — — — PCPS3 PCPS� PCPS1 PCPS0 — — — — — — — — Bit 7~4 Unimplemented, read as “0” PCPS3~PCPS2: PC6~PC4 source current selection Bit 3~2 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) Bit 1~0 PCPS1~PCPS0: PC3~PC0 source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.)
  • Page 68 — — SDOPS SDI_SD�PS SCK_SCLPS SCSBPS INT1PS INT0PS (HT66F01�5) — SDOPS1 SDOPS0 SDI_SD�PS SCK_SCLPS SCSBPS TXPS RXPS (HT66F01�5) Pin-remapping Function Selection Registers List IFS Register – HT66F0175 Name — — SDOPS SDI_SD�PS SCK_SCLPS SCSBPS INT1PS INT0PS — — — —...

  • Page 69: I/O Pin Str�Ct�Res

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM IFS Register – HT66F0185 Name — SDOPS1 SDOPS0 SDI_SD�PS SCK_SCLPS SCSBPS TXPS RXPS — — Bit 7 Unimplemented, read as “0” SDOPS1~SDOPS0: SDO pin-remapping selection Bit 6~5 00: SDO on PC3 01: SDO on PA1 10: Undefined 11: SDO on PC2 Bit 4 SDI_SDAPS: SDI/SDA pin-remapping selection 0: SDI/SDA on PC4 1: SDI/SDA on PA3 Bit 3 SCK_SCLPS: SCK/SCL pin-remapping selection 0: SCK/CL on PC5 1: SCK/CL on PB6 Bit 2 SCSBPS: SCS pin-remapping selection 0: SCS on PC6...
  • Page 70 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM P u l l - H i g h R e g i s t e r C o n t r o l B i t W e a k S e l e c t...

  • Page 71: Timer Modules - Tm

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Timer Modules – TM One of the most fundamental functions in any microcontroller devices is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, generally abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact, Standard and Periodic TM sections. Introduction The devices contain two or three TMs depending upon which device is selected with each TM having a reference name of TM0, TM1, and TM2. Each individual TM can be categorised as a certain type, namely Compact Type TM, Standard Type TM or Periodic Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact, Standard and Periodic TMs will be described in this section and the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the three types of TMs are summarised in the accompanying table.

  • Page 72: Tm External Pins

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. The clock source can be a ratio of the system clock, f , or the internal high clock, , the f clock source or the external TCKn pin. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source for event counting. TM Interrupts The Compact, Standard or Periodic type TM has two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TCKn pin is also used as the external trigger input pin in single pulse output mode for the STM and PTM respectively. The TMs each have one output pin with the label TPn. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. The TPn pin acts as an input when the TM is setup to...
  • Page 73 P�0 O�tp�t F�nction P�0/TP0 O�tp�t T0CP P�0 (PTM) Capt�re Inp�t T0C�PTS TCK Inp�t PB�/TCK0 TM0 Function Pin Control Block Diagram – HT66F0175 only P�0 O�tp�t F�nction P�0/TP0 O�tp�t T0CP P�0 (STM) Capt�re Inp�t TCK Inp�t PB�/TCK0 TM0 Function Pin Control Block Diagram – HT66F0185 only P��...
  • Page 74 A/D Flash MCU with EEPROM PB3 O�tp�t F�nction PB3/TP� O�tp�t (CTM) T�CP TCK Inp�t P�6/TCK� TM2 Function Pin Control Block Diagram – HT66F0185 only Note: 1. The I/O register data bits shown are used for TM output inversion control. 2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input. TMPC Register – HT66F0175 Name CLOP — — — — — T1CP T0CP — —...
  • Page 75 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, being either 10- bit or 16-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the “MOV” instruction to access the CCRA and CCRP low byte registers, named TMnAL and TMnRPL, using the following access procedures. Accessing the CCRA or CCRP low byte registers without following these access procedures will result in unpredictable values. TMn Co�nter Re�ister (Read only) TMnDL TMnDH �-bit B�ffer TMn�L TMn�H TMn CCR� Re�ister (Read/Write) TMnRPL TMnRPH PTM CCRP Re�ister (Read/Write) Data B�s...

  • Page 76: Compact Type Tm - Ctm

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Compact Type TM – CTM The Compact type TM, CTM, is only contained in the HT66F0185 device. Although the simplest form of the TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive one external output pin. Device TM Core TM No. TM Input Pin TM Output Pin HT66F01�5 16-bit CTM TM�...
  • Page 77 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Compact Type TM Register Description Overall operation of the Compact TM is controlled using a series of registers. A read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit CCRA value. There is also a read/write register used to store the internal 8-bit CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name TMnC0 TnP�U TnCK� TnCK1 TnCK0 TnON — — — TMnC1 TnM1 TnM0 TnIO1 TnIO0...
  • Page 78 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TMnC0 Register Name TnP�U TnCK� TnCK1 TnCK0 TnON — — — — — — — — — Bit 7 TnPAU: TMn Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TMn will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 TnCK2~TnCK0: Select TMn Counter clock 000: f 001: f 010: f 011: f 100: f 101: f...
  • Page 79 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TMnC1 Register Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR Bit 7~6 TnM1~TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TMn. To ensure reliable operation the TMn should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TMn output pin control will be disabled. Bit 5~4 TnIO1~TnIO0: Select TPn pin output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Undefined Timer/Counter Mode Unused These two bits are used to determine how the TMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which...
  • Page 80 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TnOC: TPn Output control Bit 3 Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode 0: Active low 1: Active high This is the output control bit for the TMn output pin. Its operation depends upon whether TMn is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TMn output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 TnPOL: TPn Output polarity control...

  • Page 81: Compact Type Tm Operation Modes

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Compact Type TM Operation Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to “00” respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TMnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 1-bit, FFFF Hex, value, however here the TnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TMn output pin will change state. The TMn output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TMn output pin. The way in which the TMn output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TMn output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TMn output pin, which is setup after the...
  • Page 82 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter overflow Co�nter Val�e TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 CCRP=0 Co�nter cleared by CCRP val�e 0xFFFF CCRP > 0 Co�nter Res�me Restart CCRP Pa�se Stop CCR� Time TnON TnP�U TnPOL CCRP Int.
  • Page 83 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = 1; TnM [1:0] = 00 CCR� = 0 CCR� > 0 Co�nter cleared by CCR� val�e Co�nter overflow 0xFFFF CCR�=0 Res�me CCR� Pa�se Stop Co�nter Restart CCRP Time TnON TnP�U TnPOL No Tn�F fla�...
  • Page 84 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TMn output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TMn output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TMn is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency...
  • Page 85 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter Val�e TnDPX = 0; TnM [1:0] = 10 Co�nter cleared by CCRP Co�nter Reset when TnON ret�rns hi�h CCRP Co�nter Stop if Pa�se Res�me TnON bit low CCR� Time TnON TnP�U TnPOL CCR� Int. fla�...
  • Page 86 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter Val�e TnDPX = 1; TnM [1:0] = 10 Co�nter cleared by CCR� Co�nter Reset when TnON ret�rns hi�h CCR� Co�nter Stop if Pa�se Res�me TnON bit low CCRP Time TnON TnP�U TnPOL CCRP Int.

  • Page 87: Standard Type Tm - Stm

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Standard Type TM – STM The Standard Type TM, STM, is only contained in the HT66F0185 device. The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external input pin and can drive one external output pin. Device TM Core TM No. TM Input Pin TM Output Pin HT66F01�5 16-bit STM TCK0 CCRP Comparator P Match �-bit Comparator P TnPF Interr�pt TnOC b�~b15...
  • Page 88 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit CCRA value. The TMnRP register is used to store the 8-bit CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Name TMnC0 TnP�U TnCK� TnCK1 TnCK0 TnON — — — TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR TMnDL D� D� TMnDH D1�...
  • Page 89 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TMnC0 Register Name TnP�U TnCK� TnCK1 TnCK0 TnON — — — — — — — — — Bit 7 TnPAU: TMn Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TMn will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 TnCK2~TnCK0: Select TMn Counter clock 000: f 001: f 010: f 011: f 100: f 101: f...
  • Page 90 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TMnC1 Register Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR Bit 7~6 TnM1~TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TMn. To ensure reliable operation the TMn should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TMn output pin control will be disabled. Bit 5~4 TnIO1~TnIO0: Select TPn pin output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of TPn...
  • Page 91 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TnOC: TMn TPn Output control Bit 3 Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TMn output pin. Its operation depends upon whether TMn is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TMn output pin before a compare match occurs. In the PWM Mode/Single Pulse Output Mode it determines if the PWM signal is active high or active low. Bit 2 TnPOL: TMn TPn Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the TPn output pin. When the bit is set high the TMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the TMn is in the Timer/Counter Mode.

  • Page 92: Standard Type Tm Operation Modes

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TMnRP Register Name TnRP� TnRP6 TnRP5 TnRP4 TnRP3 TnRP� TnRP1 TnRP0 Bit 7~0 TnRP7~TnRP0: TMn CCRP 8-bit register, compared with the TMn counter bit 15~bit 8 Comparator P match period: 0: 65536 TMn clocks 1~255: (1~255) × 256 TMn clocks These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter’s highest eight bits. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value.
  • Page 93 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter overflow Co�nter Val�e TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 CCRP=0 Co�nter cleared by CCRP val�e 0xFFFF CCRP > 0 Co�nter Res�me Restart CCRP Pa�se Stop CCR� Time TnON TnP�U TnPOL CCRP Int.
  • Page 94 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = 1; TnM [1:0] = 00 CCR� = 0 CCR� > 0 Co�nter cleared by CCR� val�e Co�nter overflow 0xFFFF CCR�=0 Res�me CCR� Pa�se Stop Co�nter Restart CCRP Time TnON TnP�U TnPOL No Tn�F fla�...
  • Page 95 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TMn output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TMn output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within the TMn is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle...
  • Page 96 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter Val�e TnDPX = 0; TnM [1:0] = 10 Co�nter cleared by CCRP Co�nter Reset when TnON ret�rns hi�h CCRP Co�nter Stop if Pa�se Res�me TnON bit low CCR� Time TnON TnP�U TnPOL CCR� Int.
  • Page 97 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter Val�e TnDPX = 1; TnM [1:0] = 10 Co�nter cleared by CCR� Co�nter Reset when TnON ret�rns hi�h CCR� Co�nter Stop if Pa�se Res�me TnON bit low CCRP Time TnON TnP�U TnPOL CCRP Int.
  • Page 98 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Single Pulse Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TMn output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TMn interrupt. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode. CCR� CCR� Leadin� Ed�e Trailin� Ed�e S/W Command S/W Command SET“TnON” CLR“TnON” TnON bit TnON bit 0 à...
  • Page 99 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter Val�e TnM [1:0] = 10 ; TnIO [1:0] = 11 Co�nter stopped by CCR� Co�nter Reset when TnON ret�rns hi�h CCR� Co�nter Stops Res�me Pa�se by software CCRP Time TnON ��to. set by...
  • Page 100 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Capture Input Mode To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPn pin, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPn pin the present value in the counter will be latched into the CCRA registers and a TMn interrupt generated. Irrespective of what events occur on the TPn pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TMn interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPn pin, however it must be noted that the counter will continue to run. The TnCCLR and TnDPX bits are not used in this Mode. Rev. 1.50 ����st ��� �01�...
  • Page 101 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter Val�e TnM [1:0] = 01 Co�nter cleared by CCRP Co�nter Co�nter Stop Reset CCRP Res�me Pa�se Time TnON TnP�U �ctive �ctive �ctive ed�e ed�e ed�e TMn capt�re pin CCR� Int. Fla� Tn�F CCRP Int. Fla�...

  • Page 102: Periodic Type Tm - Ptm

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can also be controlled with one external input pin and can drive one external output pin. Device TM Core TM No. TM Input Pin TM Output Pin HT66F01�5 10-bit PTM TM0� TM1 TCK0� TCK1 TP0� TP1 HT66F01�5 10-bit PTM TCK1 CCRP Comparator P Match 10-bit Comparator P TnPF Interr�pt...

  • Page 103: Periodic Type Tm Re�Ister Description

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Periodic Type TM Register Description Overall operation of the Periodic TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name TMnC0 TnP�U TnCK� TnCK1 TnCK0 TnON —...
  • Page 104 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TMnAL Register Name D� D� Bit 7~0 TMn CCRA Low Byte Register bit 7 ~ bit 0 TMn 10-bit CCRA bit 7 ~ bit 0 TMnAH Register Name — — — — — — D� — — — — — — — — — — — — Bit 7~2 Unimplemented, read as “0” Bit 1~0 TMn CCRA High Byte Register bit 1 ~ bit 0...
  • Page 105 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TMnC0 Register Name TnP�U TnCK� TnCK1 TnCK0 TnON — — — — — — — — — Bit 7 TnPAU: TMn Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TMn will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 TnCK2~TnCK0: Select TMn Counter clock 000: f 001: f 010: f 011: f 100: f 101: f...
  • Page 106 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TMnC1 Register Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnC�PTS TnCCLR Bit 7~6 TnM1~TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TMn. To ensure reliable operation the TMn should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TMn output pin control will be disabled. Bit 5~4 TnIO1~TnIO0: Select TPn output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of TPn or TCKn...
  • Page 107 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TnOC: TMn TPn Output control Bit 3 Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TMn output pin. Its operation depends upon whether TMn is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TMn output pin before a compare match occurs. In the PWM Mode/Single Pulse Output Mode it determines if the PWM signal is active high or active low. Bit 2 TnPOL: TMn TPn Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the TPn output pin. When the bit is set high the TMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the TMn is in the Timer/Counter Mode.

  • Page 108: Periodic Type Tm Operation Modes

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Periodic Type TM Operation Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to “0”. As the name of the mode suggests, after a comparison is made, the TMn output pin will change state. The TMn output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TMn output pin. The way in which the TMn output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TMn output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TMn output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0...
  • Page 109 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter overflow Co�nter Val�e TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 CCRP=0 Co�nter cleared by CCRP val�e 0x3FF CCRP > 0 Co�nter Res�me Restart CCRP Pa�se Stop CCR� Time TnON TnP�U TnPOL CCRP Int.
  • Page 110 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = 1; TnM [1:0] = 00 CCR� = 0 CCR� > 0 Co�nter cleared by CCR� val�e Co�nter overflow 0x3FF CCR�=0 Res�me CCR� Pa�se Stop Co�nter Restart CCRP Time TnON TnP�U TnPOL No Tn�F fla�...
  • Page 111 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TMn output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TMn output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within the TMn is useful for applications which require functions such as motor control, heating control, illumination control, etc. By providing a signal of fixed frequency but of varying duty cycle on the TMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore...
  • Page 112 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter Val�e TnM [1:0] = 10 Co�nter cleared by CCRP Co�nter Reset when TnON ret�rns hi�h CCRP Co�nter Stop if Pa�se Res�me TnON bit low CCR� Time TnON TnP�U TnPOL CCR� Int. Fla� Tn�F CCRP Int.
  • Page 113 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Single Pulse Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TMn output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TMn interrupt. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR is not used in this Mode. CCR� CCR� Leadin� Ed�e Trailin� Ed�e S/W Command S/W Command SET“TnON” CLR“TnON” TnON bit TnON bit 0 à...
  • Page 114 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter Val�e TnM [1:0] = 10 ; TnIO [1:0] = 11 Co�nter stopped by CCR� Co�nter Reset when TnON ret�rns hi�h CCR� Co�nter Stops Res�me Pa�se by software CCRP Time TnON ��to. set by...
  • Page 115 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Capture Input Mode To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPn or TCKn pin, selected by the TnCAPTS bit in the TMnC1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPn or TCKn pin the present value in the counter will be latched into the CCRA registers and a TMn interrupt generated. Irrespective of what events occur on the TPn or TCKn pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TMn interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn or TCKn pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPn or TCKn pin, however it must be noted that the counter will continue to run. As the TPn or TCKn pin is pin shared with other functions, care must be taken if the TMn is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR, TnOC and TnPOL bits are not used in this Mode. Rev. 1.50 ����st ��� �01�...
  • Page 116 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Co�nter Val�e TnM [1:0] = 01 Co�nter cleared by CCRP Co�nter Co�nter Stop Reset CCRP Res�me Pa�se Time TnON TnP�U �ctive �ctive �ctive ed�e ed�e ed�e TMn capt�re pin TPn or TCKn CCR� Int. Fla�...

  • Page 117: Analog To Digital Converter

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview These devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. It also can convert the internal signals, such as the Bandgap reference voltage, into a 12-bit digital value. The external or internal analog signal to be converted is determined by the SAINS2~SAINS0 bits together with the SACS2~SACS0 bits. Note that when the external and internal analog signals are simultaneously selected to be converted, the internal analog signal will have the priority. In the meantime the external analog signal will temporarily be switched off until the internal analog signal is deselected. More detailed information about the A/D input signal is described in the “A/D Converter Control Registers” and “A/D Converter Input Signal”...
  • Page 118 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM A/D Converter Register Description Overall operation of the A/D converter is controlled using six registers. A read only register pair exists to store the A/D Converter data 12-bit value. One register, ACERL, is used to configure the external analog input pin function. The remaining three registers are control registers which setup the operating and control function of the A/D converter. Register Name S�DOL D� — — — — (�DRFS=0) S�DOL D� D� (�DRFS=1) S�DOH D� D� (�DRFS=0) S�DOH — — — — D� (�DRFS=1) S�DC0 ST�RT �DBZ...
  • Page 119 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM A/D Converter Control Registers – SADC0, SADC1, SADC2, ACERL To control the function and operation of the A/D converter, three control registers known as SADC0, SADC1 and SADC2 are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock source as well as controlling the start function and monitoring the A/D converter busy status. As these devices contain only one actual analog to digital converter hardware circuit, each of the external and internal analog signals must be routed to the converter. The SACS2~SACS0 bits in the SADC0 register are used to determine which external channel input is selected to be converted. The SAINS2~SAINS0 bits in the SADC1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. If the SAINS2~SAINS0 bits are set to “000” or “100”, the external analog channel input will be selected to be converted and the SACS2~SACS0 bits can deternine which external channel is selected to be converted. If the SAINS2~SAINS0 bits are set to any other values except “000” and “100”, one of the internal analog signals can be selected to be converted. The internal analog signals can be derived from the A/D converter supply power, V , or internal reference voltage, V , with a specific ratio of 1, 1/2 or 1/4. If the internal analog signal is selected to be converted, the external channel signal input will automatically be switched off to avoid the signal contention. SAINS [2:0] SACS [2:0] Input Signals Description 000�...
  • Page 120 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM • SADC0 Register Name ST�RT �DBZ �DCEN �DRFS — S�CS� S�CS1 S�CS0 — — Bit 7 START: Start the A/D Conversion 0→1→0: Start This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. Bit 6 ADBZ: A/D Converter busy flag 0: No A/D conversion is in progress 1: A/D conversion is in progress This read only flag is used to indicate whether the A/D conversion is in progress or not. When the START bit is set from low to high and then to low again, the ADBZ flag will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be cleared to 0 after the A/D conversion is complete. Bit 5 ADCEN: A/D Converter function enable control 0: Disable 1: Enable This bit controls the A/D internal function. This bit should be set to one to enable the A/D converter. If the bit is set low, then the A/D converter will be switched off reducing the device power consumption. When the A/D converter function is disabled, the contents of the A/D data register pair, SADOH/SADOL, will keep unchanged.
  • Page 121 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM • SADC1 Register Name S�INS� S�INS10 S�INS0 — — S�CKS� S�CKS1 S�CKS0 — — — — Bit 7~5 SAINS2~SAINS0: A/D Converter input signal select 000, 100: External signal – External analog channel input 001: Internal signal – Internal A/D converter power supply voltage V 010: Internal signal – Internal A/D converter power supply voltage V 011: Internal signal – Internal A/D converter power supply voltage V 101: Internal signal – Internal reference voltage V 110: Internal signal – Internal reference voltage V 111: Internal signal – Internal reference voltage V When the internal analog signal is selected to be converted, the external channel input signal will automatically be switched off regardless of the SACS2~SACS0 bit field value. The internal reference voltage can be derived from various sources selected using the SAVRS3~SAVRS0 bits in the SADC2 register. Bit 4~3 Unimplemented, read as “0” Bit 2~0 SACKS2~SACKS0: A/D conversion clock source select 000: f...
  • Page 122 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM • SADC2 Register Name �DPG�EN VBGEN VREFIPS VREFPS S�VRS3 S�VRS� S�VRS1 S�VRS0 Bit 7 ADPGAEN: A/D converter PGA function enable control 0: Disable 1: Enable This bit controls the internal PGA function to provide various reference voltage for the A/D converter. When the bit is set high, the internal reference voltage, V , can be used as the internal converted signal or reference voltage by the A/D converter. If the internal reference voltage is not used by the A/D converter, then the PGA function should be properly configured to conserve power. Bit 6 VBGEN: Internal Bandgap reference voltage enable control 0: Disable 1: Enable This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit is set high, the Bandgap reference voltage can be used by the A/D converter. If the Bandgap reference voltage is not used by the A/D converter and...
  • Page 123 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM • ACERL Register Name �CE� �CE6 �CE5 �CE4 �CE3 �CE� �CE1 �CE0 Bit 7 ACE7: Define PB3 is A/D input or not 0: Not A/D input 1: A/D input, AN7 Bit 6 ACE6: Define PA7 is A/D input or not 0: Not A/D input 1: A/D input, AN6 Bit 5 ACE5: Define PA6 is A/D input or not 0: Not A/D input 1: A/D input, AN5 Bit 4 ACE4: Define PA5 is A/D input or not 0: Not A/D input 1: A/D input, AN4 Bit 3 ACE3: Define PA4 is A/D input or not 0: Not A/D input 1: A/D input, AN3 Bit 2 ACE2: Define PB2 is A/D input or not...

  • Page 124: D Operation

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins as well as other functions. The corresponding pin-shared function selection bits in the ACERL register determine which external input pins are selected as A/D converter analog channel inputs or other functional pins. If the corresponding pin is setup to be an A/D converter analog channel input, the original pin functions will be disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the port control register to enable the A/D input as when the relevant A/D input function selection bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own reference voltage input pin, VREFI. However, the reference voltage can also be supplied from the power supply pin or an internal Bandgap circuit, a choice which is made through the SAVRS3~SAVRS0 bits in the SADC2 register. The selected A/D reference voltage can be output on the VREF pin. The analog input values must not be allowed to exceed the value of V . Note that the VREFI or VREF pin function selection bit in the SADC2 register must be properly configured before the reference voltage pin function is used.

  • Page 125: Conversion Rate And Timin� Dia�Ram

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM The clock source for the A/D converter, which originates from the system clock f , can be chosen to be either f or a subdivided version of f . The division ratio value is determined by the SACKS2~SACKS0 bits in the SADC1 register. Although the A/D clock source is determined by the system clock f and by bits SACKS2~SACKS0, there are some limitations on the maximum A/D clock source speed that can be selected. As the recommended range of permissible A/D clock period, , is from 0.5μs to 10μs, care must be taken for system clock frequencies. For example, as the ADCK system clock operates at a frequency of 8MHz, the SACKS2~SACKS0 bits should not be set to 000, 001 or 111. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the devices, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. A/D Clock Period (t...

  • Page 126: S�Mmary Of �/D Conversion Steps

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM ON�ST �DCEN �/D samplin� time �/D samplin� time �DS �DS ST�RT Start of �/D conversion Start of �/D conversion Start of �/D conversion �DBZ End of �/D End of �/D conversion conversion S�CS[�:0] 011B...
  • Page 127 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Step 8 If A/D conversion interrupt is used, the interrupt control registers must be correctly configured to ensure the A/D interrupt function is active. The master interrupt bontrol bit, EMI, and the A/D conversion interrupt control bit, ADE, must both be set high in advance. Step 9 The A/D conversion procedure can now be initialized by setting the START bit from low to high and then low again. Step 10 If A/D conversion is in progress, the ADBZ flag will be set high. After the A/D conversion process is complete, the ADBZ flag will go low and then the output data can be read from SADOH and SADOL registers. Note: When checking for the end of the conversion process, if the method of polling the ADBZ bit in the SADC0 register is used, the interrupt enable step above can be omitted. Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADCEN low in the SADC0 register. When this happens, the internal A/D converter circuits will not consume power...
  • Page 128 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM A/D Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the ADBZ bit in the SADC0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an ADBZ polling method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H mov SADC1,a ; select f /8 as A/D clock and switch off V...
  • Page 129 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Example: using the interrupt method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H mov SADC1,a ; select f /8 as A/D clock and switch off V voltage set ADCEN mov a,03h ;...

  • Page 130: Serial Interface Module - Sim

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Serial Interface Module – SIM These devices contain a Serial Interface Module, which includes both the four-line SPI interface or two-line I C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and therefore the SIM interface functional pins must first be selected using the corresponding pin-shared function selection bits. As both interface types share the same pins and registers, the choice of whether the SPI or I C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O pins are selected using pull- high control registers when the SIM function is enabled and the corresponding pins are used as SIM input pins. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices.

  • Page 131: Spi Re�Isters

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM S P I M a s t e r S P I S l a v e S C K S C K S D O S D I S D I S D O...
  • Page 132 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I C function. The SIMC1 register is not used by the SPI function, only by the I C function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag, etc. SIMC0 Register Name SIM� SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN SIMICF — — Bit 7~5 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is f 001: SPI master mode; SPI clock is f /16 010: SPI master mode; SPI clock is f /64 011: SPI master mode; SPI clock is f 100: SPI master mode; SPI clock is TM1 CCRP match frequency/2 101: SPI slave mode 110: I C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting...
  • Page 133 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM SIMC2 Register Name D� CKPOLB CKEG CSEN WCOL Bit 7~6 Undefined bits These bits can be read or written by the application program. Bit 5 CKPOLB: SPI clock line base condition selection 0: The SCK line will be high when the clock is inactive. 1: The SCK line will be low when the clock is inactive. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4 CKEG: SPI SCK clock active edge type selection CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Bit 3...

  • Page 134: Spi Comm�Nication

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output a SCS signal to enable the slave devices before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI master mode will continue to function even in the IDLE1 Mode if the selected SPI clock source is running. S I M E N = 1 , C S E N = 0 ( E x t e r n a l P u l l - H i g h )
  • Page 135 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM S C S S C K ( C K P O L B = 1 ) S C K ( C K P O L B = 0 ) S D O D 7 / D 0...

  • Page 136: I C Interface

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM C Interface The I C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. V D D S D A S C L D e v i c e...
  • Page 137 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM S T A R T s i g n a l f r o m M a s t e r S e n d s l a v e a d d r e s s...
  • Page 138 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I C functions. Before the device writes data to the I C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I C bus, the device can read it from the SIMD register. Any transmission or reception of data from the I C bus must be made via the SIMD register. Name D� D� “x”: �nknown SIMA Register The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Name IIC�6 IIC�5 IIC�4 IIC�3 IIC�� IIC�1 IIC�0 “x”: �nknown...
  • Page 139 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM SIMC0 Register Name SIM� SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN SIMICF — — Bit 7~5 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is f 001: SPI master mode; SPI clock is f /16 010: SPI master mode; SPI clock is f /64 011: SPI master mode; SPI clock is f 100: SPI master mode; SPI clock is TM1 CCRP match frequency/2 101: SPI slave mode 110: I C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from TM1. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 Unimplemented, read as “0”...
  • Page 140 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM SIMC1 Register Name H��S TX�K I�MWU RX�K Bit 7 HCF: I C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6 HAAS: I C Bus address match flag 0: Not address match 1: Address match The HAAS flag is the address match flag. This flag is used to determine if the slave...

  • Page 141: I � C B�S Comm�Nication

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM RXAK: I Bit 0 C bus receive acknowledge flag 0: Slave receives acknowledge flag 1: Slave does not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is “0”, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is “1”. When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I C Bus. C Bus Communication Communication on the I C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS and SIMTOF bits to determine whether the interrupt source originates from an address match, 8-bit data transfer completion or C bus time-out occurrence. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I C bus, the microcontroller must initialise the bus, the following are steps to achieve this: • Step 1 Set the SIM2~SIM0 bits to “110” and SIMEN bit to “1” in the SIMC0 register to enable the I...
  • Page 142 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM C Bus Start Signal The START signal can only be generated by the master device connected to the I C bus and not by the slave device. This START signal will be detected by all devices connected to the I C bus. When detected, this indicates that the I C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. C Slave Address The transmission of a START signal by the master will be detected by all devices on the I C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I C bus interrupt can come from three sources, when the program enters the interrupt...
  • Page 143 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level “0”, before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. S t a r t S l a v e A d d r e s s...

  • Page 144: I � C Time-O�T Control

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM S t a r t Y e s S I M T O F = 1 S E T S I M T O E N Y e s H A A S = 1...
  • Page 145 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM S t a r t S l a v e A d d r e s s S R W A C K S C L S D A I C t i m e - o u t...

  • Page 146: Comparators

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Comparators An analog comparator is contained only within the HT66F0185 device. The comparator function offers flexibility via their register controlled features such as power-down, polarity select, hysteresis etc. In sharing their pins with normal I/O pins the comparators do not waste precious I/O pins if there functions are otherwise unused. C n P O L C n O U T C n + C n X C n - P i n - s h a r e d f u n c t i o n...
  • Page 147 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM CPC Register Name CSEL CPOL COUT CMPEG1 CMPEG0 CHYEN Bit 7 CSEL: Select Comparator pins or I/O pins 0: I/O pin selected 1: Comparator input pins C+ and C- selected This is the Comparator input pin or I/O pin select bit. If the bit is high, the comparator input pins will be enabled. As a result, these two pins will lose their I/O pin functions. Any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected. CEN: Comparator ON/Off control Bit 6 0: Off 1: On This is the Comparator on/off control bit. If the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. For power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the SLEEP or IDLE mode. CPOL: Comparator Output polarity Bit 5 0: Output not inverted 1: Output inverted This is the comparator polarity bit. If the bit is zero then the COUT bit will reflect the non-inverted output condition of the comparator. If the bit is high the comparator COUT bit will be inverted. Bit 4 COUT: Comparator Output bit CPOL = 0 0: C+ < C-...

  • Page 148: Scom/Sseg Function For Lcd

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM SCOM/SSEG Function for LCD The devices have the capability of driving external LCD panels. The common and segment pins for LCD driving, SCOM0~SCOM5 and SSEG0~SSEG19 or SSEG0~SSEG23, are pin-shared with certain pins on the I/O ports. The LCD signals, COM and SEG, are generated using the application program. LCD Operation An external LCD panel can be driven using the devices by configuring the I/O pins as common pins and segment pins. The LCD driver function is controlled using the LCD control registers which in addition to controlling the overall on/off function also controls the R-type bias current on the SCOM and SSEG pins. This enables the LCD COM and SEG driver to generate the necessary V , (1/3) , (2/3)V and V voltage levels for LCD 1/3 bias operation. The LCDEN bit in the SLCDC0 register is the overall master control for the LCD driver. This bit is used in conjunction with the COMnEN and SEGnEN bits to select which I/O pins are used for LCD driving. Note that the corresponding Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation. COMnEN COMSEGSn SCOM0/SSEG0 (�/3) V SCOM5/SSEG5 COM/SEG Voltage Analog Switch Select SSEG6...
  • Page 149 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM LCD Frames A cyclic LCD waveform includes two frames known as Frame 0 and Frame 1 for which the following offers a functional explanation. • Frame 0 To select Frame 0, clear the FRAME bit in the SLCDC 0 register to 0. In frame 0, the COM signal output can have a value of V or a V value of (1/3)×V . The SEG BIAS signal output can have a value of V or a V value of (2/3)×V BIAS • Frame 1 To select Frame 1, set the FRAME bit in the SLCDC0 register to 1.

  • Page 150: Lcd Control Re�Isters

    SEG11EN SEG10EN SEG9EN SEG�EN SEG�EN SEG6EN SLCDC3 — — SEG19EN SEG1�EN SEG1�EN SEG16EN SEG15EN SEG14EN LCD Driver Control Registers List – HT66F0175 Register Name SLCDC0 FR�ME ISEL1 ISEL0 LCDEN COM3EN COM�EN COM1EN COM0EN SLCDC1 COM5EN COM4EN COMSEGS5 COMSEGS4 COMSEGS3 COMSEGS� COMSEGS1 COMSEGS0 SLCDC�...
  • Page 151 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM COM1EN: SCOM1/SSEG1 or other pin function select Bit 1 0: Other pin-shared functions 1: SCOM1/SSEG1 function COM0EN: SCOM0/SSEG0 or other pin function select Bit 0 0: Other pin-shared functions 1: SCOM0/SSEG0 function SLCDC1 Register Name COM5EN COM4EN COMSEGS5 COMSEGS4 COMSEGS3 COMSEGS� COMSEGS1 COMSEGS0 Bit 7 COM5EN: SCOM5/SSEG5 or other pin function select 0: Other pin-shared functions 1: SCOM5/SSEG5 function Bit 6 COM4EN: SCOM4/SSEG4 or other pin function select 0: Other pin-shared functions 1: SCOM4/SSEG4 function Bit 5 COMSEGS5: SCOM5 or SSEG5 pin function select 0: SCOM5 1: SSEG5 Bit 4 COMSEGS4: SCOM4 or SSEG4 pin function select 0: SCOM4...
  • Page 152 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM SLCDC2 Register Name SEG13EN SEG1�EN SEG11EN SEG10EN SEG9EN SEG�EN SEG�EN SEG6EN Bit 7 SEG13EN: SSEG13 pin function select 0: Other pin-shared functions 1: SSEG13 function Bit 6 SEG12EN: SSEG12 pin function select 0: Other pin-shared functions 1: SSEG12 function Bit 5 SEG11EN: SSEG11 pin function select 0: Other pin-shared functions 1: SSEG11 function Bit 4 SEG10EN: SSEG10 pin function select 0: Other pin-shared functions 1: SSEG10 function Bit 3 SEG9EN: SSEG9 pin function select 0: Other pin-shared functions 1: SSEG9 function Bit 2 SEG8EN: SSEG8 pin function select 0: Other pin-shared functions...
  • Page 153 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM SLCDC3 Register – HT66F0175 Name — — SEG19EN SEG1�EN SEG1�EN SEG16EN SEG15EN SEG14EN — — — — Bit 7~6 Unimplemented, read as “0” SEG19EN: SSEG19 pin function select Bit 5 0: Other pin-shared functions 1: SSEG19 function Bit 4 SEG18EN: SSEG18 pin function select 0: Other pin-shared functions 1: SSEG18 function Bit 3 SEG17EN: SSEG17 pin function select 0: Other pin-shared functions 1: SSEG17 function Bit 2 SEG16EN: SSEG16 pin function select 0: Other pin-shared functions...
  • Page 154 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM SLCDC3 Register – HT66F0185 Name SEG�1EN SEG�0EN SEG19EN SEG1�EN SEG1�EN SEG16EN SEG15EN SEG14EN Bit 7 SEG21EN: SSEG21 pin function select 0: Other pin-shared functions 1: SSEG21 function Bit 6 SEG20EN: SSEG20 pin function select 0: Other pin-shared functions 1: SSEG20 function Bit 5 SEG19EN: SSEG19 pin function select 0: Other pin-shared functions 1: SSEG19 function Bit 4 SEG18EN: SSEG18 pin function select 0: Other pin-shared functions 1: SSEG18 function Bit 3 SEG17EN: SSEG17 pin function select 0: Other pin-shared functions 1: SSEG17 function Bit 2...

  • Page 155: Uart Interface

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM UART Interface The UART interface module is only contained in the HT66F0185 device. The HT66F0185 device contains an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features: • Full-duplex, asynchronous communication • 8 or 9 bits character length • Even, odd or no parity options • One or two stop bits • Baud rate generator with 8-bit prescaler • Parity, framing, noise and overrun error detection • Support for interrupt on address detect (last character bit=1) • Separately enabled transmitter and receiver • 2-byte Deep FIFO Receive Data Buffer • Transmit and receive interrupts • Interrupts can be initialized by the following conditions: Transmitter Empty ♦...

  • Page 156: U�Rt External Pin

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM UART External Pin To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX and RX pins are respectively the UART transmitter and receiver pins which are pin-shared with I/O or other pin-shared functions. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the TX and RX pins. When the TX or RX pin function is disabled by clearing the UARTEN, TXEN or RXEN bit, the TX or RX pin will be used as I/O or other pin-shared functional pin depending upon the pin-shared function priority. UART Data Transfer Scheme The above diagram shows the overall data transfer structure arrangement for the UART interface. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. Only the TXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory. This shared register known as the TXR_RXR register is used for both data transmission and data reception. UART Status and Control Registers There are five control registers associated with the UART function. The USR, UCR1 and UCR2...
  • Page 157 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TXR_RXR Register The TXR_RXR register is the data register which is used to store the data to be transmitted on the TX pin or being received from the RX pin. Name TXRX� TXRX6 TXRX5 TXRX4 TXRX3 TXRX� TXRX1 TXRX0 “x”: �nknown Bit 7~0 TXRX7~TXRX0: UART Transmit/Receive Data bits USR Register The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only and further...
  • Page 158 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM OERR: Overrun error flag Bit 4 0: No overrun error is detected 1: Overrun error is detected The OERR flag is the overrun error flag which indicates when the receiver buffer has overflowed. When this read only flag is “0”, it indicates that there is no overrun error. When the flag is “1”, it indicates that an overrun error occurs which will inhibit further transfers to the RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an access to the RXR data register. RIDLE: Receiver status Bit 3 0: Data reception is in progress (data being received) 1: No data reception is in progress (receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is “0”, it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is “1”, it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is “1” indicating that the UART receiver is idle and the RX pin stays in logic high condition. Bit 2 RXIF: Receive RXR data register status 0: RXR data register is empty 1: RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is “0”, it indicates that the RXR read data register is empty. When the flag is “1”, it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available.
  • Page 159 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM UCR1 Register The UCR1 register together with the UCR2 register are the UART control registers that are used to set the various options for the UART function such as overall on/off control, parity control, data transfer bit length, etc. Further explanation on each of the bits is given below. Name U�RTEN PREN STOPS TXBRK RX� TX� “x”: �nknown Bit 7 UARTEN: UART function enable control 0: Disable UART; TX and RX pins are used as other pin-shared functional pins. 1: Enable UART; TX and RX pins can function as UART pins defined by TXEN and RXEN bits The UARTEN bit is the UART enable bit. When this bit is equal to “0”, the UART will be disabled and the RX pin as well as the TX pin will be other pin-shared functional pins. When the bit is equal to “1”, the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. Bit 6 BNO: Number of data transfer bits selection 0: 8-bit data transfer...
  • Page 160 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TXBRK: Transmit break character Bit 2 0: No break character is transmitted 1: Break characters transmit The TXBRK bit is the Transmit Break Character bit. When this bit is equal to “0”, there are no break characters and the TX pin operats normally. When the bit is equal to “1”, there are transmit break characters and the transmitter will send logic zeros. When this bit is equal to “1”, after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. Bit 1 RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9 bit of the received data known as RX8. The BNO bit is used to determine whether data transfes are in 8-bit or 9-bit format. Bit 0 TX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9 bit of the transmitted data known as TX8. The BNO bit is used to determine whether data transfes are in 8-bit or 9-bit format. UCR2 Register The UCR2 register is the second of the UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation if the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up function enable and the address detect function enable.
  • Page 161 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM BRGH: Baud Rate speed selection Bit 5 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the baud rate register, BRG, controls the baud rate of the UART. If the bit is equal to 0, the low speed mode is selected. Bit 4 ADDEN: Address detect function enable control 0: Address detection function is disabled 1: Address detection function is enabled The bit named ADDEN is the address detection function enable control bit. When this bit is equal to 1, the address detection function is enabled. When it occurs, if the 8 bit, which corresponds to RX7 if BNO=0, or the 9 bit, which corresponds to RX8 if BNO=1, has a value of “1”, then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8 or 9 bit depending on the value of the BNO bit. If the address bit known as the 8 or 9 bit of the received word is “0” with the address detection function being enabled, an interrupt will not be generated and the received data will be discarded. WAKE: RX pin falling edge wake-up function enable control Bit 3 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled The bit enables or disables the receiver wake-up function. If this bit is equal to 1 and the device is in IDLE0 or SLEEP mode, a falling edge on the RX pin will wake up the device. If this bit is equal to 0 and the device is in the power down mode, any edge transitions on the RX pin will not wake up the device. RIE: Receiver interrupt enable control Bit 2 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled The bit enables or disables the receiver interrupt. If this bit is equal to 1 and when the...
  • Page 162 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Baud Rate Generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit counter, the period of which is determined by two factors. The first of these is the value placed in the BRG register and the second is the value of the BRGH bit within the UCR2 control register. The BRGH bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value in the BRG register, N, which is used in the following baud rate calculation formula determines the division factor. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit Ba�d Rate (BR) [64(N+1)] [16(N+1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. BRG Register Name BRG� BRG6 BRG5 BRG4 BRG3 BRG� BRG1 BRG0 “x”: �nknown...

  • Page 163: U�Rt Set�P And Control

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM UART Setup and Control For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits and one or two stop bits. Parity is supported by the UART hardware and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the transmitter and receiver of the UART are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Enabling/Disabling the UART Interface The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX pin, then it will default to a logic high value. Clearing the UARTEN bit will disable the TX and RX pins and these two pins will be used as I/ O or other pin-shared functional pins. When the UART function is disabled, the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the enable control, the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the...

  • Page 164: U�Rt Transmitter

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. N e x t P a r i t y B i t S t a r t S t a r t B i t B i t 0...

  • Page 165: U�Rt Receiver

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM This sequence of events can now be repeated to send additional data. It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set, then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: 1. A USR register access 2. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. Transmitting Break If the TXBRK bit is set, then the break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13xN “0” bits, where N=1, 2, etc. If a break character is to be transmitted, then the TXBRK bit must be first set by the application program and then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level, then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic high at the end of the last break character will ensure that the start bit of the next frame is recognized. UART Receiver The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9 bit, which is the MSB, will be stored in the RX8 bit in the UCR1 register. At the receiver core lies the Receiver Shift Register more commonly known as the RSR. The data which...
  • Page 166 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM byte has been completely shifted in, otherwise the 3 byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the RXEN bit to ensure that the UART receiver is enabled and the RX pin is used as a UART receiver pin. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received, the following sequence of events will occur: • The RXIF bit in the USR register will be set then RXR register has data available, at least one more character can be read. • When the contents of the shift register have been transferred to the RXR register and if the RIE bit is set, then an interrupt will be generated. • If during reception, a frame error, noise error, parity error or an overrun error has been detected, then the error flags can be set. The RXIF bit can be cleared using the following software sequence: 1. A USR register access 2. A RXR register read execution Receiving Break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the...
  • Page 167 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Receiver Interrupt The read only receive interrupt flag, RXIF, in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1. Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – OERR The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a 3 byte can continue to be received. Before the 3 byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: • The OERR flag in the USR register will be set. • The RXR contents will not be lost. • The shift register will be overwritten. • An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register. Noise Error – NF Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is...
  • Page 168 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM UART Interrupt Structure Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if its corresponding interrupt control is enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. Four of these conditions have the corresponding USR register flags which will generate a UART interrupt if its associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt...

  • Page 169: U�Rt Power Down And Wake-�P

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Address Detect Mode Setting the Address Detect function enable control bit, ADDEN, in the UCR2 register, enables this special function. If this bit is set to 1, then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is equal to 1, then when the data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the related interrupt enable control bit and the EMI bit of the microcontroller must also be enabled for correct interrupt generation. The highest address bit is the bit if the bit BNO=1 or the 8 bit if the bit BNO=0. If the highest bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is equal to 0, then a Receive Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last but status. The address detection and parity functions are mutually exclusive functions. Therefore, if the address detect function is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity function enable bit PREN to zero. Bit 9 if BNO=1 UART Interrupt ADDEN Bit 8 if BNO=0 Generated √ √ √ ADDEN Bit Function UART Power Down and Wake-up When the MCU system clock is switched off, the UART will cease to function. If the MCU executes...

  • Page 170: Low Voltage Detector - Lvd

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, V , and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the V voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Name — — LVDO LVDEN — VLVD� VLVD1 VLVD0 —...

  • Page 171: Lvd Operation

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, V , with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, V , falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay t should be allowed for the circuitry to stabilise before reading the LVDS LVDO bit. Note also that as the V voltage may rise and fall rather slowly, at the voltage nears that of V , there may be multiple bit LVDO transitions. V D D L V D L V D E N L V D O L V D S...
  • Page 172 SIMF — — EEPROM write operation — TnPE TnPF n = 0~1 Tn�E Tn�F n = 0~1 Interrupt Register Bit Naming Conventions – HT66F0175 Function Enable Bit Request Flag Notes Global — — INTn Pins INTnE INTnF n = 0 ~ 1 Comparator —...
  • Page 173 — — T0�E T0PE MFI1 — — T1�F T1PF — — T1�E T1PE MFI� — — — — Interrupt Registers List – HT66F0175 Register Name INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — MF0F INT0F MF0E INT0E...
  • Page 174 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM INTC0 Register – HT66F0175 Name — MF0F — INT0F MF0E — INT0E — — — — — — Bit 7 Unimplemented, read as “0” MF0F: Multi-function 0 interrupt request flag Bit 6 0: No request 1: Interrupt request Bit 5 Unimplemented, read as “0” INT0F: INT0 interrupt request flag Bit 4 0: No request 1: Interrupt request MF0E: Multi-function 0 interrupt control Bit 3 0: Disable 1: Enable Bit 2 Unimplemented, read as “0”...
  • Page 175 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM INTC1 Register Name TB0F �DF MF�F MF1F TB0E �DE MF�E MF1E Bit 7 TB0F: Time Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 6 ADF: A/D Converter interrupt request flag 0: No request 1: Interrupt request Bit 5 MF2F: Multi-function 2 interrupt request flag 0: No request 1: Interrupt request Bit 4 MF1F: Multi-function 1 interrupt request flag 0: No request 1: Interrupt request Bit 3 TB0E: Time Base 0 interrupt control 0: Disable 1: Enable Bit 2 ADE: A/D Converter interrupt control 0: Disable...
  • Page 176 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM INTC2 Register – HT66F0175 Name — SIMF INT1F TB1F — SIME INT1E TB1E — — — — Bit 7 Unimplemented, read as “0” SIMF: SIM interrupt request flag Bit 6 0: No request 1: Interrupt request Bit 5 INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request Bit 4 TB1F: Time Base 1 interrupt request flag 0: No request 1: Interrupt request Bit 3 Unimplemented, read as “0” Bit 2...
  • Page 177 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM INTC2 Register – HT66F0185 Name SIMF INT1F TB1F SIME INT1E TB1E Bit 7 URF: UART interrupt request flag 0: No request 1: Interrupt request Bit 6 SIMF: SIM interrupt request flag 0: No request 1: Interrupt request Bit 5 INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request Bit 4 TB1F: Time Base 1 interrupt request flag 0: No request 1: Interrupt request Bit 3 URE: UART interrupt control 0: Disable 1: Enable Bit 2 SIME: SIM interrupt control 0: Disable...
  • Page 178 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM MFI1 Register – HT66F0175 Name — — T1�F T1PF — — T1�E T1PE — — — — — — — — Bit 7~6 Unimplemented, read as “0” T1AF: TM1 Comparator A match Interrupt request flag Bit 5 0: No request 1: Interrupt request Bit 4 T1PF: TM1 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” T1AE: TM1 Comparator A match Interrupt control...
  • Page 179 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM MFI2 Register Name — — — — — — — — — — — — Bit 7~6 Unimplemented, read as “0” DEF: Data EEPROM Interrupt request flag Bit 5 0: No request 1: Interrupt request Bit 4 LVF: LVD Interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” DEE: Data EEPROM Interrupt control Bit 1 0: Disable 1: Enable Bit 0 LVE: LVD Interrupt control 0: Disable...
  • Page 180 TB1E �0H Interr�pts contained within INT1 Pin INT1F INT1E �4H M�lti-F�nction Interr�pts SIMF SIME ��H Interrupt Scheme – HT66F0175 EMI a�to disabled in ISR Legend Req�est Fla�� no a�to reset in ISR Interr�pt Req�est Enable Master Priority Vector Name Fla�s...

  • Page 181: External Interr

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM External Interrupt The external interrupts are controlled by signal transitions on the pins INT0~INT1. An external interrupt request will take place when the external interrupt request flags, INT0F~INT1F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT1E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set and the external interrupt pin is selected by the corresponding pin-shared function selection bits. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Comparator Interrupt – HT66F0185 The comparator interrupt is controlled by the internal comparator. A comparator interrupt request will take place when the comparator interrupt request flag, CPF, is set, a situation that will occur when the comparator output changes state. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and comparator interrupt enable bit, CPE, must first be set. When the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. When the interrupt is serviced, the comparator interrupt request flag, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Multi-function Interrupt Within the device there are up to three Multi-function interrupts. Unlike the other independent...
  • Page 182 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM A/D Converter Interrupt The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Time Base Interrupt The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources...
  • Page 183 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TBC Register Name TBON TBCK TB11 TB10 LXTLP TB0� TB01 TB00 Bit 7 TBON: Time Base function enable control 0: Disable 1: Enable Bit 6 TBCK: Time Base clock source select 0: f 1: f Bit 5~4 TB11~TB10: Time Base 1 time-out period selection 00: 2 01: 2 10: 2 11: 2 Bit 3 LXTLP: LXT Low Power control 0: Disable – LXT quick start-up 1: Enable – LXT slow start-up Bit 2~0 TB02~TB00: Time Base 0 time-out period selection 000: 2 001: 2 010: 2...

  • Page 184: Lvd Interr

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. However, only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program. EEPROM Interrupt The EEPROM Write Interrupt is contained within the Multi-function Interrupt. An EEPROM Write Interrupt request will take place when the EEPROM Write Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective...
  • Page 185 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though these devices are in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program.

  • Page 186: Configuration Options

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. Options Hi�h Speed System Oscillator Selection – HXT or HIRC Low Speed System Oscillator Selection � – LXT or LIRC HIRC Freq�ency Selection – �MHz� 1�MHz or 16MHz...

  • Page 187: Instruction Set

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of several kinds of MOV instructions, data can be transferred from registers...

  • Page 188: Branches And Control Transfer

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such...

  • Page 189: Instruction Set Summary

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic �DD ��[m] �dd Data Memory to �CC Z� C� �C� OV �DDM ��[m] �dd �CC to Data Memory Note Z�...
  • Page 190 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Mnemonic Description Cycles Flag Affected Data Move MOV ��[m] Move Data Memory to �CC None MOV [m]�� Move �CC to Data Memory Note None MOV ��x Move immediate data to �CC None Bit Operation CLR [m].i...

  • Page 191: Instruction Definition

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Instruction Definition Add Data Memory to ACC with Carry ADC A,[m] Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s) OV, Z, AC, C ADD A,x...
  • Page 192 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Operation Stack ← Program Counter + 1 Program Counter ← addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ← 00H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i ← 0 Affected flag(s) None CLR WDT Clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared.
  • Page 193 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM CPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ← [m] Affected flag(s) DAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H Affected flag(s) DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. Operation [m] ← [m] − 1...
  • Page 194 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Operation Program Counter ← addr Affected flag(s) None MOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ← [m] Affected flag(s) None MOV A,x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator. Operation ACC ← x Affected flag(s) None MOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory.
  • Page 195 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM RET A,x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Operation Program Counter ← Stack ACC ← x Affected flag(s) None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Operation Program Counter ← Stack EMI ← 1 Affected flag(s) None RL [m] Rotate Data Memory left Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. Operation [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 Affected flag(s) None RLA [m]...
  • Page 196 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM RRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 Affected flag(s) None Rotate Data Memory right through Carry RRC [m] Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 Affected flag(s) RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0...
  • Page 197 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM SDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC ← [m] − 1 Skip if ACC=0 Affected flag(s) None Set Data Memory SET [m] Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i ← 1 Affected flag(s) None Skip if increment Data Memory is 0 SIZ [m] Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the...
  • Page 198 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − x Affected flag(s) OV, Z, AC, C SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 ↔ [m].7~[m].4 Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The...
  • Page 199 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM TABRD [m] Read table (specific page) to TBLH and Data Memory Description The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDC [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None XOR A,[m]...

  • Page 200: Package Information

    HT66F0175/HT66F0185 A/D Flash MCU with EEPROM Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.50 �00 ����st ��� �01�...
  • Page 201 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM 20-pin SOP (300mil) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. � — 0.406 BSC — — 0.�95 BSC — 0.01� — 0.0�0 C’ — 0.504 BSC — — — 0.104 — 0.050 BSC —...
  • Page 202 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM 20-pin SSOP (150mil) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. � — 0.�36 BSC — — 0.154 BSC — 0.00� — 0.01� C’ — 0.341 BSC — — — 0.069 — 0.0�5 BSC —...
  • Page 203 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM 24-pin SOP (300mil) Outline Dimensions " Dimensions in inch Symbol Min. Nom. Max. � — 0.406 BSC — — 0.�95 BSC — 0.01� — 0.0�0 C’ — 0.606 BSC — — — 0.104 —...
  • Page 204 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM 24-pin SSOP (150mil) Outline Dimensions " Dimensions in inch Symbol Min. Nom. Max. � — 0.�36 BSC — — 0.154 BSC — 0.00� — 0.01� C’ — 0.341 BSC — — — 0.069 —...
  • Page 205 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM 28-pin SOP (300mil) Outline Dimensions &  " Dimensions in inch Symbol Min. Nom. Max. � — 0.406 BSC — — 0.�95 BSC — 0.01� — 0.0�0 C’ — 0.�05 BSC — — —...
  • Page 206 HT66F0175/HT66F0185 A/D Flash MCU with EEPROM 28-pin SSOP (150mil) Outline Dimensions &  " Dimensions in inch Symbol Min. Nom. Max. � — 0.�36 BSC — — 0.154 BSC — 0.00� — 0.01� C’ — 0.390 BSC — — —...
  • Page 207 However� Holtek ass�mes no responsibility arisin� from the �se of the specifications described. The applications mentioned herein are used solely for the p�rpose of ill�stration and Holtek makes no warranty or representation that s�ch applications will be s�itable witho�t f�rther modification� nor recommends the �se of its prod�cts for application that may present a risk to h�man life d�e to...

This manual is also suitable for:

Ht66f0185

Table of Contents